{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,25]],"date-time":"2026-04-25T08:38:39Z","timestamp":1777106319481,"version":"3.51.4"},"reference-count":32,"publisher":"Association for Computing Machinery (ACM)","issue":"8","license":[{"start":{"date-parts":[[2022,7,21]],"date-time":"2022-07-21T00:00:00Z","timestamp":1658361600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-sa\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["Commun. ACM"],"published-print":{"date-parts":[[2022,8]]},"abstract":"<jats:p>The network interface cards (NICs) of modern computers are changing to adapt to faster data rates and to help with the scaling issues of general-purpose CPU technologies. Among the ongoing innovations, the inclusion of programmable accelerators on the NIC's data path is particularly interesting, since it provides the opportunity to offload some of the CPU's network packet processing tasks to the accelerator. Given the strict latency constraints of packet processing tasks, accelerators are often implemented leveraging platforms such as Field-Programmable Gate Arrays (FPGAs). FPGAs can be re-programmed after deployment, to adapt to changing application requirements, and can achieve both high throughput and low latency when implementing packet processing tasks. However, they have limited resources that may need to be shared among diverse applications, and programming them is difficult and requires hardware design expertise.<\/jats:p>\n          <jats:p>We present hXDP, a solution to run on FPGAs software packet processing tasks described with the eBPF technology and targeting the Linux's eXpress Data Path. hXDP uses only a fraction of the available FPGA resources, while matching the performance of high-end CPUs. The iterative execution model of eBPF is not a good fit for FPGA accelerators. Nonetheless, we show that many of the instructions of an eBPF program can be compressed, parallelized, or completely removed, when targeting a purpose-built FPGA design, thereby significantly improving performance.<\/jats:p>\n          <jats:p>We implement hXDP on an FPGA NIC and evaluate it running real-world unmodified eBPF programs. Our implementation runs at 156.25MHz and uses about 15% of the FPGA resources. Despite these modest requirements, it can run dynamically loaded programs, achieves the packet processing throughput of a high-end CPU core, and provides a 10X lower packet forwarding latency.<\/jats:p>","DOI":"10.1145\/3543668","type":"journal-article","created":{"date-parts":[[2022,7,21]],"date-time":"2022-07-21T16:21:39Z","timestamp":1658420499000},"page":"92-100","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":41,"title":["hXDP"],"prefix":"10.1145","volume":"65","author":[{"given":"Marco Spaziani","family":"Brunella","sequence":"first","affiliation":[{"name":"Axbryd\/University of Rome Tor Vergata, Rome, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giacomo","family":"Belocchi","sequence":"additional","affiliation":[{"name":"Axbryd\/University of Rome Tor Vergata, Rome, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marco","family":"Bonola","sequence":"additional","affiliation":[{"name":"Axbryd\/CNIT, Rome, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Salvatore","family":"Pontarelli","sequence":"additional","affiliation":[{"name":"Axbryd\/University of Rome La Sapienza, Rome, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giuseppe","family":"Siracusano","sequence":"additional","affiliation":[{"name":"NEC Laboratories Europe, Heidelberg, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giuseppe","family":"Bianchi","sequence":"additional","affiliation":[{"name":"University of Rome Tor Vergata, Rome, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Aniello","family":"Cammarano","sequence":"additional","affiliation":[{"name":"Axbryd, Rome, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alessandro","family":"Palumbo","sequence":"additional","affiliation":[{"name":"University of Rome Tor Vergata, Rome, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Petrucci","sequence":"additional","affiliation":[{"name":"University of Rome Tor Vergata, Rome, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Roberto","family":"Bifulco","sequence":"additional","affiliation":[{"name":"NEC Laboratories Europe, Heidelberg, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2022,7,21]]},"reference":[{"key":"e_1_2_1_1_1","unstructured":"P4-NetFPGA. https:\/\/github.com\/NetFPGA\/P4-NetFPGA-public\/wiki.  P4-NetFPGA. https:\/\/github.com\/NetFPGA\/P4-NetFPGA-public\/wiki."},{"key":"e_1_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1966.264565"},{"key":"e_1_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2656877.2656890"},{"key":"e_1_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2486001.2486011"},{"key":"e_1_2_1_5_1","first-page":"9","article-title":"A VLIW packet manipulator processor. In 2018 European Conference on Networks and Communications (EuCNC)","volume":"1","author":"Brunella M.S.","year":"2018","unstructured":"Brunella , M.S. , Pontarelli , S. , Bonola , M. , Bianchi , G. V-PMP : A VLIW packet manipulator processor. In 2018 European Conference on Networks and Communications (EuCNC) , IEEE , 2018 , 1 -- 9 . Brunella, M.S., Pontarelli, S., Bonola, M., Bianchi, G. V-PMP: A VLIW packet manipulator processor. In 2018 European Conference on Networks and Communications (EuCNC), IEEE, 2018, 1--9.","journal-title":"IEEE"},{"key":"e_1_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.5555\/3195638.3195647"},{"key":"e_1_2_1_7_1","volume-title":"13th USENIX Symposium on Operating Systems Design and Implementation (OSDI 18)","author":"Chen T.","year":"2018","unstructured":"Chen , T. , Moreau , T. , Jiang , Z. , Zheng , L. , Yan , E. , Shen , H. , Cowan , M. , Wang , L. , Hu , Y. , Ceze , L. , Guestrin , C. , Krishnamurthy , A. TVM : An automated end-to-end optimizing compiler for deep learning . In 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI 18) , USENIX Association, Carlsbad, CA , 2018 , 578--594. Chen, T., Moreau, T., Jiang, Z., Zheng, L., Yan, E., Shen, H., Cowan, M., Wang, L., Hu, Y., Ceze, L., Guestrin, C., Krishnamurthy, A. TVM: An automated end-to-end optimizing compiler for deep learning. In 13th USENIX Symposium on Operating Systems Design and Implementation (OSDI 18), USENIX Association, Carlsbad, CA, 2018, 578--594."},{"key":"e_1_2_1_8_1","first-page":"124","article-title":"The microsoft catapult project. In 2017 IEEE International Symposium on Workload Characterization (IISWC)","volume":"124","author":"Chiou D","year":"2017","unstructured":"Chiou , D . The microsoft catapult project. In 2017 IEEE International Symposium on Workload Characterization (IISWC) , IEEE , 2017 , 124 -- 124 . Chiou, D. The microsoft catapult project. In 2017 IEEE International Symposium on Workload Characterization (IISWC), IEEE, 2017, 124--124.","journal-title":"IEEE"},{"key":"e_1_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373360.3380836"},{"key":"e_1_2_1_10_1","volume-title":"Katran source code repository","author":"Facebook","year":"2018","unstructured":"Facebook . Facebook. Katran source code repository , 2018 . https:\/\/github.com\/facebookincubator\/katran. Facebook. Facebook. Katran source code repository, 2018. https:\/\/github.com\/facebookincubator\/katran."},{"key":"e_1_2_1_11_1","volume-title":"15th USENIX Symposium on Networked Systems Design and Implementation (NSDI 18)","author":"Firestone D.","year":"2018","unstructured":"Firestone , D. , Putnam , A. , Mundkur , S. , Chiou , D. , Dabagh , A. , Andrewartha , M. , Angepat , H. , Bhanu , V. , Caulfield , A. , Chung , E. , Chandrappa , H.K. , Chaturmohta , S. , Humphrey , M. , Lavier , J. , Lam , N. , Liu , F. , Ovtcharov , K. , Padhye , J. , Popuri , G. , Raindel , S. , Sapre , T. , Shaw , M. , Silva , G. , Sivakumar , M. , Srivastava , N. , Verma , A. , Zuhair , Q. , Bansal , D. , Burger , D. , Vaid , K. , Maltz , D.A. , Greenberg , A. Azure accelerated networking: Smartnics in the public cloud . In 15th USENIX Symposium on Networked Systems Design and Implementation (NSDI 18) , Renton, WA, USENIX Association , 2018 , 51--66. Firestone, D., Putnam, A., Mundkur, S., Chiou, D., Dabagh, A., Andrewartha, M., Angepat, H., Bhanu, V., Caulfield, A., Chung, E., Chandrappa, H.K., Chaturmohta, S., Humphrey, M., Lavier, J., Lam, N., Liu, F., Ovtcharov, K., Padhye, J., Popuri, G., Raindel, S., Sapre, T., Shaw, M., Silva, G., Sivakumar, M., Srivastava, N., Verma, A., Zuhair, Q., Bansal, D., Burger, D., Vaid, K., Maltz, D.A., Greenberg, A. Azure accelerated networking: Smartnics in the public cloud. In 15th USENIX Symposium on Networked Systems Design and Implementation (NSDI 18), Renton, WA, USENIX Association, 2018, 51--66."},{"key":"e_1_2_1_12_1","unstructured":"FlowBlaze. Repository with FlowBlaze source code and additional material. http:\/\/axbryd.com\/FlowBlaze.html.  FlowBlaze. Repository with FlowBlaze source code and additional material. http:\/\/axbryd.com\/FlowBlaze.html."},{"key":"e_1_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM48280.2020.00015"},{"key":"e_1_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2654506"},{"key":"e_1_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00059"},{"key":"e_1_2_1_16_1","first-page":"8","article-title":"A catalog and in-hardware evaluation of open-source drop-in compatible risc-v softcore processors. In 2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","volume":"1","author":"Heinz C.","year":"2019","unstructured":"Heinz , C. , Lavan , Y. , Hofmann , J. , Koch , A . A catalog and in-hardware evaluation of open-source drop-in compatible risc-v softcore processors. In 2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig) , IEEE , 2019 , 1 -- 8 . Heinz, C., Lavan, Y., Hofmann, J., Koch, A. A catalog and in-hardware evaluation of open-source drop-in compatible risc-v softcore processors. In 2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2019, 1--8.","journal-title":"IEEE"},{"key":"e_1_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/3282307"},{"key":"e_1_2_1_18_1","first-page":"212","article-title":"Demystifying the performance of XDP BPF. In 2019 IEEE Conference on Network Softwarization (NetSoft)","volume":"208","author":"Hohlfeld O.","year":"2019","unstructured":"Hohlfeld , O. , Krude , J. , Reelfs , J.H. , R\u00fcth , J. , Wehrle , K . Demystifying the performance of XDP BPF. In 2019 IEEE Conference on Network Softwarization (NetSoft) , IEEE , 2019 , 208 -- 212 . Hohlfeld, O., Krude, J., Reelfs, J.H., R\u00fcth, J., Wehrle, K. Demystifying the performance of XDP BPF. In 2019 IEEE Conference on Network Softwarization (NetSoft), IEEE, 2019, 208--212.","journal-title":"IEEE"},{"key":"e_1_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/3281411.3281443"},{"key":"e_1_2_1_20_1","unstructured":"Intel. 5g wireless. 2020 https:\/\/www.intel.com\/content\/www\/us\/en\/communications\/products\/programmable\/applications\/baseband.html.  Intel. 5g wireless. 2020 https:\/\/www.intel.com\/content\/www\/us\/en\/communications\/products\/programmable\/applications\/baseband.html."},{"key":"e_1_2_1_21_1","first-page":"24","article-title":"A reconfigurable vliw processor using FPGAs. In [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines","volume":"17","author":"Iseli C.","year":"1993","unstructured":"Iseli , C. , Sanchez , E. Spyder : A reconfigurable vliw processor using FPGAs. In [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines . IEEE , 1993 , 17 -- 24 . Iseli, C., Sanchez, E. Spyder: A reconfigurable vliw processor using FPGAs. In [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines. IEEE, 1993, 17--24.","journal-title":"IEEE"},{"key":"e_1_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046207"},{"key":"e_1_2_1_23_1","volume-title":"15th Workshop on Hot Topics in Operating Systems (HotOS XV)","author":"Kaufmann A.","year":"2015","unstructured":"Kaufmann , A. , Peter , S. , Anderson , T. , Krishnamurthy , A. Flexnic : Rethinking network DMA . In 15th Workshop on Hot Topics in Operating Systems (HotOS XV) , Kartause Ittingen, Switzerland, USENIX Association , 2015 . Kaufmann, A., Peter, S., Anderson, T., Krishnamurthy, A. Flexnic: Rethinking network DMA. In 15th Workshop on Hot Topics in Operating Systems (HotOS XV), Kartause Ittingen, Switzerland, USENIX Association, 2015."},{"key":"e_1_2_1_24_1","first-page":"1","article-title":"eBPF hardware offload to SmartNICs: cls bpf and XDP","author":"Kicinski J.","year":"2016","unstructured":"Kicinski , J. , Viljoen , N . eBPF hardware offload to SmartNICs: cls bpf and XDP . Proc. Netdev 1 , 2016 . Kicinski, J., Viljoen, N. eBPF hardware offload to SmartNICs: cls bpf and XDP. Proc. Netdev 1, 2016.","journal-title":"Proc. Netdev"},{"key":"e_1_2_1_25_1","volume-title":"The programmable data plane: Abstractions, architectures, algorithms, and applications. 54, 4","author":"Michel O.","year":"2021","unstructured":"Michel , O. , Bifulco , R. , R\u00e9tv\u00e1ri , G. , Schmid , S. The programmable data plane: Abstractions, architectures, algorithms, and applications. 54, 4 ( 2021 ). Michel, O., Bifulco, R., R\u00e9tv\u00e1ri, G., Schmid, S. The programmable data plane: Abstractions, architectures, algorithms, and applications. 54, 4 (2021)."},{"key":"e_1_2_1_26_1","unstructured":"NEC. Building an Open vRAN Ecosystem White Paper. 2020. https:\/\/www.nec.com\/en\/global\/solutions\/5g\/index.html.  NEC. Building an Open vRAN Ecosystem White Paper. 2020. https:\/\/www.nec.com\/en\/global\/solutions\/5g\/index.html."},{"key":"e_1_2_1_27_1","unstructured":"Netronome. AgilioTM CX 2x40GbE intelligent server adapter. https:\/\/www.netronome.com\/media\/redactor_files\/PB_Agilio_CX_2x40GbE.pdf.  Netronome. AgilioTM CX 2x40GbE intelligent server adapter. https:\/\/www.netronome.com\/media\/redactor_files\/PB_Agilio_CX_2x40GbE.pdf."},{"key":"e_1_2_1_28_1","volume-title":"16th USENIX Symposium on Networked Systems Design and Implementation (NSDI 19)","author":"Pontarelli S.","year":"2019","unstructured":"Pontarelli , S. , Bifulco , R. , Bonola , M. , Cascone , C. , Spaziani , M. , Bruschi , V. , Sanvito , D. , Siracusano , G. , Capone , A. , Honda , M. , Huici , F. , Siracusano , G. Flowblaze : Stateful packet processing in hardware . In 16th USENIX Symposium on Networked Systems Design and Implementation (NSDI 19) . Boston, MA, USENIX Association , 2019 , 531--548 Pontarelli, S., Bifulco, R., Bonola, M., Cascone, C., Spaziani, M., Bruschi, V., Sanvito, D., Siracusano, G., Capone, A., Honda, M., Huici, F., Siracusano, G. Flowblaze: Stateful packet processing in hardware. In 16th USENIX Symposium on Networked Systems Design and Implementation (NSDI 19). Boston, MA, USENIX Association, 2019, 531--548"},{"key":"e_1_2_1_29_1","volume-title":"2017 USENIX Annual Technical Conference (USENIX ATC 17)","author":"Sultana N.","year":"2017","unstructured":"Sultana , N. , Galea , S. , Greaves , D. , Wojcik , M. , Shipton , J. , Clegg , R. , Mai , L. , Bressana , P. , Soul\u00e9 , R. , Mortier , R. , Costa , P. , Pietzuch , P. , Crowcroft , J. , Moore , A.W. , Zilberman , N. Emu : Rapid prototyping of networking services . In 2017 USENIX Annual Technical Conference (USENIX ATC 17) , Santa Clara, CA, USENIX Association , 2017 , 459--471. Sultana, N., Galea, S., Greaves, D., Wojcik, M., Shipton, J., Clegg, R., Mai, L., Bressana, P., Soul\u00e9, R., Mortier, R., Costa, P., Pietzuch, P., Crowcroft, J., Moore, A.W., Zilberman, N. Emu: Rapid prototyping of networking services. In 2017 USENIX Annual Technical Conference (USENIX ATC 17), Santa Clara, CA, USENIX Association, 2017, 459--471."},{"key":"e_1_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/3050220.3050234"},{"key":"e_1_2_1_31_1","volume-title":"5G Wireless Solutions Powered by Xilinx","author":"Xilinx","year":"2020","unstructured":"Xilinx . 5G Wireless Solutions Powered by Xilinx . 2020 . https:\/\/www.xilinx.com\/applications\/megatrends\/5g.html Xilinx. 5G Wireless Solutions Powered by Xilinx. 2020. https:\/\/www.xilinx.com\/applications\/megatrends\/5g.html"},{"key":"e_1_2_1_32_1","volume-title":"IEEE Micro '14 34","author":"Zilberman N.","year":"2014","unstructured":"Zilberman , N. , Audzevich , Y. , Covington , G.A. , Moore , A.W. Net FPGA SUME : Toward 100 Gbps as Research Commodity . IEEE Micro '14 34 , 5 ( 2014 ), 32--41. Zilberman, N., Audzevich, Y., Covington, G.A., Moore, A.W. NetFPGA SUME: Toward 100 Gbps as Research Commodity. IEEE Micro '14 34, 5 (2014), 32--41."}],"container-title":["Communications of the ACM"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3543668","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3543668","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:00:48Z","timestamp":1750186848000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3543668"}},"subtitle":["Efficient software packet processing on FPGA NICs"],"short-title":[],"issued":{"date-parts":[[2022,7,21]]},"references-count":32,"journal-issue":{"issue":"8","published-print":{"date-parts":[[2022,8]]}},"alternative-id":["10.1145\/3543668"],"URL":"https:\/\/doi.org\/10.1145\/3543668","relation":{},"ISSN":["0001-0782","1557-7317"],"issn-type":[{"value":"0001-0782","type":"print"},{"value":"1557-7317","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,7,21]]},"assertion":[{"value":"2022-07-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}