{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:16:38Z","timestamp":1750220198716,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":28,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,8,29]],"date-time":"2022-08-29T00:00:00Z","timestamp":1661731200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100014440","name":"Ministerio de Ciencia, Innovaci\u00f3n y Universidades","doi-asserted-by":"publisher","award":["RTI2018-098156-B-C51","FPU18\/01948"],"award-info":[{"award-number":["RTI2018-098156-B-C51","FPU18\/01948"]}],"id":[{"id":"10.13039\/100014440","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,8,29]]},"DOI":"10.1145\/3545008.3545083","type":"proceedings-article","created":{"date-parts":[[2023,1,15]],"date-time":"2023-01-15T01:04:08Z","timestamp":1673744648000},"page":"1-11","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Cache-Poll: Containing Pollution in Non-Inclusive Caches Through Cache Partitioning"],"prefix":"10.1145","author":[{"given":"Lucia","family":"Pons","sequence":"first","affiliation":[{"name":"Universitat Polit\u00e8cnica de Val\u00e8ncia, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Julio","family":"Sahuquillo","sequence":"additional","affiliation":[{"name":"Universitat Polit\u00e8cnica de Val\u00e8ncia, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Salvador","family":"Petit","sequence":"additional","affiliation":[{"name":"Universitat Polit\u00e8cnica de Val\u00e8ncia, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Julio","family":"Pons","sequence":"additional","affiliation":[{"name":"Universitat Polit\u00e8cnica de Val\u00e8ncia, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,1,13]]},"reference":[{"volume-title":"AMD Zen 3 Ryzen Deep Dive Review: 5950X, 5900X, 5800X, and 5600X Tested. Retrieved","year":"2022","key":"e_1_3_2_1_1_1","unstructured":"AnandTech. 2020. AMD Zen 3 Ryzen Deep Dive Review: 5950X, 5900X, 5800X, and 5600X Tested. Retrieved February 1, 2022 from https:\/\/www.anandtech.com\/print\/16214\/amd-zen-3-ryzen-deep-dive-review-5950x-5900x-5800x-and-5700x-tested"},{"key":"e_1_3_2_1_2_1","volume-title":"Improving Real-Time Performance by Utilizing Cache Allocation Technology. White Paper: 31843-001US. Retrieved","author":"Intel Corporation","year":"2022","unstructured":"Intel Corporation. 2015. Improving Real-Time Performance by Utilizing Cache Allocation Technology. White Paper: 31843-001US. Retrieved February 1, 2022 from http:\/\/www.intel. com\/content\/dam\/www\/public\/us\/en\/documents\/white- papers\/ cache-allocation-technology-white-paper.pdf"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00019"},{"key":"e_1_3_2_1_4_1","volume-title":"Retrieved","author":"Gruber T.","year":"2022","unstructured":"T. Gruber and J. Hammer. 2019. L2 L3 MEM traffic on Intel Skylake SP CascadeLake SP. Retrieved April 20, 2022 from https:\/\/github.com\/RRZE-HPC\/likwid\/wiki\/L2-L3-MEM-traffic-on-Intel-Skylake-SP-CascadeLake-SP"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.52"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1990.134547"},{"key":"e_1_3_2_1_7_1","unstructured":"Akhilesh Kumar and Malay Trivedi. 2017. Intel Xeon Scalable Processor Architecture Deep Dive. Presentation at Intel Press Workshops."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10766-014-0334-5"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2749475"},{"key":"e_1_3_2_1_10_1","volume-title":"L3 cache. Retrieved","author":"Shared Arm","year":"2022","unstructured":"Arm DynamIQ Shared Unit-110 Technical\u00a0Reference Manual. 2021. L3 cache. Retrieved February 1, 2022 from https:\/\/developer.arm.com\/documentation\/102639\/0201\/L3-cache"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2018.00021"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1371\/journal.pone.0220135"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/3337821.3337891"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00019"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/3302424.3303963"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2020.2996031"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-96983-1_43"},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3112970"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2017.19"},{"key":"e_1_3_2_1_20_1","unstructured":"I.\u00a0Molnar T.\u00a0Gleixner. 2009. Performance counters for Linux. (2009)."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2013.6618815"},{"key":"e_1_3_2_1_22_1","volume-title":"Broadwell - Microarchitectures - Intel. Retrieved","author":"Engineering WikiChip Semiconductor","year":"2022","unstructured":"Semiconductor &\u00a0Engineering WikiChip, Chips &\u00a0Semi. 2001. Broadwell - Microarchitectures - Intel. Retrieved February 1, 2022 from https:\/\/en.wikichip.org\/wiki\/intel\/microarchitectures\/broadwell_(client)"},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155672"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1145\/3190508.3190511"},{"key":"e_1_3_2_1_25_1","doi-asserted-by":"publisher","DOI":"10.1145\/3337821.3337895"},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1145\/3190508.3190555"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2014.6844459"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/2872362.2872394"}],"event":{"name":"ICPP '22: 51st International Conference on Parallel Processing","acronym":"ICPP '22","location":"Bordeaux France"},"container-title":["Proceedings of the 51st International Conference on Parallel Processing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3545008.3545083","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3545008.3545083","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:02:44Z","timestamp":1750186964000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3545008.3545083"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,8,29]]},"references-count":28,"alternative-id":["10.1145\/3545008.3545083","10.1145\/3545008"],"URL":"https:\/\/doi.org\/10.1145\/3545008.3545083","relation":{},"subject":[],"published":{"date-parts":[[2022,8,29]]},"assertion":[{"value":"2023-01-13","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}