{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:17:13Z","timestamp":1750220233382,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,6,23]],"date-time":"2022-06-23T00:00:00Z","timestamp":1655942400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"GuangDong Basic and Applied Basic Research Foundation","award":["2021A1515110777"],"award-info":[{"award-number":["2021A1515110777"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,6,23]]},"DOI":"10.1145\/3546000.3546002","type":"proceedings-article","created":{"date-parts":[[2022,8,19]],"date-time":"2022-08-19T16:08:37Z","timestamp":1660925317000},"page":"12-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Reinforcement Learning Enabled Throughput Optimization for Interconnection Networks of Interposer-based system"],"prefix":"10.1145","author":[{"given":"Shuhao","family":"Ling","sequence":"first","affiliation":[{"name":"Guangdong University of Technology, China"}]},{"given":"Huaien","family":"Gao","sequence":"additional","affiliation":[{"name":"Guangdong University of Technology, China"}]},{"given":"Jiasong","family":"Chen","sequence":"additional","affiliation":[{"name":"Guangdong University of Technology, China"}]},{"given":"Dawei","family":"Liu","sequence":"additional","affiliation":[{"name":"Guangdong University of Technology, China"}]}],"member":"320","published-online":{"date-parts":[[2022,8,19]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Kirk Saban. 2012. Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity Bandwidth and Power Efficiency. White paper Virtex-7 FPGAs WP380(V1). Xilinx.  Kirk Saban. 2012. Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity Bandwidth and Power Efficiency. White paper Virtex-7 FPGAs WP380(V1). Xilinx."},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.61"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2016.7753258"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203849"},{"key":"e_1_3_2_1_5_1","volume-title":"Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems. In 2019 ACM\/IEEE International Workshop on System Level Interconnect Prediction (SLIP), 1\u20138. https:\/\/doi.org\/10","author":"Stow Dylan","year":"2019","unstructured":"Dylan Stow , Itir Akgun , and Yuan Xie . 2019 . Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems. In 2019 ACM\/IEEE International Workshop on System Level Interconnect Prediction (SLIP), 1\u20138. https:\/\/doi.org\/10 .1109\/SLIP.2019.8771333 10.1109\/SLIP.2019.8771333 Dylan Stow, Itir Akgun, and Yuan Xie. 2019. Investigation of Cost-Optimal Network-on-Chip for Passive and Active Interposer Systems. In 2019 ACM\/IEEE International Workshop on System Level Interconnect Prediction (SLIP), 1\u20138. https:\/\/doi.org\/10.1109\/SLIP.2019.8771333"},{"volume-title":"Proceedings of the 13th IEEE\/ACM International Symposium on Networks-on-Chip (NoCs), 1-8). https:\/\/doi.org\/10","author":"Guo H.","key":"e_1_3_2_1_6_1","unstructured":"Shabani, H. and Guo , X ., 2019, October. Cluscross: a new topology for silicon interposer-based Network-on-Chip . In Proceedings of the 13th IEEE\/ACM International Symposium on Networks-on-Chip (NoCs), 1-8). https:\/\/doi.org\/10 .1145\/3313231.3352363 10.1145\/3313231.3352363 Shabani, H. and Guo, X., 2019, October. Cluscross: a new topology for silicon interposer-based Network-on-Chip. In Proceedings of the 13th IEEE\/ACM International Symposium on Networks-on-Chip (NoCs), 1-8). https:\/\/doi.org\/10.1145\/3313231.3352363"},{"volume-title":"Proceedings of the 48th International Symposium on Microarchitecture, 546\u2013558","author":"Kannan Ajaykumar","key":"e_1_3_2_1_7_1","unstructured":"Ajaykumar Kannan , Natalie Enright Jerger , and Gabriel H. Loh . 2015. Enabling interposer-based disintegration of multi-core processors . In Proceedings of the 48th International Symposium on Microarchitecture, 546\u2013558 . https:\/\/doi.org\/10.1145\/2830772.2830808 10.1145\/2830772.2830808 Ajaykumar Kannan, Natalie Enright Jerger, and Gabriel H. Loh. 2015. Enabling interposer-based disintegration of multi-core processors. In Proceedings of the 48th International Symposium on Microarchitecture, 546\u2013558. https:\/\/doi.org\/10.1145\/2830772.2830808"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/SLIP52707.2021.00018"},{"key":"e_1_3_2_1_9_1","volume-title":"Reinforcement Learning Enabled Routing for High-Performance Networks-on-Chip. In 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1\u20135. https:\/\/doi.org\/10","author":"Reza Md Farhadur","year":"2021","unstructured":"Md Farhadur Reza and Tung Thanh Le . 2021 . Reinforcement Learning Enabled Routing for High-Performance Networks-on-Chip. In 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1\u20135. https:\/\/doi.org\/10 .1109\/ISCAS51556.2021.9401790 10.1109\/ISCAS51556.2021.9401790 Md Farhadur Reza and Tung Thanh Le. 2021. Reinforcement Learning Enabled Routing for High-Performance Networks-on-Chip. In 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1\u20135. https:\/\/doi.org\/10.1109\/ISCAS51556.2021.9401790"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3069210"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2022.104485"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317768"},{"key":"e_1_3_2_1_13_1","unstructured":"Greg Brockman Vicki Cheung Ludwig Pettersson Jonas Schneider John Schulman Jie Tang and Wojciech Zaremba. 2016. OpenAI Gym. Retrieved April 8 2022 from http:\/\/arxiv.org\/abs\/1606.01540  Greg Brockman Vicki Cheung Ludwig Pettersson Jonas Schneider John Schulman Jie Tang and Wojciech Zaremba. 2016. OpenAI Gym. Retrieved April 8 2022 from http:\/\/arxiv.org\/abs\/1606.01540"},{"key":"e_1_3_2_1_14_1","volume-title":"Barto","author":"Sutton Richard S.","year":"2018","unstructured":"Richard S. Sutton and Andrew G . Barto . 2018 . Reinforcement learning: an introduction. The MIT Press , Cambridge, Massachusetts. Richard S. Sutton and Andrew G. Barto. 2018. Reinforcement learning: an introduction. The MIT Press, Cambridge, Massachusetts."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919636"},{"key":"e_1_3_2_1_16_1","volume-title":"The gem5 Simulator: Version 20.0+. Retrieved","author":"Lowe-Power","year":"2022","unstructured":"Lowe-Power J, Ahmad AM , Akram A, 2020. The gem5 Simulator: Version 20.0+. Retrieved April 8, 2022 from http:\/\/arxiv.org\/abs\/2007.03152 Lowe-Power J, Ahmad AM, Akram A, 2020. The gem5 Simulator: Version 20.0+. Retrieved April 8, 2022 from http:\/\/arxiv.org\/abs\/2007.03152"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218539"},{"key":"e_1_3_2_1_18_1","volume-title":"EquiNox: Equivalent NoC Injection Routers for Silicon Interposer-Based Throughput Processors. In 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA), 435\u2013446","author":"Li Yunfan","year":"2020","unstructured":"Yunfan Li and Lizhong Chen . 2020 . EquiNox: Equivalent NoC Injection Routers for Silicon Interposer-Based Throughput Processors. In 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA), 435\u2013446 . https:\/\/doi.org\/10.1109\/HPCA47549.2020.00043 10.1109\/HPCA47549.2020.00043 Yunfan Li and Lizhong Chen. 2020. EquiNox: Equivalent NoC Injection Routers for Silicon Interposer-Based Throughput Processors. In 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA), 435\u2013446. https:\/\/doi.org\/10.1109\/HPCA47549.2020.00043"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1155\/2020\/8887589"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TSUSC.2020.2981340"},{"volume-title":"On-chip networks","author":"Enright Natalie","key":"e_1_3_2_1_21_1","unstructured":"Jerger, Natalie Enright , Tushar Krishna , and Li-Shiuan Peh . 2017. On-chip networks . Association for Computing Machinery and Morgan & Claypool . Jerger, Natalie Enright, Tushar Krishna, and Li-Shiuan Peh. 2017. On-chip networks. Association for Computing Machinery and Morgan & Claypool."},{"volume-title":"Principles and practices of interconnection networks","author":"James William","key":"e_1_3_2_1_22_1","unstructured":"Dally, William James , and Brian Patrick Towles . 2004. Principles and practices of interconnection networks . Elsevier . Dally, William James, and Brian Patrick Towles. 2004. Principles and practices of interconnection networks. Elsevier."}],"event":{"name":"HP3C'22: 2022 6th International Conference on High Performance Compilation, Computing and Communications","acronym":"HP3C'22","location":"Jilin China"},"container-title":["Proceedings of the 6th International Conference on High Performance Compilation, Computing and Communications"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3546000.3546002","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3546000.3546002","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:30:18Z","timestamp":1750188618000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3546000.3546002"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6,23]]},"references-count":22,"alternative-id":["10.1145\/3546000.3546002","10.1145\/3546000"],"URL":"https:\/\/doi.org\/10.1145\/3546000.3546002","relation":{},"subject":[],"published":{"date-parts":[[2022,6,23]]},"assertion":[{"value":"2022-08-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}