{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T16:25:11Z","timestamp":1774628711425,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":22,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,6,23]],"date-time":"2022-06-23T00:00:00Z","timestamp":1655942400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Key-Area Research and Development Program of Guangdong","award":["2019B010141002"],"award-info":[{"award-number":["2019B010141002"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,6,23]]},"DOI":"10.1145\/3546000.3546010","type":"proceedings-article","created":{"date-parts":[[2022,8,19]],"date-time":"2022-08-19T16:08:37Z","timestamp":1660925317000},"page":"66-71","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["An Efficient Parallel Architecture for Convolutional Neural Networks Accelerator on FPGAs"],"prefix":"10.1145","author":[{"given":"Huang","family":"Hongmin","sequence":"first","affiliation":[{"name":"School of Automation, Guangdong University of Technology, China and Company of Chipeye Microelectronics Foshan Ltd., China"}]},{"given":"Li","family":"Xueming","sequence":"additional","affiliation":[{"name":"School of Automation, Guangdong University of Technology, China"}]},{"given":"Qin","family":"Yadong","sequence":"additional","affiliation":[{"name":"School of Automation, Guangdong University of Technology, China"}]},{"given":"Hu","family":"Xianghong","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology, China"}]},{"given":"Xiong","family":"Xiaoming","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology, China and Company of Chipeye Microelectronics Foshan Ltd., China"}]}],"member":"320","published-online":{"date-parts":[[2022,8,19]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"e_1_3_2_1_2_1","volume-title":"Very deep convolutional networks for large-scale image recognition. arXiv preprint arXiv:1409.1556","author":"Simonyan Karen","year":"2014","unstructured":"[ 2 ] Karen Simonyan and Andrew Zisserman . Very deep convolutional networks for large-scale image recognition. arXiv preprint arXiv:1409.1556 , 2014 . [2] Karen Simonyan and Andrew Zisserman. Very deep convolutional networks for large-scale image recognition. arXiv preprint arXiv:1409.1556, 2014."},{"key":"e_1_3_2_1_3_1","first-page":"4","volume-title":"2018 Second International Conference on Advances in Electronics, Computers and Communications (ICAECC)","author":"Mujawar Shahmustafa","unstructured":"[ 3 ] Shahmustafa Mujawar , Divya Kiran , and Hariharan Ramasangu . An efficient cnn architecture for image classification on fpga accelerator . In 2018 Second International Conference on Advances in Electronics, Computers and Communications (ICAECC) , pages 1\u2013 4 . IEEE, 2018. [3] Shahmustafa Mujawar, Divya Kiran, and Hariharan Ramasangu. An efficient cnn architecture for image classification on fpga accelerator. In 2018 Second International Conference on Advances in Electronics, Computers and Communications (ICAECC), pages 1\u20134. IEEE, 2018."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.690"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3081818"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2021.04.061"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2014.223"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11760-021-01964-9"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2014.2325029"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"key":"e_1_3_2_1_11_1","first-page":"8","volume-title":"2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)","author":"Meloni Paolo","unstructured":"[ 11 ] Paolo Meloni , Gianfranco Deriu , Francesco Conti , Igor Loi , Luigi Raffo , and Luca Benini . A high-efficiency runtime reconfigurable ip for cnn acceleration on a mid-range all-programmable soc . In 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig) , pages 1\u2013 8 . IEEE, 2016. [11] Paolo Meloni, Gianfranco Deriu, Francesco Conti, Igor Loi, Luigi Raffo, and Luca Benini. A high-efficiency runtime reconfigurable ip for cnn acceleration on a mid-range all-programmable soc. In 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig), pages 1\u20138. IEEE, 2016."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2017.2690919"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2922372"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2995330"},{"key":"e_1_3_2_1_15_1","volume-title":"Devices & Systems","author":"Huang Hongmin","year":"2021","unstructured":"[ 15 ] Hongmin Huang , Xianghong Hu , Xueming Li , and Xiaoming Xiong . An efficient loop tiling framework for convolutional neural network inference accelerators. IET Circuits , Devices & Systems , 2021 . [15] Hongmin Huang, Xianghong Hu, Xueming Li, and Xiaoming Xiong. An efficient loop tiling framework for convolutional neural network inference accelerators. IET Circuits, Devices & Systems, 2021."},{"key":"e_1_3_2_1_16_1","first-page":"25","volume-title":"2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","author":"Lu Liqiang","unstructured":"[ 16 ] Liqiang Lu , Jiaming Xie , Ruirui Huang , Jiansong Zhang , Wei Lin , and Yun Liang . An efficient hardware accelerator for sparse convolutional neural networks on fpgas . In 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) , pages 17\u2013 25 . IEEE, 2019. [16] Liqiang Lu, Jiaming Xie, Ruirui Huang, Jiansong Zhang, Wei Lin, and Yun Liang. An efficient hardware accelerator for sparse convolutional neural networks on fpgas. In 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pages 17\u201325. IEEE, 2019."},{"key":"e_1_3_2_1_17_1","volume-title":"Angel-eye: A complete design flow for mapping cnn onto embedded fpga","author":"Guo Kaiyuan","year":"2017","unstructured":"[ 17 ] Kaiyuan Guo , Lingzhi Sui , Jiantao Qiu , Jincheng Yu , Junbin Wang , Song Yao , Song Han , Yu\u00a0Wang, and Huazhong Yang . Angel-eye: A complete design flow for mapping cnn onto embedded fpga . IEEE transactions on computer-aided design of integrated circuits and systems, 37(1):35\u201347, 2017 . [17] Kaiyuan Guo, Lingzhi Sui, Jiantao Qiu, Jincheng Yu, Junbin Wang, Song Yao, Song Han, Yu\u00a0Wang, and Huazhong Yang. Angel-eye: A complete design flow for mapping cnn onto embedded fpga. IEEE transactions on computer-aided design of integrated circuits and systems, 37(1):35\u201347, 2017."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3095283"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.14569\/IJACSA.2018.091062"},{"key":"e_1_3_2_1_20_1","first-page":"155","volume-title":"2020 IEEE 9th Global Conference on Consumer Electronics (GCCE)","author":"Wu Chung-Bin","unstructured":"[ 20 ] Chung-Bin Wu , Ching-Shun Wang , and Yu-Kuan Hsiao . Reconfigurable hardware architecture design and implementation for ai deep learning accelerator . In 2020 IEEE 9th Global Conference on Consumer Electronics (GCCE) , pages 154\u2013 155 . IEEE, 2020. [20] Chung-Bin Wu, Ching-Shun Wang, and Yu-Kuan Hsiao. Reconfigurable hardware architecture design and implementation for ai deep learning accelerator. In 2020 IEEE 9th Global Conference on Consumer Electronics (GCCE), pages 154\u2013155. IEEE, 2020."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2903150.2911715"},{"key":"e_1_3_2_1_22_1","first-page":"290","volume-title":"International conference on artificial neural networks","author":"Cong Jason","unstructured":"[ 22 ] Jason Cong and Bingjun Xiao . Minimizing computation in convolutional neural networks . In International conference on artificial neural networks , pages 281\u2013 290 . Springer, 2014. [22] Jason Cong and Bingjun Xiao. Minimizing computation in convolutional neural networks. In International conference on artificial neural networks, pages 281\u2013290. Springer, 2014."}],"event":{"name":"HP3C'22: 2022 6th International Conference on High Performance Compilation, Computing and Communications","location":"Jilin China","acronym":"HP3C'22"},"container-title":["Proceedings of the 6th International Conference on High Performance Compilation, Computing and Communications"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3546000.3546010","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3546000.3546010","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:30:18Z","timestamp":1750188618000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3546000.3546010"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6,23]]},"references-count":22,"alternative-id":["10.1145\/3546000.3546010","10.1145\/3546000"],"URL":"https:\/\/doi.org\/10.1145\/3546000.3546010","relation":{},"subject":[],"published":{"date-parts":[[2022,6,23]]},"assertion":[{"value":"2022-08-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}