{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T19:17:00Z","timestamp":1772738220267,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,6,23]],"date-time":"2022-06-23T00:00:00Z","timestamp":1655942400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"GuangDong Basic and Applied Basic Research Foundation","award":["2021A1515110777"],"award-info":[{"award-number":["2021A1515110777"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,6,23]]},"DOI":"10.1145\/3546000.3546019","type":"proceedings-article","created":{"date-parts":[[2022,8,19]],"date-time":"2022-08-19T16:08:37Z","timestamp":1660925317000},"page":"124-130","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["A High-Performance Bidirectional Compiler for Conversion Between SystemC and Verilog"],"prefix":"10.1145","author":[{"given":"Chenyu","family":"Huang","sequence":"first","affiliation":[{"name":"Guangdong University of Technology, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Huaien","family":"Gao","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Guangdong University of Technology, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yongfeng","family":"Zhong","sequence":"additional","affiliation":[{"name":"Guangdong University of Technology, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shuting","family":"Cai","sequence":"additional","affiliation":[{"name":"Guangdong University of Technology, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2022,8,19]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.3390\/s150510399"},{"key":"e_1_3_2_1_2_1","unstructured":"T Gr\u00f6tker Liao S Martin G System Design with SystemC[M].  T Gr\u00f6tker Liao S Martin G System Design with SystemC[M]."},{"key":"e_1_3_2_1_3_1","volume-title":"Automation & Test in Europe Conference & Exhibition (DATE). IEEE","author":"Tempel S","unstructured":"Tempel S , Herdt V , Drechsler R. An effective methodology for integrating concolic testing with SystemC-based virtual prototypes[C]\/\/2021 Design , Automation & Test in Europe Conference & Exhibition (DATE). IEEE , 2021: 218-221. Tempel S, Herdt V, Drechsler R. An effective methodology for integrating concolic testing with SystemC-based virtual prototypes[C]\/\/2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2021: 218-221."},{"key":"e_1_3_2_1_4_1","volume-title":"SystemC-based electronic system-level design space exploration environment for dedicated heterogeneous multi-processor systems[J]. Microprocessors and microsystems","author":"Pomante L","year":"2020","unstructured":"Pomante L , Muttillo V , Santic M , SystemC-based electronic system-level design space exploration environment for dedicated heterogeneous multi-processor systems[J]. Microprocessors and microsystems , 2020 , 72(Feb.):102898.1-102898.18. Pomante L , Muttillo V , Santic M , SystemC-based electronic system-level design space exploration environment for dedicated heterogeneous multi-processor systems[J]. Microprocessors and microsystems, 2020, 72(Feb.):102898.1-102898.18."},{"key":"e_1_3_2_1_5_1","volume-title":"systemc language usage as the alternative to the hdl and high- level modeling for noc simulation[J]","author":"Romanov A","year":"2019","unstructured":"Romanov A , Ivannikov A . systemc language usage as the alternative to the hdl and high- level modeling for noc simulation[J] . 2019 . Romanov A , Ivannikov A . systemc language usage as the alternative to the hdl and high- level modeling for noc simulation[J]. 2019."},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/Austrochip53290.2021.9576848"},{"key":"e_1_3_2_1_7_1","volume-title":"Development of SystemC-Verilog HDL Translator Using SLDS Mechanism[J]. IEICE technical report. Computer systems","author":"Sato M","year":"2012","unstructured":"Sato M , Mitsui H . Development of SystemC-Verilog HDL Translator Using SLDS Mechanism[J]. IEICE technical report. Computer systems , 2012 , 111. Sato M , Mitsui H . Development of SystemC-Verilog HDL Translator Using SLDS Mechanism[J]. IEICE technical report. Computer systems, 2012, 111."},{"key":"e_1_3_2_1_8_1","volume-title":"A novel neural source code representation based on abstract syntax tree[C]\/\/2019 IEEE\/ACM 41st International Conference on Software Engineering (ICSE)","author":"Zhang J","year":"2019","unstructured":"Zhang J , Wang X , Zhang H , A novel neural source code representation based on abstract syntax tree[C]\/\/2019 IEEE\/ACM 41st International Conference on Software Engineering (ICSE) . IEEE , 2019 : 783-794. Zhang J, Wang X, Zhang H, A novel neural source code representation based on abstract syntax tree[C]\/\/2019 IEEE\/ACM 41st International Conference on Software Engineering (ICSE). IEEE, 2019: 783-794."},{"key":"e_1_3_2_1_9_1","volume-title":"Through the looking glass: Automated design understanding of SystemC-based VPs at the ESL[J]","author":"Goli M","year":"2021","unstructured":"Goli M , Drechsler R. Through the looking glass: Automated design understanding of SystemC-based VPs at the ESL[J] . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 2021 . Goli M, Drechsler R. Through the looking glass: Automated design understanding of SystemC-based VPs at the ESL[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021."},{"key":"e_1_3_2_1_10_1","volume-title":"Dissertations & Theses - Gradworks","author":"Chen R .","year":"2011","unstructured":"Chen R . Synthesizable systemC to VHDL compiler design[J] . Dissertations & Theses - Gradworks , 2011 . Chen R . Synthesizable systemC to VHDL compiler design[J]. Dissertations & Theses - Gradworks, 2011."},{"key":"e_1_3_2_1_11_1","volume-title":"VDE","author":"Kaja E","year":"2021","unstructured":"Kaja E , Leon N O , Werner M , Extending Verilator to Enable Fault Simulation[C]\/\/ MBMV 2021 ; 24th Workshop . VDE , 2021: 1-6. Kaja E, Leon N O, Werner M, Extending Verilator to Enable Fault Simulation[C]\/\/MBMV 2021; 24th Workshop. VDE, 2021: 1-6."},{"key":"e_1_3_2_1_12_1","volume-title":"Avalibale online: https:\/\/www.edautils.com\/verilog2systemc.html (accessed on","year":"2022","unstructured":"verilog2systemc. Avalibale online: https:\/\/www.edautils.com\/verilog2systemc.html (accessed on 8 April 2022 ). verilog2systemc. Avalibale online: https:\/\/www.edautils.com\/verilog2systemc.html (accessed on 8 April 2022)."},{"key":"e_1_3_2_1_13_1","volume-title":"Development of SystemC-Verilog HDL Translator Using SLDS Mechanism[J]. IEICE technical report. Computer systems","author":"Sato M","year":"2012","unstructured":"Sato M , Mitsui H . Development of SystemC-Verilog HDL Translator Using SLDS Mechanism[J]. IEICE technical report. Computer systems , 2012 , 111. Sato M , Mitsui H . Development of SystemC-Verilog HDL Translator Using SLDS Mechanism[J]. IEICE technical report. Computer systems, 2012, 111."},{"key":"e_1_3_2_1_14_1","volume-title":"An open-source tool for SystemC to Verilog automatic translation[J]","author":"Castillo J , P","year":"2007","unstructured":"Castillo , Huerta J , P Mart\u00ednez , An open-source tool for SystemC to Verilog automatic translation[J] . 2007 . Castillo, Huerta J , P Mart\u00ednez, An open-source tool for SystemC to Verilog automatic translation[J]. 2007."},{"key":"e_1_3_2_1_15_1","volume-title":"Avalibale online:https:\/\/sourceforge.net\/projects\/sysc2ver (accessed on","author":"System","year":"2022","unstructured":"System C to Verilog RTL converter. Avalibale online:https:\/\/sourceforge.net\/projects\/sysc2ver (accessed on 8 April 2022 ). SystemC to Verilog RTL converter. Avalibale online:https:\/\/sourceforge.net\/projects\/sysc2ver (accessed on 8 April 2022)."},{"key":"e_1_3_2_1_16_1","volume-title":"Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL[C]\/\/ International Symposium on Applied Reconfigurable Computing","author":"Takamaeda-Yamazaki S .","year":"2015","unstructured":"Takamaeda-Yamazaki S . Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL[C]\/\/ International Symposium on Applied Reconfigurable Computing . Springer , Cham , 2015 . Takamaeda-Yamazaki S . Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL[C]\/\/ International Symposium on Applied Reconfigurable Computing. Springer, Cham, 2015."},{"key":"e_1_3_2_1_17_1","volume-title":"Verilog Program Examples using iverilog and GTKwave","author":"Prasad G .","year":"2021","unstructured":"Prasad G . Verilog Program Examples using iverilog and GTKwave . 2021 . Prasad G . Verilog Program Examples using iverilog and GTKwave. 2021."},{"key":"e_1_3_2_1_18_1","volume-title":"Op2-clang: A source-to-source translator using clang\/llvm libtooling[C]\/\/2018 IEEE\/ACM 5th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC)","author":"Balogh G D","year":"2018","unstructured":"Balogh G D , Mudalige G R , Reguly I Z , Op2-clang: A source-to-source translator using clang\/llvm libtooling[C]\/\/2018 IEEE\/ACM 5th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC) . IEEE , 2018 : 59-70. Balogh G D, Mudalige G R, Reguly I Z, Op2-clang: A source-to-source translator using clang\/llvm libtooling[C]\/\/2018 IEEE\/ACM 5th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC). IEEE, 2018: 59-70."}],"event":{"name":"HP3C'22: 2022 6th International Conference on High Performance Compilation, Computing and Communications","location":"Jilin China","acronym":"HP3C'22"},"container-title":["Proceedings of the 6th International Conference on High Performance Compilation, Computing and Communications"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3546000.3546019","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3546000.3546019","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:30:18Z","timestamp":1750188618000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3546000.3546019"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6,23]]},"references-count":18,"alternative-id":["10.1145\/3546000.3546019","10.1145\/3546000"],"URL":"https:\/\/doi.org\/10.1145\/3546000.3546019","relation":{},"subject":[],"published":{"date-parts":[[2022,6,23]]},"assertion":[{"value":"2022-08-19","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}