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Syst."],"published-print":{"date-parts":[[2023,3,31]]},"abstract":"<jats:p>The overlay architecture enables to raise the abstraction level of hardware design and enhances hardware-accelerated applications\u2019 portability. In FPGAs, there is a growing awareness of the overlay structure as typified by many-core architecture. It works in theory; however, it is difficult in practice, because it is beset with serious design issues. For example, the size of FPGAs is bigger than before. It is exacerbating the issue of the place-and-route. Besides, a single FPGA is actually the sum of small-to-middle FPGAs by advancing packaging technology like silicon interposers. Thus, the tightly coupled many-core designs will face this covert issue that the wires among the regions are extremely restricted. This article proposes efficient essential processing elements, micro-architecture design, and the interconnect architecture toward a scalable many-core overlay design. In particular, our work proposes a novel compact buffering technique to reduce memory resource utilization in tightly connected overlays while preserving computational efficiency. This technique reduces the utilization of BlockRAM to nearly 50% while achieving a best-case computational efficiency of 91.93% in a three-dimensional Jacobi benchmark. Besides, the proposed enhancements led to around 2\u00d7 and 3\u00d7 improvement in performance and power efficiency, respectively. Moreover, the improved scalability allowed increasing compute resources and delivering around 4\u00d7 better performance and power efficiency, as compared to the baseline Dynamically Re-programmable Architecture of Gather-scatter Overlay Nodes overlay.<\/jats:p>","DOI":"10.1145\/3547657","type":"journal-article","created":{"date-parts":[[2022,7,20]],"date-time":"2022-07-20T11:42:45Z","timestamp":1658317365000},"page":"1-33","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["A Scalable Many-core Overlay Architecture on an HBM2-enabled Multi-Die FPGA"],"prefix":"10.1145","volume":"16","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8504-4739","authenticated-orcid":false,"given":"Riadh Ben","family":"Abdelhamid","sequence":"first","affiliation":[{"name":"University of Tsukuba, Tsukuba, Ibaraki, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9744-8271","authenticated-orcid":false,"given":"Yoshiki","family":"Yamaguchi","sequence":"additional","affiliation":[{"name":"University of Tsukuba, Tsukuba, Ibaraki, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8730-2228","authenticated-orcid":false,"given":"Taisuke","family":"Boku","sequence":"additional","affiliation":[{"name":"Center for Computational Sciences, University of Tsukuba, Tsukuba, Ibaraki, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,1,18]]},"reference":[{"key":"e_1_3_1_2_2","first-page":"360","volume-title":"Proceedings of the 28th International Conference on Field Programmable Logic and Applications (FPL\u201918)","author":"Abbas Mustafa","year":"2018","unstructured":"Mustafa Abbas and Vaughn Betz. 2018. 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