{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T18:13:16Z","timestamp":1775067196931,"version":"3.50.1"},"reference-count":44,"publisher":"Association for Computing Machinery (ACM)","issue":"1-4","license":[{"start":{"date-parts":[[2022,11,24]],"date-time":"2022-11-24T00:00:00Z","timestamp":1669248000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Comput. Syst."],"published-print":{"date-parts":[[2022,11,30]]},"abstract":"<jats:p>\n            Issue time prediction processors use dataflow dependencies and predefined instruction latencies to predict issue times of repeated instructions. In this work, we make two key observations: (1) memory accesses often take additional time to arrive than the static, predefined access latency that is used to describe these systems. This is due to contention in the memory hierarchy and variability in DRAM access times, and (2) we find that these memory access delays often repeat across iterations of the same code. We propose a new processor microarchitecture that replaces a complex reservation-station-based scheduler with an efficient, scalable alternative. Our scheduling technique tracks real-time delays of loads to accurately predict instruction issue times and uses a reordering mechanism to prioritize instructions based on that prediction. To accomplish this in an energy-efficient manner we introduce (1) an\n            <jats:italic>instruction delay learning mechanism<\/jats:italic>\n            that monitors repeated load instructions and learns their latest delay, (2) an\n            <jats:italic>issue time predictor<\/jats:italic>\n            that uses learned delays and dataflow dependencies to predict instruction issue times, and (3)\n            <jats:italic>priority queues<\/jats:italic>\n            that reorder instructions based on their issue time prediction. Our processor achieves 86.2% of the performance of a traditional out-of-order processor, higher than previous efficient scheduler proposals, while consuming 30% less power.\n          <\/jats:p>","DOI":"10.1145\/3548681","type":"journal-article","created":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T11:32:46Z","timestamp":1657884766000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":5,"title":["Efficient Instruction Scheduling Using Real-time Load Delay Tracking"],"prefix":"10.1145","volume":"40","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7139-4444","authenticated-orcid":false,"given":"Andreas","family":"Diavastos","sequence":"first","affiliation":[{"name":"Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8742-134X","authenticated-orcid":false,"given":"Trevor E.","family":"Carlson","sequence":"additional","affiliation":[{"name":"National University of Singapore, Singapore"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2022,11,24]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00042"},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715034"},{"key":"e_1_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2015.12"},{"key":"e_1_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1145\/335231.335263"},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1145\/377792.377854"},{"key":"e_1_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750407"},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063454"},{"key":"e_1_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.1145\/2629677"},{"key":"e_1_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/279361.279378"},{"key":"e_1_3_1_11_2","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000079"},{"key":"e_1_3_1_12_2","doi-asserted-by":"publisher","DOI":"10.1145\/263580.263597"},{"key":"e_1_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1145\/859618.859647"},{"key":"e_1_3_1_14_2","doi-asserted-by":"publisher","DOI":"10.1145\/384285.379253"},{"key":"e_1_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783764"},{"key":"e_1_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798281"},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1999.744331"},{"key":"e_1_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2004.10014"},{"key":"e_1_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.43"},{"key":"e_1_3_1_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00039"},{"key":"e_1_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00009"},{"key":"e_1_3_1_22_2","doi-asserted-by":"publisher","DOI":"10.5555\/545215.545223"},{"key":"e_1_3_1_23_2","volume-title":"Systolic Priority Queues.","author":"Leiserson Charles E.","year":"1979","unstructured":"Charles E. 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