{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,24]],"date-time":"2026-02-24T17:58:37Z","timestamp":1771955917349,"version":"3.50.1"},"reference-count":33,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2022,12,24]],"date-time":"2022-12-24T00:00:00Z","timestamp":1671840000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Key-Area Research and Development Program of Guangdong Province","award":["2019B010140001"],"award-info":[{"award-number":["2019B010140001"]}]},{"name":"National 111 Center","award":["B12026"],"award-info":[{"award-number":["B12026"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2023,3,31]]},"abstract":"<jats:p>Field-programmable gate arrays (FPGAs) have grown to be an important platform for integrated circuit design and hardware emulation. However, with the dramatic increase in design scale, it has become a key challenge to partition very large scale integration into multi-FPGA systems. Fast estimation of FPGA on-chip resource usage for individual sub-circuit blocks early in the circuit design flow will provide an essential basis for reasonable circuit partition. It will also help FPGA designers to tune the circuits in hardware description language. In this article, we propose a framework for fast estimation of the on-chip resources consumed by register transfer level (RTL) designs with machine learning methods. We extensively collect RTL designs as a dataset, extract features from the result of a parser tool and analyze their roles, and train a targeted three-stage ensemble learning model. A 5,513\u00d7 speedup is achieved while having 27% relative absolute error. Although the effect is sufficient to support RTL circuit partition, we discuss how the estimation quality continues to be improved.<\/jats:p>","DOI":"10.1145\/3555047","type":"journal-article","created":{"date-parts":[[2022,9,29]],"date-time":"2022-09-29T11:46:18Z","timestamp":1664451978000},"page":"1-16","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Machine Learning Based Framework for Fast Resource Estimation of RTL Designs Targeting FPGAs"],"prefix":"10.1145","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1227-3909","authenticated-orcid":false,"given":"Benzheng","family":"Li","sequence":"first","affiliation":[{"name":"Xidian University School of Microelectronics, Xi\u2019an, Shaanxi, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5434-5619","authenticated-orcid":false,"given":"Xi","family":"Zhang","sequence":"additional","affiliation":[{"name":"Xidian University School of Microelectronics, Xi\u2019an, Shaanxi, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3427-5320","authenticated-orcid":false,"given":"Hailong","family":"You","sequence":"additional","affiliation":[{"name":"Xidian University School of Microelectronics, Xi\u2019an, Shaanxi, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9110-4248","authenticated-orcid":false,"given":"Zhongdong","family":"Qi","sequence":"additional","affiliation":[{"name":"Xidian University School of Microelectronics, Xi\u2019an, Shaanxi, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8587-0747","authenticated-orcid":false,"given":"Yuming","family":"Zhang","sequence":"additional","affiliation":[{"name":"Xidian University School of Microelectronics, Xi\u2019an, Shaanxi, China"}]}],"member":"320","published-online":{"date-parts":[[2022,12,24]]},"reference":[{"key":"e_1_3_1_2_2","unstructured":"OpenCores. 1999. OpenCores Home Page. Retrieved October 6 2022 from https:\/\/www.opencores.org."},{"key":"e_1_3_1_3_2","unstructured":"Verific. 2000. Verific Design Automation. Retrieved October 6 2022 from https:\/\/www.verific.com\/."},{"key":"e_1_3_1_4_2","unstructured":"GitHub. 2008. GitHub Home Page. Retrieved October 6 2022 from https:\/\/www.github.com."},{"key":"e_1_3_1_5_2","unstructured":"Keras. 2015. Keras Home Page. Retrieved October 6 2022 from https:\/\/keras.io."},{"key":"e_1_3_1_6_2","unstructured":"Xilinx. 2021. UG1399\u2014Vitis High-Level Synthesis User Guide. Available at https:\/\/www.xilinx.com."},{"key":"e_1_3_1_7_2","unstructured":"Xilinx. 2021. Vivado ML Standard Edition. Available at https:\/\/www.xilinx.com."},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4302-5990-9_4"},{"key":"e_1_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2003.1206381"},{"key":"e_1_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.862742"},{"key":"e_1_3_1_11_2","doi-asserted-by":"crossref","unstructured":"C. Brandolese W. Fornaciari and F. Salice. 2004. An area estimation methodology for FPGA based designs at systemc-level. In Proceedings of the 41st Design Automation Conference .","DOI":"10.1145\/996566.996606"},{"key":"e_1_3_1_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00016"},{"issue":"4","key":"e_1_3_1_13_2","first-page":"1","article-title":"XGBoost: Extreme gradient boosting","volume":"1","author":"Chen Tianqi","year":"2015","unstructured":"Tianqi Chen, Tong He, Michael Benesty, Vadim Khotilovich, Yuan Tang, Hyunsu Cho, Kailong Chen, et\u00a0al. 2015. XGBoost: Extreme gradient boosting. R Package Version 0.4-2 1, 4 (2015), 1\u20134.","journal-title":"R Package Version 0.4-2"},{"key":"e_1_3_1_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00029"},{"key":"e_1_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.1023\/A:1007607513941"},{"key":"e_1_3_1_16_2","article-title":"Support vector regression machines","volume":"9","author":"Drucker Harris","year":"1996","unstructured":"Harris Drucker, Christopher J. Burges, Linda Kaufman, Alex Smola, and Vladimir Vapnik. 1996. Support vector regression machines. In Advances in Neural Information Processing Systems 9 (1996).","journal-title":"Advances in Neural Information Processing Systems"},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44614-1_57"},{"key":"e_1_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.1214\/aos\/1016218223"},{"key":"e_1_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4541637"},{"key":"e_1_3_1_20_2","doi-asserted-by":"crossref","unstructured":"Jonathan Babb Russell Tessier and Anant Agarwal. 1993. Virtual wires: Overcoming pin limitations in FPGA-based logic emulators. In [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines . IEEE 142\u2013151.","DOI":"10.1109\/FPGA.1993.279469"},{"key":"e_1_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1016\/0893-6080(89)90020-8"},{"key":"e_1_3_1_22_2","doi-asserted-by":"crossref","unstructured":"Guyue Huang Jingbo Hu Yifan He Jialong Liu Mingyuan Ma Zhaoyang Shen Juejian Wu et\u00a0al. 2021. Machine learning for electronic design automation: A survey. ACM Transactions on Design Automation of Electronic Systems 26 5 (2021) Article 40 46 pages.","DOI":"10.1145\/3451179"},{"key":"e_1_3_1_23_2","doi-asserted-by":"publisher","DOI":"10.1145\/3177540.3177542"},{"key":"e_1_3_1_24_2","article-title":"High quality hypergraph partitioning for logic emulation","author":"Li Benzheng","year":"2021","unstructured":"Benzheng Li, Zhongdong Qi, Zhengguang Tang, Xiyi He, and Hailong You. 2021. High quality hypergraph partitioning for logic emulation. Integration 83 (2021), 67\u201376.","journal-title":"Integration"},{"key":"e_1_3_1_25_2","doi-asserted-by":"publisher","DOI":"10.1145\/3019612.3019683"},{"key":"e_1_3_1_26_2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00069"},{"key":"e_1_3_1_27_2","doi-asserted-by":"publisher","DOI":"10.1145\/2457443.2457446"},{"key":"e_1_3_1_28_2","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998400"},{"key":"e_1_3_1_29_2","doi-asserted-by":"publisher","DOI":"10.5555\/1953048.2078195"},{"key":"e_1_3_1_30_2","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2014.6983050"},{"key":"e_1_3_1_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2008.4629908"},{"key":"e_1_3_1_32_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI51109.2021.00019"},{"key":"e_1_3_1_33_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-30117-2_44"},{"key":"e_1_3_1_34_2","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00020"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3555047","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3555047","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T16:46:49Z","timestamp":1750178809000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3555047"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,12,24]]},"references-count":33,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2023,3,31]]}},"alternative-id":["10.1145\/3555047"],"URL":"https:\/\/doi.org\/10.1145\/3555047","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,12,24]]},"assertion":[{"value":"2022-02-14","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-07-24","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-12-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}