{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,18]],"date-time":"2025-12-18T14:22:09Z","timestamp":1766067729782,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":34,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,3,27]],"date-time":"2023-03-27T00:00:00Z","timestamp":1679875200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100011033","name":"Agencia Estatal de Investigaci\u00f3n","doi-asserted-by":"publisher","award":["PID2019-107255GB-C21"],"award-info":[{"award-number":["PID2019-107255GB-C21"]}],"id":[{"id":"10.13039\/501100011033","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100000781","name":"European Research Council","doi-asserted-by":"publisher","award":["772773"],"award-info":[{"award-number":["772773"]}],"id":[{"id":"10.13039\/501100000781","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,3,27]]},"DOI":"10.1145\/3555776.3577631","type":"proceedings-article","created":{"date-parts":[[2023,6,7]],"date-time":"2023-06-07T17:16:29Z","timestamp":1686158189000},"page":"461-470","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Tracking Coherence-Related Contention Delays in Real-Time Multicore Systems"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1960-6358","authenticated-orcid":false,"given":"Roger","family":"Pujol","sequence":"first","affiliation":[{"name":"Computer Architecture - Operating Systems (CAOS), Barcelona Supercomputing Center, Barcelona, Spain"},{"name":"Computer Architecture, Universitat Polit\u00e8cnica de Catalunya, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5926-5861","authenticated-orcid":false,"given":"Mohamed","family":"Hassan","sequence":"additional","affiliation":[{"name":"Department of Electrical & Computer Engineering, McMaster University, Hamilton, Ontario, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6061-7470","authenticated-orcid":false,"given":"Hamid","family":"Tabani","sequence":"additional","affiliation":[{"name":"Computer Architecture - Operating Systems (CAOS), Barcelona Supercomputing Center, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7951-4028","authenticated-orcid":false,"given":"Jaume","family":"Abella","sequence":"additional","affiliation":[{"name":"Computer Architecture - Operating Systems (CAOS), Barcelona Supercomputing Center (BSC-CNS), Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3344-376X","authenticated-orcid":false,"given":"Francisco Javier","family":"Cazorla","sequence":"additional","affiliation":[{"name":"Computer Architecture - Operating Systems (CAOS), Barcelona Supercomputing Center, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,6,7]]},"reference":[{"volume-title":"Subset Services","author":"ARRNC Inc. 2012.","key":"e_1_3_2_1_1_1","unstructured":"ARRNC Inc. 2012. ARINC Specification 653: Avionics Application Software Standard Standard Interface, Part 1 and 4 , Subset Services . ARINC Inc . ARRNC Inc. 2012. ARINC Specification 653: Avionics Application Software Standard Standard Interface, Part 1 and 4, Subset Services. ARINC Inc."},{"key":"e_1_3_2_1_2_1","unstructured":"Arm Ltd. 2018. Arm CoreLink CMN-600 Coherent Mesh Network - Technical Reference Manual.  Arm Ltd. 2018. Arm CoreLink CMN-600 Coherent Mesh Network - Technical Reference Manual."},{"key":"e_1_3_2_1_3_1","unstructured":"Ayoosh Bansal et al. 2019. Cache Where you Want! Reconciling Predictability and Coherent Caching. CoRR abs\/1909.05349 (2019). http:\/\/arxiv.org\/abs\/1909.05349  Ayoosh Bansal et al. 2019. Cache Where you Want! Reconciling Predictability and Coherent Caching. CoRR abs\/1909.05349 (2019). http:\/\/arxiv.org\/abs\/1909.05349"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_5_1","volume-title":"21st Euromicro Conference on Real-Time Systems, ECRTS 2009","author":"John","year":"2009","unstructured":"John M. Calandrino and James H. Anderson. 2009. On the Design and Implementation of a Cache-Aware Multicore Real-Time Scheduler . In 21st Euromicro Conference on Real-Time Systems, ECRTS 2009 , Dublin, Ireland , July 1-3, 2009 . IEEE Computer Society, 194--204. 10.1109\/ECRTS.2009.13 John M. Calandrino and James H. Anderson. 2009. On the Design and Implementation of a Cache-Aware Multicore Real-Time Scheduler. In 21st Euromicro Conference on Real-Time Systems, ECRTS 2009, Dublin, Ireland, July 1-3, 2009. IEEE Computer Society, 194--204. 10.1109\/ECRTS.2009.13"},{"key":"e_1_3_2_1_6_1","volume-title":"Multicore Systems. In 2016 IEEE Real-Time Systems Symposium, RTSS 2016","author":"Micaiah","year":"2016","unstructured":"Micaiah Chisholm et al. 2016. Reconciling the Tension Between Hardware Isolation and Data Sharing in Mixed-Criticality , Multicore Systems. In 2016 IEEE Real-Time Systems Symposium, RTSS 2016 , Porto, Portugal, November 29 - December 2, 2016 . IEEE Computer Society, 57--68. 10.1109\/RTSS.2016.015 Micaiah Chisholm et al. 2016. Reconciling the Tension Between Hardware Isolation and Data Sharing in Mixed-Criticality, Multicore Systems. In 2016 IEEE Real-Time Systems Symposium, RTSS 2016, Porto, Portugal, November 29 - December 2, 2016. IEEE Computer Society, 57--68. 10.1109\/RTSS.2016.015"},{"volume-title":"Ada-Europe International Conference on Reliable Software Technologies. 102--118","author":"Enrique","key":"e_1_3_2_1_7_1","unstructured":"Enrique D\u00edaz et al. 2017. MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding . In Ada-Europe International Conference on Reliable Software Technologies. 102--118 . Enrique D\u00edaz et al. 2017. MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding. In Ada-Europe International Conference on Reliable Software Technologies. 102--118."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2616307"},{"key":"e_1_3_2_1_9_1","unstructured":"freescale semicondutor. 2014. e6500 Core Reference Manual. https:\/\/www.nxp.com\/docs\/en\/reference-manual\/E6500RM.pdf. E6500RM. Rev 0. 06\/2014.  freescale semicondutor. 2014. e6500 Core Reference Manual. https:\/\/www.nxp.com\/docs\/en\/reference-manual\/E6500RM.pdf. E6500RM. Rev 0. 06\/2014."},{"key":"e_1_3_2_1_10_1","first-page":"2016","article-title":"QorIQ T2080 Reference Manual. Also supports T2081. Doc. No.: T2080RM","volume":"3","author":"Freescale","year":"2016","unstructured":"Freescale semicondutor. 2016 . QorIQ T2080 Reference Manual. Also supports T2081. Doc. No.: T2080RM . Rev. 3 , 11\/ 2016 . Freescale semicondutor. 2016. QorIQ T2080 Reference Manual. Also supports T2081. Doc. No.: T2080RM. Rev. 3, 11\/2016.","journal-title":"Rev."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/2883591.2883594"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2016.0114"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.4230\/LIPIcs.ECRTS.2020.16"},{"key":"e_1_3_2_1_14_1","volume-title":"Predictable Cache Coherence for Multi-core Real-Time Systems. In 2017 IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2017","author":"Mohamed","year":"2017","unstructured":"Mohamed Hassan et al. 2017 . Predictable Cache Coherence for Multi-core Real-Time Systems. In 2017 IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2017 , Pittsburg, PA, USA , April 18-21, 2017 , Gabriel Parmer (Ed.). IEEE Computer Society, 235--246. 10.1109\/RTAS.2017.13 Mohamed Hassan et al. 2017. Predictable Cache Coherence for Multi-core Real-Time Systems. In 2017 IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2017, Pittsburg, PA, USA, April 18-21, 2017, Gabriel Parmer (Ed.). IEEE Computer Society, 235--246. 10.1109\/RTAS.2017.13"},{"key":"e_1_3_2_1_15_1","volume-title":"Patterson","author":"Hennessy John L.","year":"2012","unstructured":"John L. Hennessy and David A . Patterson . 2012 . Computer Architecture - A Quantitative Approach, 5 th Edition. Morgan Kaufmann . John L. Hennessy and David A. Patterson. 2012. Computer Architecture - A Quantitative Approach, 5th Edition. Morgan Kaufmann.","edition":"5"},{"key":"e_1_3_2_1_16_1","volume-title":"2020 IEEE Real-Time Systems Symposium (RTSS). IEEE, 218--230","author":"Hessien Salah","year":"2020","unstructured":"Salah Hessien and Mohamed Hassan . 2020 . The Best of All Worlds: Improving Predictability at the Performance of Conventional Coherence with No Protocol Modifications . In 2020 IEEE Real-Time Systems Symposium (RTSS). IEEE, 218--230 . Salah Hessien and Mohamed Hassan. 2020. The Best of All Worlds: Improving Predictability at the Performance of Conventional Coherence with No Protocol Modifications. In 2020 IEEE Real-Time Systems Symposium (RTSS). IEEE, 218--230."},{"key":"e_1_3_2_1_17_1","volume-title":"CARP: A Data Communication Mechanism for Multi-core Mixed-Criticality Systems. In IEEE Real-Time Systems Symposium, RTSS 2019","author":"Anirudh","year":"2019","unstructured":"Anirudh M. Kaushik et al. 2019 . CARP: A Data Communication Mechanism for Multi-core Mixed-Criticality Systems. In IEEE Real-Time Systems Symposium, RTSS 2019 , Hong Kong, SAR, China , December 3-6, 2019 . IEEE, 419--432. 10.1109\/RTSS46320.2019.00044 Anirudh M. Kaushik et al. 2019. CARP: A Data Communication Mechanism for Multi-core Mixed-Criticality Systems. In IEEE Real-Time Systems Symposium, RTSS 2019, Hong Kong, SAR, China, December 3-6, 2019. IEEE, 419--432. 10.1109\/RTSS46320.2019.00044"},{"key":"e_1_3_2_1_18_1","volume-title":"Kaushik et al","author":"Anirudh","year":"2020","unstructured":"Anirudh M. Kaushik et al . 2020 . Designing predictable cache coherence protocols for multi-core real-time systems. IEEE Trans. Comput . (2020). Anirudh M. Kaushik et al. 2020. Designing predictable cache coherence protocols for multi-core real-time systems. IEEE Trans. Comput. (2020)."},{"volume-title":"2021 IEEE 27th Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 105--117","author":"Anirudh","key":"e_1_3_2_1_19_1","unstructured":"Anirudh M. Kaushik and Hiren D. Patel. 2021. A Systematic Approach to Achieving Tight Worst-Case Latency and High-Performance Under Predictable Cache Coherence . In 2021 IEEE 27th Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 105--117 . Anirudh M. Kaushik and Hiren D. Patel. 2021. A Systematic Approach to Achieving Tight Worst-Case Latency and High-Performance Under Predictable Cache Coherence. In 2021 IEEE 27th Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 105--117."},{"key":"e_1_3_2_1_20_1","unstructured":"Hyoseung Kim et al. 2014. Bounding Memory Interference Delay in COTS-based Multi-Core Systems. In RTAS.  Hyoseung Kim et al. 2014. Bounding Memory Interference Delay in COTS-based Multi-Core Systems. In RTAS."},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2801239"},{"key":"e_1_3_2_1_22_1","volume-title":"Critical Systems: The Case of NXP's T2080 Cache Coherence. In DATE.","author":"Roger Pujol","year":"2021","unstructured":"Roger Pujol et al. 2021 . Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP's T2080 Cache Coherence. In DATE. Roger Pujol et al. 2021. Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP's T2080 Cache Coherence. In DATE."},{"key":"e_1_3_2_1_23_1","unstructured":"David Radack et al. 2018. Civil Certification of Multi-core Processing Systems in Commercial Avionics.  David Radack et al. 2018. Civil Certification of Multi-core Processing Systems in Commercial Avionics."},{"key":"e_1_3_2_1_24_1","volume-title":"2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). IEEE, 101--111","author":"Christos","year":"2016","unstructured":"Christos Sakalis et al. 2016. Splash-3: A properly synchronized benchmark suite for contemporary research . In 2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). IEEE, 101--111 . 10.1109\/ISPASS. 2016 .7482078 Christos Sakalis et al. 2016. Splash-3: A properly synchronized benchmark suite for contemporary research. In 2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). IEEE, 101--111. 10.1109\/ISPASS.2016.7482078"},{"key":"e_1_3_2_1_25_1","volume-title":"Fixed-Priority Memory-Centric Scheduler for COTS-Based Multiprocessors. In 32nd Euromicro Conference on Real-Time Systems, ECRTS 2020, July 7-10, 2020, Virtual Conference (LIPIcs","volume":"24","author":"Gero","year":"2020","unstructured":"Gero Schw\u00e4ricke et al. 2020 . Fixed-Priority Memory-Centric Scheduler for COTS-Based Multiprocessors. In 32nd Euromicro Conference on Real-Time Systems, ECRTS 2020, July 7-10, 2020, Virtual Conference (LIPIcs , Vol. 165). 1:1--1: 24 . 10.4230\/LIPIcs.ECRTS. 2020 .1 Gero Schw\u00e4ricke et al. 2020. Fixed-Priority Memory-Centric Scheduler for COTS-Based Multiprocessors. In 32nd Euromicro Conference on Real-Time Systems, ECRTS 2020, July 7-10, 2020, Virtual Conference (LIPIcs, Vol. 165). 1:1--1:24. 10.4230\/LIPIcs.ECRTS.2020.1"},{"key":"e_1_3_2_1_26_1","unstructured":"Nathana\u00ebl Sensfelder et al. 2020. On How to Identify Cache Coherence: Case of the NXP QorIQ T4240. In ECRTS.  Nathana\u00ebl Sensfelder et al. 2020. On How to Identify Cache Coherence: Case of the NXP QorIQ T4240. In ECRTS."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.2200\/S00346ED1V01Y201104CAC016"},{"key":"e_1_3_2_1_28_1","unstructured":"Nivedita Sritharan et al. 2017. HourGlass: Predictable Time-based Cache Coherence Protocol for Dual-Critical Multi-Core Systems. CoRR abs\/1706.07568 (2017). http:\/\/arxiv.org\/abs\/1706.07568  Nivedita Sritharan et al. 2017. HourGlass: Predictable Time-based Cache Coherence Protocol for Dual-Critical Multi-Core Systems. CoRR abs\/1706.07568 (2017). http:\/\/arxiv.org\/abs\/1706.07568"},{"key":"e_1_3_2_1_29_1","volume-title":"Simultaneous and Coherent Data Sharing in Mixed Criticality Systems. In IEEE Real-Time Systems Symposium, RTSS 2019","author":"Nivedita","year":"2019","unstructured":"Nivedita Sritharan et al. 2019. Enabling Predictable , Simultaneous and Coherent Data Sharing in Mixed Criticality Systems. In IEEE Real-Time Systems Symposium, RTSS 2019 , Hong Kong, SAR, China , December 3-6, 2019 . IEEE, 433--445. 10.1109\/RTSS46320.2019.00045 Nivedita Sritharan et al. 2019. Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems. In IEEE Real-Time Systems Symposium, RTSS 2019, Hong Kong, SAR, China, December 3-6, 2019. IEEE, 433--445. 10.1109\/RTSS46320.2019.00045"},{"key":"e_1_3_2_1_30_1","volume-title":"Proceedings of the 45th Design Automation Conference, DAC 2008","author":"Suhendra Vivy","year":"2008","unstructured":"Vivy Suhendra and Tulika Mitra . 2008 . Exploring locking & partitioning for predictable shared caches on multi-cores . In Proceedings of the 45th Design Automation Conference, DAC 2008 , Anaheim, CA, USA , June 8-13, 2008, Limor Fix (Ed.). ACM, 300--303. 10.1145\/1391469.1391545 Vivy Suhendra and Tulika Mitra. 2008. Exploring locking & partitioning for predictable shared caches on multi-cores. In Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, Limor Fix (Ed.). ACM, 300--303. 10.1145\/1391469.1391545"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/2910589"},{"key":"e_1_3_2_1_32_1","volume-title":"Outstanding Paper Award: Making Shared Caches More Predictable on Multicore Platforms. In 25th Euromicro Conference on Real-Time Systems, ECRTS 2013","author":"Bryan","year":"2013","unstructured":"Bryan C. Ward et al. 2013 . Outstanding Paper Award: Making Shared Caches More Predictable on Multicore Platforms. In 25th Euromicro Conference on Real-Time Systems, ECRTS 2013 , Paris, France , July 9-12, 2013 . IEEE Computer Society, 157--167. 10.1109\/ECRTS.2013.26 Bryan C. Ward et al. 2013. Outstanding Paper Award: Making Shared Caches More Predictable on Multicore Platforms. In 25th Euromicro Conference on Real-Time Systems, ECRTS 2013, Paris, France, July 9-12, 2013. IEEE Computer Society, 157--167. 10.1109\/ECRTS.2013.26"},{"key":"e_1_3_2_1_33_1","unstructured":"XILINX. 2018. Rockwell Collins Uses Zynq UltraScale+ RFSoC Devices in Revolutionizing How Arrays are Produced and Fielded: Powered by Xilinx. https:\/\/www.xilinx.com\/video\/corporate\/rockwell-collins-rfsoc-revolutionizing-how-arrays-are-produced.html  XILINX. 2018. Rockwell Collins Uses Zynq UltraScale+ RFSoC Devices in Revolutionizing How Arrays are Produced and Fielded: Powered by Xilinx. https:\/\/www.xilinx.com\/video\/corporate\/rockwell-collins-rfsoc-revolutionizing-how-arrays-are-produced.html"},{"key":"e_1_3_2_1_34_1","unstructured":"XILINX. 2019. Zynq UltraScale+ Device. Technical Reference Manual. UG1085 (v2.1).  XILINX. 2019. Zynq UltraScale+ Device. Technical Reference Manual. UG1085 (v2.1)."}],"event":{"name":"SAC '23: 38th ACM\/SIGAPP Symposium on Applied Computing","sponsor":["SIGAPP ACM Special Interest Group on Applied Computing"],"location":"Tallinn Estonia","acronym":"SAC '23"},"container-title":["Proceedings of the 38th ACM\/SIGAPP Symposium on Applied Computing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3555776.3577631","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3555776.3577631","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T18:08:23Z","timestamp":1750183703000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3555776.3577631"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,3,27]]},"references-count":34,"alternative-id":["10.1145\/3555776.3577631","10.1145\/3555776"],"URL":"https:\/\/doi.org\/10.1145\/3555776.3577631","relation":{},"subject":[],"published":{"date-parts":[[2023,3,27]]},"assertion":[{"value":"2023-06-07","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}