{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T17:10:44Z","timestamp":1773249044951,"version":"3.50.1"},"reference-count":47,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2022,12,24]],"date-time":"2022-12-24T00:00:00Z","timestamp":1671840000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"crossref","award":["62090025, 62141407, 61822402, 61974032, and 61929102"],"award-info":[{"award-number":["62090025, 62141407, 61822402, 61974032, and 61929102"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100012166","name":"National Key R&D Program of China","doi-asserted-by":"crossref","award":["2020YFA0711900, 2020YFA0711901"],"award-info":[{"award-number":["2020YFA0711900, 2020YFA0711901"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Young Scientist project of MOE"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2023,3,31]]},"abstract":"<jats:p>Chip floorplanning has long been a critical task with high computation complexity in the physical implementation of VLSI chips. Its key objective is to determine the initial locations of large chip modules with minimized wirelength while adhering to the density constraint, which in essence is a process of constructing an optimized mapping from circuit connectivity to physical locations. Proven to be an NP-hard problem, chip floorplanning is difficult to be solved efficiently using algorithmic approaches. This article presents GraphPlanner, a variational graph-convolutional-network-based deep learning technique for chip floorplanning. GraphPlanner is able to learn an optimized and generalized mapping between circuit connectivity and physical wirelength and produce a chip floorplan using efficient model inference. GraphPlanner is further equipped with an efficient clustering method, a unification of hyperedge coarsening with graph spectral clustering, to partition a large-scale netlist into high-quality clusters with minimized inter-cluster weighted connectivity. GraphPlanner has been integrated with two state-of-the-art mixed-size placers. Experimental studies using both academic benchmarks and industrial designs demonstrate that compared to state-of-the-art mixed-size placers alone, GraphPlanner improves placement runtime by 25% with 4% wirelength reduction on average.<\/jats:p>","DOI":"10.1145\/3555804","type":"journal-article","created":{"date-parts":[[2022,8,17]],"date-time":"2022-08-17T12:07:12Z","timestamp":1660738032000},"page":"1-24","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":12,"title":["GraphPlanner: Floorplanning with Graph Neural Network"],"prefix":"10.1145","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8078-6717","authenticated-orcid":false,"given":"Yiting","family":"Liu","sequence":"first","affiliation":[{"name":"School of Computer Science, Fudan University, Songhu Road, Yangpu District, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3702-7373","authenticated-orcid":false,"given":"Ziyi","family":"Ju","sequence":"additional","affiliation":[{"name":"School of Computer Science, Fudan University, Songhu Road, Yangpu District, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2126-8586","authenticated-orcid":false,"given":"Zhengming","family":"Li","sequence":"additional","affiliation":[{"name":"School of Computer Science, Fudan University, Songhu Road, Yangpu District, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8897-5931","authenticated-orcid":false,"given":"Mingzhi","family":"Dong","sequence":"additional","affiliation":[{"name":"School of Computer Science &amp; Zhangjiang Fudan International Innovation Center, Fudan University, Pudong New Area, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4824-7179","authenticated-orcid":false,"given":"Hai","family":"Zhou","sequence":"additional","affiliation":[{"name":"ICBench Inc., Dieqiao Road, Pudong New Area, Shanghai"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6159-6085","authenticated-orcid":false,"given":"Jia","family":"Wang","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Illinois Institute of Technology Chicago, Chicago, IL, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2164-8175","authenticated-orcid":false,"given":"Fan","family":"Yang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University Shanghai, Zhangheng Road, Pudong New Area, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8097-4053","authenticated-orcid":false,"given":"Xuan","family":"Zeng","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University Shanghai, Zhangheng Road, Pudong New Area, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3944-7531","authenticated-orcid":false,"given":"Li","family":"Shang","sequence":"additional","affiliation":[{"name":"School of Computer Science, Fudan University Shanghai, Songhu Road, Yangpu District, Shanghai, China"}]}],"member":"320","published-online":{"date-parts":[[2022,12,24]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415690"},{"key":"e_1_3_1_3_2","volume-title":"NeurIPS 2020 Workshop on Machine Learning for Systems","author":"Agnesina Anthony","year":"2020","unstructured":"Anthony Agnesina, Sai Pentapati, and Sung Kyu Lim. 2020. A general framework for VLSI tool parameter optimization with deep reinforcement learning. In NeurIPS 2020 Workshop on Machine Learning for Systems."},{"key":"e_1_3_1_4_2","doi-asserted-by":"crossref","unstructured":"A. B. Kahng J. Lienig I. L. Markov and J. Hu. 2011. VLSI Physical Design: From Graph Partitioning to Timing Closure . Springer 1\u2013312.","DOI":"10.1007\/978-90-481-9591-6_1"},{"key":"e_1_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.5555\/800262.809144"},{"key":"e_1_3_1_6_2","doi-asserted-by":"crossref","unstructured":"A. E. Caldwell A. B. Kahng and I. L. Markov. 2000. Toward CAD-IP Reuse: The MARCO GSRC bookshelf of fundamental CAD algorithms. IEEE Design and Test of Computers 19 3 (2002) 70\u201379.","DOI":"10.1109\/MDT.2002.1003801"},{"key":"e_1_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.1145\/1123008.1123055"},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2000.855354"},{"key":"e_1_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISKE.2008.4731079"},{"key":"e_1_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923063"},{"key":"e_1_3_1_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2859220"},{"key":"e_1_3_1_12_2","unstructured":"Ruoyu Cheng and Junchi Yan. 2021. On joint learning for solving placement and routing in chip design. In 35th Conference on Neural Information Processing Systems (NeurIPS\u201921) 1\u201312."},{"key":"e_1_3_1_13_2","volume-title":"Spectral Graph Theory","author":"Chung Fan R. K.","year":"1997","unstructured":"Fan R. K. Chung and Fan Chung Graham. 1997. Spectral Graph Theory. Number 92. American Mathematical Society."},{"key":"e_1_3_1_14_2","doi-asserted-by":"crossref","unstructured":"Alfred E. Dunlop and Brian W. Kernighan. 1985. A procedure for placement of standard-cell VLSI circuits. IEEE Transactions on Computer-Aided Design 4 1 (1985) 92\u201398.","DOI":"10.1109\/TCAD.1985.1270101"},{"key":"e_1_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.5555\/800263.809204"},{"key":"e_1_3_1_16_2","volume-title":"Baltimore: Johns Hopkins University Press","author":"Golub G.","year":"1983","unstructured":"G. Golub and C. V. Loan. 1983. Matrix Computations. Baltimore: Johns Hopkins University Press."},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.5555\/3086952"},{"key":"e_1_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415691"},{"key":"e_1_3_1_19_2","first-page":"1","volume-title":"International Workshop on System Level Interconnect Prediction","author":"Han Sung Kyu","year":"2011","unstructured":"Sung Kyu Han, Kwangok Jeong, Andrew B. Kahng, and Jingwei Lu. 2011. Stability and scalability in global routing. In International Workshop on System Level Interconnect Prediction. IEEE, 1\u20136."},{"key":"e_1_3_1_20_2","doi-asserted-by":"crossref","unstructured":"Leena Jain and Amarbir Singh. 2013. Non slicing floorplan representations in VLSI floorplanning: A summary. International Journal of Computer Applications 71 15 (2013) 12\u201319.","DOI":"10.5120\/12433-8962"},{"key":"e_1_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1145\/332357.332401"},{"key":"e_1_3_1_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/92.748202"},{"key":"e_1_3_1_23_2","doi-asserted-by":"publisher","DOI":"10.1007\/s10710-006-9020-8"},{"key":"e_1_3_1_24_2","unstructured":"D. P. Kingma and Welling. 2014. Autoencoding variational bayes. In Proceedings of the International Conference on Learning Representations (ICLR\u201914) 1\u201314."},{"key":"e_1_3_1_25_2","article-title":"Semi-supervised classification with graph convolutional networks","author":"Kipf Thomas N.","year":"2016","unstructured":"Thomas N. Kipf and Max Welling. 2016. Semi-supervised classification with graph convolutional networks. arXiv preprint arXiv:1609.02907 (2016).","journal-title":"arXiv preprint arXiv:1609.02907"},{"key":"e_1_3_1_26_2","article-title":"Variational graph auto-encoders","author":"Kipf Thomas N.","year":"2016","unstructured":"Thomas N. Kipf and Max Welling. 2016. Variational graph auto-encoders. arXiv preprint arXiv:1611.07308 (2016).","journal-title":"arXiv preprint arXiv:1611.07308"},{"key":"e_1_3_1_27_2","doi-asserted-by":"publisher","DOI":"10.1126\/science.220.4598.671"},{"key":"e_1_3_1_28_2","doi-asserted-by":"crossref","first-page":"77","DOI":"10.1109\/ISCAS.2000.856000","volume-title":"2000 IEEE International Symposium on Circuits and Systems (ISCAS\u201900)","author":"Kiyota K.","year":"2000","unstructured":"K. Kiyota and K. Fujiyoshi. 2000. Simulated annealing search through general structure floorplans using sequence-pair. In 2000 IEEE International Symposium on Circuits and Systems (ISCAS\u201900), Vol. 3. 77\u201380."},{"key":"e_1_3_1_29_2","volume-title":"2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No. 02CH37353)","volume":"2","author":"Lin Chang-Tzu","year":"2002","unstructured":"Chang-Tzu Lin, De-Sheng Chen, and Yi-Wen Wang. 2002. An efficient genetic algorithm for slicing floorplan area optimization. In 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No. 02CH37353), Vol. 2. IEEE."},{"key":"e_1_3_1_30_2","first-page":"1","volume-title":"2019 56th ACM\/IEEE Design Automation Conference (DAC\u201919)","author":"Lin Y.","year":"2019","unstructured":"Y. Lin, S. Dhar, W. Li, H. Ren, B. Khailany, and D. Z. Pan. 2019. DREAMPIace: Deep learning toolkit-enabled GPU acceleration for modern VLSI placement. In 2019 56th ACM\/IEEE Design Automation Conference (DAC\u201919). 1\u20136."},{"key":"e_1_3_1_31_2","unstructured":"Jingwei Lu. 2010. Fundamental Research on Electronic Design Automation in VLSI Design - Routability . Masters thesis. The Hong Kong Polytechnic University. http:\/\/hdl.handle.net\/10397\/4114."},{"key":"e_1_3_1_32_2","doi-asserted-by":"publisher","DOI":"10.1145\/2699873"},{"key":"e_1_3_1_33_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2391263"},{"key":"e_1_3_1_34_2","unstructured":"Yi-Chen Lu Sai Pentapati and Sung K. Lim. 2020. VLSI placement optimization using graph neural networks. In 34th Conference on Neural Information Processing Systems (NeurIPS\u201920) Workshop on ML for Systems. Computer Science 1\u20135."},{"key":"e_1_3_1_35_2","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-021-03544-w"},{"key":"e_1_3_1_36_2","doi-asserted-by":"publisher","DOI":"10.1109\/43.552084"},{"key":"e_1_3_1_37_2","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055182"},{"key":"e_1_3_1_38_2","doi-asserted-by":"publisher","DOI":"10.1109\/43.511573"},{"key":"e_1_3_1_39_2","doi-asserted-by":"publisher","DOI":"10.1145\/318013.318083"},{"key":"e_1_3_1_40_2","doi-asserted-by":"publisher","DOI":"10.1145\/1455229.1455241"},{"key":"e_1_3_1_41_2","doi-asserted-by":"publisher","DOI":"10.1109\/FOCS.2007.56"},{"key":"e_1_3_1_42_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-68739-1_4"},{"key":"e_1_3_1_43_2","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228416"},{"key":"e_1_3_1_44_2","doi-asserted-by":"crossref","first-page":"5\u2013pp","DOI":"10.1109\/ISVLSI.2006.46","volume-title":"IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI\u201906)","author":"Sun Tsung-Ying","year":"2006","unstructured":"Tsung-Ying Sun, Sheng-Ta Hsieh, Hsiang-Min Wang, and Cheng-Wei Lin. 2006. Floorplanning based on particle swarm optimization. In IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI\u201906). IEEE, 5\u2013pp."},{"key":"e_1_3_1_45_2","unstructured":"Petar Veli\u010dkovi\u0107 Guillem Cucurull Arantxa Casanova Adriana Romero Pietro Lio and Yoshua Bengio. 2018. Graph attention networks. In Proceedings of the International Conference on Learning Representations (ICLR\u201918) 1\u201312."},{"key":"e_1_3_1_46_2","doi-asserted-by":"publisher","DOI":"10.1145\/3394885.3431562"},{"key":"e_1_3_1_47_2","doi-asserted-by":"crossref","unstructured":"Jackey Z. Yan Natarajan Viswanathan and Chris Chu. 2014. An effective floorplan-guided placement algorithm for large-scale mixed-size designs. ACM Transactions on Design Automation of Electronic Systems (TODAES) 19 3 (2014) 1\u201325.","DOI":"10.1145\/2611761"},{"key":"e_1_3_1_48_2","unstructured":"Yiting Liu Ziyi Ju Zhengming Li Mingzhi Dong Hai Zhou Jia Wang Fan Yang Xuan Zeng and Li Shang. 2022. Floorplanning with graph attention. In 2022 59th ACM\/IEEE Design Automation Conference (DAC\u201922) 1\u20136."}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3555804","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3555804","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T17:51:36Z","timestamp":1750182696000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3555804"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,12,24]]},"references-count":47,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2023,3,31]]}},"alternative-id":["10.1145\/3555804"],"URL":"https:\/\/doi.org\/10.1145\/3555804","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,12,24]]},"assertion":[{"value":"2022-02-15","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-07-24","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-12-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}