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Code Optim."],"published-print":{"date-parts":[[2023,3,31]]},"abstract":"<jats:p>Programmable network data planes have extended the capabilities of packet processing in network devices by allowing custom processing pipelines and agnostic packet processing. While a variety of applications can be implemented on current programmable data planes, there are significant constraints due to hardware limitations. One way to meet these constraints is by optimizing data plane programs. Program optimization can be achieved by specializing code that leverages architectural specificity or by compilation passes. In the case of programmable data planes, to respond to the varying requirements of a large set of applications, data plane programs can target different architectures. This leads to difficulties when developers want to reuse the code. One solution to that is to use compiler optimization techniques. We propose performing data plane program specialization to reduce the generated program size. To this end, we propose to specialize in programs written in P4, a Domain Specific Language (DSL) designed for specifying network data planes. The proposed method takes advantage of key aspects of the P4 language to perform a symbolic analysis on a P4 program and then partially evaluate the program to specialize it. The approach we propose is independent of the target architecture. We evaluate the specialization technique by implementing a packet deparser on an FPGA. The results demonstrate that program specialization can reduce the resource usage by a factor of 2 for various packet deparsers.<\/jats:p>","DOI":"10.1145\/3557727","type":"journal-article","created":{"date-parts":[[2022,8,16]],"date-time":"2022-08-16T12:34:36Z","timestamp":1660653276000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Symbolic Analysis for Data Plane Programs Specialization"],"prefix":"10.1145","volume":"20","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4114-1179","authenticated-orcid":false,"given":"Thomas","family":"Luinaud","sequence":"first","affiliation":[{"name":"Polytechnique Montr\u00e9al, Montr\u00e9al, Qu\u00e9bec, Canada"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1721-2520","authenticated-orcid":false,"given":"J. M. Pierre","family":"Langlois","sequence":"additional","affiliation":[{"name":"Polytechnique Montr\u00e9al, Montr\u00e9al, Qu\u00e9bec, Canada"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3404-9959","authenticated-orcid":false,"given":"Yvon","family":"Savaria","sequence":"additional","affiliation":[{"name":"Polytechnique Montr\u00e9al, Montr\u00e9al, Qu\u00e9bec, Canada"}]}],"member":"320","published-online":{"date-parts":[[2022,11,17]]},"reference":[{"key":"e_1_3_2_2_2","unstructured":"2021. Intel\u00ae P4 Suite. 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P416 Language Specification. P4.org. Retrieved June 2021 from https:\/\/p4.org\/p4-spec\/docs\/P4-16-v1.2.2.pdf."},{"key":"e_1_3_2_13_2","doi-asserted-by":"publisher","DOI":"10.1145\/2400682.2400694"},{"key":"e_1_3_2_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICNP.2018.00059"},{"key":"e_1_3_2_15_2","doi-asserted-by":"publisher","DOI":"10.1109\/ANCS.2013.6665172"},{"key":"e_1_3_2_16_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.scico.2006.02.002"},{"key":"e_1_3_2_17_2","doi-asserted-by":"publisher","DOI":"10.1145\/3373360.3380843"},{"key":"e_1_3_2_18_2","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439303"},{"key":"e_1_3_2_19_2","doi-asserted-by":"publisher","DOI":"10.1145\/3447868"},{"key":"e_1_3_2_20_2","unstructured":"p4Lang. 2020. behavioral-model: The reference P4 software switch. (2020). Retrieved June 2021 from https:\/\/github.com\/p4lang\/behavioral-model."},{"key":"e_1_3_2_21_2","unstructured":"p4lang. 2020. p4c: P4 16 reference compiler. (2020). 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