{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:13:08Z","timestamp":1750219988743,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":29,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,11,3]],"date-time":"2022-11-03T00:00:00Z","timestamp":1667433600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"NSF (National Science Foundation)","doi-asserted-by":"publisher","award":["2035610"],"award-info":[{"award-number":["2035610"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,11,3]]},"DOI":"10.1145\/3557988.3569712","type":"proceedings-article","created":{"date-parts":[[2023,1,27]],"date-time":"2023-01-27T17:09:28Z","timestamp":1674839368000},"page":"1-7","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["Limiting Interconnect Heating in Power-Driven Physical Synthesis"],"prefix":"10.1145","author":[{"given":"Xiuyan","family":"Zhang","sequence":"first","affiliation":[{"name":"University of Illinois at Chicago"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shantanu","family":"Dutt","sequence":"additional","affiliation":[{"name":"University of Illinois at Chicago"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,1,27]]},"reference":[{"key":"e_1_3_2_1_2_1","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429428"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429427"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/2647956"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.5555\/2840819.2840879"},{"key":"e_1_3_2_1_6_1","first-page":"337","volume-title":"Rapid gate sizing with fewer iterations of Lagrangian Relaxation,\" 2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","author":"Sharma A.","year":"2017","unstructured":"A. Sharma , D. Chinnery , S. Dhamdhere and C. Chu , \" Rapid gate sizing with fewer iterations of Lagrangian Relaxation,\" 2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD) , 2017 , pp. 337 -- 343 . A. Sharma, D. Chinnery, S. Dhamdhere and C. Chu, \"Rapid gate sizing with fewer iterations of Lagrangian Relaxation,\" 2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), 2017, pp. 337--343."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2305847"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065593"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996777"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2097330"},{"key":"e_1_3_2_1_11_1","first-page":"149","volume-title":"International Symposium on Low Power Electronics and Design","author":"Chinnery D.","year":"2005","unstructured":"D. Chinnery and K. Keutzer , \" Linear programming for sizing, vth and vdd assignment,\" in Proc . International Symposium on Low Power Electronics and Design , 2005 , pp. 149 -- 154 . D. Chinnery and K. Keutzer, \"Linear programming for sizing, vth and vdd assignment,\" in Proc. International Symposium on Low Power Electronics and Design, 2005, pp. 149--154."},{"key":"e_1_3_2_1_12_1","first-page":"705","article-title":"Discrete vt assignment and gate sizing using a self-snapping continuous formulation","author":"Shah S.","year":"2005","unstructured":"S. Shah , et. al. , \" Discrete vt assignment and gate sizing using a self-snapping continuous formulation ,\" ICCAD , 2005 , pp. 705 -- 712 . S. Shah, et. al., \"Discrete vt assignment and gate sizing using a self-snapping continuous formulation,\" ICCAD, 2005, pp. 705--712.","journal-title":"ICCAD"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"crossref","unstructured":"H. Chou Y.-H. Wang and C. C.-P. Chen \"Fast and effective gate-sizing with multiple-vt assignment using generalized lagrangian relaxation \" ASP-DAC 2005.  H. Chou Y.-H. Wang and C. C.-P. Chen \"Fast and effective gate-sizing with multiple-vt assignment using generalized lagrangian relaxation \" ASP-DAC 2005.","DOI":"10.1145\/1120725.1120881"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.895793"},{"key":"e_1_3_2_1_15_1","volume-title":"Efficient and accurate gate sizing with piecewise convex delay models,\" DAC","author":"Tennakoon H.","year":"2005","unstructured":"H. Tennakoon and C. Sechen , \" Efficient and accurate gate sizing with piecewise convex delay models,\" DAC , 2005 . H. Tennakoon and C. Sechen, \"Efficient and accurate gate sizing with piecewise convex delay models,\" DAC, 2005."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"crossref","unstructured":"H Tennakoon and C Sechen \"Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step \" In Proceedings of the 2002 IEEE\/ACM international conference on Computer-aided design 2002.  H Tennakoon and C Sechen \"Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step \" In Proceedings of the 2002 IEEE\/ACM international conference on Computer-aided design 2002.","DOI":"10.1145\/774572.774631"},{"key":"e_1_3_2_1_17_1","volume-title":"Gate sizing by lagrangian relaxation revisited,\" ICCAD","author":"Wang J.","year":"2007","unstructured":"J. Wang , D. Das , and H. Zhou , \" Gate sizing by lagrangian relaxation revisited,\" ICCAD , 2007 . J. Wang, D. Das, and H. Zhou, \"Gate sizing by lagrangian relaxation revisited,\" ICCAD, 2007."},{"key":"e_1_3_2_1_18_1","article-title":"Gate sizing for cell-library-based designs","author":"Hu S.","year":"2009","unstructured":"S. Hu , M. Ketkar , and J. Hu , \" Gate sizing for cell-library-based designs ,\" IEEE Transactions on Computer Aided Design , 2009 . S. Hu, M. Ketkar, and J. Hu, \"Gate sizing for cell-library-based designs,\" IEEE Transactions on Computer Aided Design, 2009.","journal-title":"IEEE Transactions on Computer Aided Design"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"crossref","unstructured":"Y Liu and J Hu \"GPU-based parallelization for fast circuit optimization \" TODAES 2011.  Y Liu and J Hu \"GPU-based parallelization for fast circuit optimization \" TODAES 2011.","DOI":"10.1016\/B978-0-12-384988-5.00024-3"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2035575"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.5555\/2132325.2132484"},{"key":"e_1_3_2_1_22_1","volume-title":"Gate sizing by lagrangian relaxation revisited,\" ICCAD","author":"Wang J.","year":"2007","unstructured":"J. Wang , D. Das , and H. Zhou , \" Gate sizing by lagrangian relaxation revisited,\" ICCAD , 2007 . J. Wang, D. Das, and H. Zhou, \"Gate sizing by lagrangian relaxation revisited,\" ICCAD, 2007."},{"key":"e_1_3_2_1_23_1","volume-title":"Intl. Symposium on Physical Design","author":"Ozdal M. M.","year":"2012","unstructured":"M. M. Ozdal , et. al., \"The ISPD-2012 discrete cell sizing contest and benchmark suite,\" in Proc . Intl. Symposium on Physical Design , 2012 . M. M. Ozdal, et. al., \"The ISPD-2012 discrete cell sizing contest and benchmark suite,\" in Proc. Intl. Symposium on Physical Design, 2012."},{"key":"e_1_3_2_1_24_1","volume-title":"ACM","author":"Ozdal M. M.","year":"2013","unstructured":"M. M. Ozdal improved benchmark suite for the ISPD-2013 discrete cell sizing contest,\" In Proceedings of the 2013 ACM international symposium on International symposium on physical design, pages 168--170 . ACM , 2013 . M. M. Ozdal et al., \"An improved benchmark suite for the ISPD-2013 discrete cell sizing contest,\" In Proceedings of the 2013 ACM international symposium on International symposium on physical design, pages 168--170. ACM, 2013."},{"key":"e_1_3_2_1_25_1","volume-title":"Pearson Education","author":"Ahuja R. K. K.","year":"1993","unstructured":"R. K. K. Ahuja , : Theory, Algorithms, and Applications , Pearson Education , 1993 . R. K. K. Ahuja, et al., Network Flows: Theory, Algorithms, and Applications, Pearson Education, 1993."},{"key":"e_1_3_2_1_26_1","volume-title":"Adaptive Dynamic Cost Updating Procedure for Solving Fixed Charge Network Flow Problems\", Computational Optimization and Applications journal","author":"Nahapetyan A.","year":"2008","unstructured":"A. Nahapetyan , and P. Pardalos , \" Adaptive Dynamic Cost Updating Procedure for Solving Fixed Charge Network Flow Problems\", Computational Optimization and Applications journal , 2008 . A. Nahapetyan, and P. Pardalos, \"Adaptive Dynamic Cost Updating Procedure for Solving Fixed Charge Network Flow Problems\", Computational Optimization and Applications journal, 2008."},{"key":"e_1_3_2_1_27_1","volume-title":"Fast and accurate wire delay estimation for physical synthesis of large ASICs,\" GLSVLSI","author":"Puri R.","year":"2002","unstructured":"R. Puri , D. S. Kung , and A. D. Drumm , \" Fast and accurate wire delay estimation for physical synthesis of large ASICs,\" GLSVLSI , 2002 . R. Puri, D. S. Kung, and A. D. Drumm, \"Fast and accurate wire delay estimation for physical synthesis of large ASICs,\" GLSVLSI, 2002."},{"key":"e_1_3_2_1_28_1","first-page":"364","article-title":"The elmore delay as bound for rc trees with generalized input signals","author":"Gupta R.","year":"1995","unstructured":"R. Gupta , et. al. , \" The elmore delay as bound for rc trees with generalized input signals ,\" in Proc. ACM\/IEEE DAC , 1995 , pp. 364 -- 369 . R. Gupta, et. al., \"The elmore delay as bound for rc trees with generalized input signals,\" in Proc. ACM\/IEEE DAC, 1995, pp. 364--369.","journal-title":"Proc. ACM\/IEEE DAC"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.331409"},{"key":"e_1_3_2_1_30_1","unstructured":"https:\/\/www.synopsys.com\/implementation-and-signoff\/signoff\/primetime.html  https:\/\/www.synopsys.com\/implementation-and-signoff\/signoff\/primetime.html"}],"event":{"name":"ICCAD '22: IEEE\/ACM International Conference on Computer-Aided Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CAS","IEEE CEDA"],"location":"San Diego California","acronym":"ICCAD '22"},"container-title":["Proceedings of the 24th ACM\/IEEE Workshop on System Level Interconnect Pathfinding"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3557988.3569712","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3557988.3569712","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T17:49:31Z","timestamp":1750182571000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3557988.3569712"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,11,3]]},"references-count":29,"alternative-id":["10.1145\/3557988.3569712","10.1145\/3557988"],"URL":"https:\/\/doi.org\/10.1145\/3557988.3569712","relation":{},"subject":[],"published":{"date-parts":[[2022,11,3]]},"assertion":[{"value":"2023-01-27","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}