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However, the special isolation logic needed to ensure electrical protection between\n            <jats:italic>off<\/jats:italic>\n            and\n            <jats:italic>on<\/jats:italic>\n            domains makes fine-grained power domains area- and timing-inefficient. We propose a novel design of the CGRA routing fabric that reduces the area overhead of power domain boundary protection from around 9% to less than 1% without incurring any extra timing delay from the isolation cells. Conventional Unified Power Format based flow for power domain boundary protection does not support this design choice. Therefore, we create our own compiler-like passes that iteratively introduce the needed design changes, and formally verify the transformations using methods based on satisfiability modulo theories. These passes also let us optimize how we handle test and debug signals through the\n            <jats:italic>off<\/jats:italic>\n            tiles in the CGRA. Using our framework, we add power domains to a CGRA that we designed and taped out. The CGRA has 32 \u00d7 16 processing element and memory tiles and 4-MB secondary memory. We address the implementation challenges encountered due to the introduction of fine-grained power domains, including the addressing of the CGRA tiles, the power grid design, well substrate connections, and distribution of global signals. Our CGRA achieves up to 83% reduction in leakage power and 26% reduction in total power versus an identical CGRA without multiple power domains, for a range of image processing and machine learning applications.\n          <\/jats:p>","DOI":"10.1145\/3558394","type":"journal-article","created":{"date-parts":[[2022,8,27]],"date-time":"2022-08-27T10:28:26Z","timestamp":1661596106000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains"],"prefix":"10.1145","volume":"16","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7821-0460","authenticated-orcid":false,"given":"Ankita","family":"Nayak","sequence":"first","affiliation":[{"name":"Stanford University, Stanford, CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8902-2518","authenticated-orcid":false,"given":"Keyi","family":"Zhang","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2078-0991","authenticated-orcid":false,"given":"Rajsekhar","family":"Setaluri","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2549-9525","authenticated-orcid":false,"given":"Alex","family":"Carsello","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1555-5784","authenticated-orcid":false,"given":"Makai","family":"Mann","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2385-619X","authenticated-orcid":false,"given":"Christopher","family":"Torng","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4359-3638","authenticated-orcid":false,"given":"Stephen","family":"Richardson","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3323-7752","authenticated-orcid":false,"given":"Rick","family":"Bahr","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3474-9752","authenticated-orcid":false,"given":"Pat","family":"Hanrahan","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3245-7542","authenticated-orcid":false,"given":"Mark","family":"Horowitz","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8834-8663","authenticated-orcid":false,"given":"Priyanka","family":"Raina","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2023,4,2]]},"reference":[{"key":"e_1_3_2_2_2","unstructured":"Andrew Adams. n.d. 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Retrieved September 6 2022 from https:\/\/www.techonline.com\/tech-papers\/xilinx-7-series-fpgas-the-logical-advantage\/."},{"key":"e_1_3_2_36_2","doi-asserted-by":"crossref","first-page":"714","DOI":"10.1109\/ISCAS.2016.7527340","volume-title":"Proceedings of the 2016 IEEE International Symposium on Circuits and Systems (ISCAS\u201916)","author":"Miniskar Narasinga Rao","year":"2016","unstructured":"Narasinga Rao Miniskar, Rahul R. Patil, Raj Narayana Gadde, Young-Chul Rams Cho, Sukjin Kim, and Shi Hwa Lee. 2016. Intra mode power saving methodology for CGRA-based reconfigurable processor architectures. In Proceedings of the 2016 IEEE International Symposium on Circuits and Systems (ISCAS\u201916). IEEE, Los Alamitos, CA, 714\u2013717."},{"key":"e_1_3_2_37_2","doi-asserted-by":"publisher","DOI":"10.1109\/SOFTCOM.2015.7314103"},{"key":"e_1_3_2_38_2","unstructured":"Chris Nicol. 2017. A Coarse Grain Reconfigurable Array (CGRA) for Statically Scheduled Data Flow Computing . White Paper. Wave Computing."},{"key":"e_1_3_2_39_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.94"},{"key":"e_1_3_2_40_2","unstructured":"Wikipedia. n.d. Boolean Satisfiability Problem. Retrieved September 6 2022 from https:\/\/en.wikipedia.org\/wiki\/Boolean_satisfiability_problem."},{"key":"e_1_3_2_41_2","unstructured":"Raj Setaluri. n.d. Gemstone. Retrieved September 6 2022 from https:\/\/github.com\/StanfordAHA\/gemstone."},{"key":"e_1_3_2_42_2","first-page":"1","volume-title":"Proceedings of the 2015 IEEE 33rd VLSI Test Symposium (VTS\u201915)","author":"Sharafinejad Reza","year":"2015","unstructured":"Reza Sharafinejad, Bijan Alizadeh, and Masahiro Fujita. 2015. UPF-based formal verification of low power techniques in modern processors. In Proceedings of the 2015 IEEE 33rd VLSI Test Symposium (VTS\u201915). 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