{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,2]],"date-time":"2026-07-02T04:30:06Z","timestamp":1782966606756,"version":"3.54.5"},"publisher-location":"New York, NY, USA","reference-count":39,"publisher":"ACM","license":[{"start":{"date-parts":[[2022,10,8]],"date-time":"2022-10-08T00:00:00Z","timestamp":1665187200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"Swedish Foundation for Strategic Research","award":["CHI19-0048"],"award-info":[{"award-number":["CHI19-0048"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2022,10,8]]},"DOI":"10.1145\/3559009.3569653","type":"proceedings-article","created":{"date-parts":[[2023,1,27]],"date-time":"2023-01-27T14:02:50Z","timestamp":1674828170000},"page":"96-108","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["FlatPack"],"prefix":"10.1145","author":[{"given":"Albin","family":"Eldst\u00e5l-Ahrens","sequence":"first","affiliation":[{"name":"Chalmers University of Technology, Gothenburg, Sweden"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Angelos","family":"Arelakis","sequence":"additional","affiliation":[{"name":"ZeroPoint Technologies AB, Gothenburg, Sweden"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ioannis","family":"Sourdis","sequence":"additional","affiliation":[{"name":"Chalmers University of Technology, Gothenburg, Sweden"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2023,1,27]]},"reference":[{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","unstructured":"A. Arelakis F. Dahlgren and P. Stenstrom. 2015. HyComp: a hybrid cache compression method for selection of data-type-specific compression methods. In MICRO. IEEE Waikiki Hawaii USA 38--49.  A. Arelakis F. Dahlgren and P. Stenstrom. 2015. HyComp: a hybrid cache compression method for selection of data-type-specific compression methods. In MICRO. IEEE Waikiki Hawaii USA 38--49.","DOI":"10.1145\/2830772.2830823"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853231"},{"key":"e_1_3_2_1_4_1","volume-title":"2015 IEEE International Conference on Networking, Architecture and Storage (NAS). IEEE","author":"Cao Yanan","year":"2015","unstructured":"Yanan Cao , Long Chen , and Zhao Zhang . 2015 . Flexible memory: A novel main memory architecture with block-level memory compression . In 2015 IEEE International Conference on Networking, Architecture and Storage (NAS). IEEE , Boston, Massachusetts, USA, 285--294. Yanan Cao, Long Chen, and Zhao Zhang. 2015. Flexible memory: A novel main memory architecture with block-level memory compression. In 2015 IEEE International Conference on Networking, Architecture and Storage (NAS). IEEE, Boston, Massachusetts, USA, 285--294."},{"key":"e_1_3_2_1_5_1","volume-title":"C-pack: A high-performance microprocessor cache compression algorithm","author":"Chen Xi","year":"2010","unstructured":"Xi Chen , Lei Yang , Robert P Dick , Li Shang , and Haris Lekatsas . 2010 . C-pack: A high-performance microprocessor cache compression algorithm . IEEE transactions on very large scale integration (VLSI) systems 18, 8 (2010), 1196--1208. Xi Chen, Lei Yang, Robert P Dick, Li Shang, and Haris Lekatsas. 2010. C-pack: A high-performance microprocessor cache compression algorithm. IEEE transactions on very large scale integration (VLSI) systems 18, 8 (2010), 1196--1208."},{"key":"e_1_3_2_1_6_1","volume-title":"Compresso: Pragmatic Main Memory Compression","author":"Choukse E.","year":"2018","unstructured":"E. Choukse , M. Erez , and A. R. Alameldeen . 2018 . Compresso: Pragmatic Main Memory Compression . In MICRO. IEEE , Fukuoka, Japan , 546--558. E. Choukse, M. Erez, and A. R. Alameldeen. 2018. Compresso: Pragmatic Main Memory Compression. In MICRO. IEEE, Fukuoka, Japan, 546--558."},{"key":"e_1_3_2_1_7_1","volume-title":"Buddy Compression: Enabling Larger Memory for Deep Learning and HPC Workloads on GPUs. In 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA). ACM\/IEEE","author":"Choukse Esha","unstructured":"Esha Choukse , Michael B. Sullivan , Mike O'Connor , Mattan Erez , Jeff Pool , David Nellans , and Stephen W. Keckler . 2020 . Buddy Compression: Enabling Larger Memory for Deep Learning and HPC Workloads on GPUs. In 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA). ACM\/IEEE , Valencia, Spain, 926--939. Esha Choukse, Michael B. Sullivan, Mike O'Connor, Mattan Erez, Jeff Pool, David Nellans, and Stephen W. Keckler. 2020. Buddy Compression: Enabling Larger Memory for Deep Learning and HPC Workloads on GPUs. In 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA). ACM\/IEEE, Valencia, Spain, 926--939."},{"key":"e_1_3_2_1_8_1","volume-title":"SPEC CPU 2017","author":"Standard Performance Evaluation Corporation","year":"2017","unstructured":"Standard Performance Evaluation Corporation . 2017 . SPEC CPU 2017 . Retrieved 2021-07-30 from https:\/\/www.spec.org\/cpu2017 Standard Performance Evaluation Corporation. 2017. SPEC CPU 2017. Retrieved 2021-07-30 from https:\/\/www.spec.org\/cpu2017"},{"key":"e_1_3_2_1_9_1","volume-title":"News","volume":"33","author":"Ekman Magnus","year":"2005","unstructured":"Magnus Ekman and Per Stenstrom . 2005 . A robust main-memory compression scheme. In SIGARCH C.A . News , Vol. 33 . ACM, New York, New York, USA, 74--85. Magnus Ekman and Per Stenstrom. 2005. A robust main-memory compression scheme. In SIGARCH C.A. News, Vol. 33. ACM, New York, New York, USA, 74--85."},{"key":"e_1_3_2_1_10_1","volume-title":"AVR: Reducing Memory Traffic with Approximate Value Reconstruction. In ICPP. ACM, Kyoto, Japan, 1--10.","author":"Eldst\u00e5l-Damlin Albin","year":"2019","unstructured":"Albin Eldst\u00e5l-Damlin , Pedro Trancoso , and Ioannis Sourdis . 2019 . AVR: Reducing Memory Traffic with Approximate Value Reconstruction. In ICPP. ACM, Kyoto, Japan, 1--10. Albin Eldst\u00e5l-Damlin, Pedro Trancoso, and Ioannis Sourdis. 2019. AVR: Reducing Memory Traffic with Approximate Value Reconstruction. In ICPP. ACM, Kyoto, Japan, 1--10."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/3481641"},{"key":"e_1_3_2_1_12_1","volume-title":"Article 40 (Nov.","author":"Eldst\u00e5l-Ahrens Albin","year":"2020","unstructured":"Albin Eldst\u00e5l-Ahrens and Ioannis Sourdis . 2020. MemSZ: Squeezing Memory Traffic with Lossy Compression. ACM TACO 17, 4 , Article 40 (Nov. 2020 ), 40:1--40:25 pages. Albin Eldst\u00e5l-Ahrens and Ioannis Sourdis. 2020. MemSZ: Squeezing Memory Traffic with Lossy Compression. ACM TACO 17, 4, Article 40 (Nov. 2020), 40:1--40:25 pages."},{"key":"e_1_3_2_1_13_1","volume-title":"Management of Guest OS Memory Compression In Virtualized Systems. Patent US20080307188A1.","author":"Peter","unstructured":"Peter A. Franaszek and Dan E. Poff. 2007 . Management of Guest OS Memory Compression In Virtualized Systems. Patent US20080307188A1. Peter A. Franaszek and Dan E. Poff. 2007. Management of Guest OS Memory Compression In Virtualized Systems. Patent US20080307188A1."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"crossref","unstructured":"D. Genbrugge S. Eyerman and L. Eeckhout. 2010. Interval simulation: Raising the level of abstraction in architectural simulation. In HPCA. IEEE Bangalore India 1--12.  D. Genbrugge S. Eyerman and L. Eeckhout. 2010. Interval simulation: Raising the level of abstraction in architectural simulation. In HPCA. IEEE Bangalore India 1--12.","DOI":"10.1109\/HPCA.2010.5416636"},{"key":"e_1_3_2_1_15_1","volume-title":"11th International Symposium on High-Performance Computer Architecture. IEEE","author":"Hallnor E.G.","unstructured":"E.G. Hallnor and S.K. Reinhardt . 2005. A unified compressed memory hierarchy . In 11th International Symposium on High-Performance Computer Architecture. IEEE , San Fransisco, California, USA, 201--212. E.G. Hallnor and S.K. Reinhardt. 2005. A unified compressed memory hierarchy. In 11th International Symposium on High-Performance Computer Architecture. IEEE, San Fransisco, California, USA, 201--212."},{"key":"e_1_3_2_1_16_1","volume-title":"Attach\u00e9: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads","author":"Hong S.","year":"2018","unstructured":"S. Hong , P. J. Nair , B. Abali , A. Buyuktosunoglu , K. Kim , and M. Healy . 2018 . Attach\u00e9: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads . In MICRO. IEEE , Fukuoka, Japan , 326--338. S. Hong, P. J. Nair, B. Abali, A. Buyuktosunoglu, K. Kim, and M. Healy. 2018. Attach\u00e9: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads. In MICRO. IEEE, Fukuoka, Japan, 326--338."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/3151033"},{"key":"e_1_3_2_1_18_1","volume-title":"Bit-plane compression: Transforming data for better compression in many-core architectures","author":"Kim Jungrae","unstructured":"Jungrae Kim , Michael Sullivan , Esha Choukse , and Mattan Erez . 2016. Bit-plane compression: Transforming data for better compression in many-core architectures . In ISCA. ACM\/IEEE, Seoul, Republic of Korea , 329--340. Jungrae Kim, Michael Sullivan, Esha Choukse, and Mattan Erez. 2016. Bit-plane compression: Transforming data for better compression in many-core architectures. In ISCA. ACM\/IEEE, Seoul, Republic of Korea, 329--340."},{"key":"e_1_3_2_1_19_1","volume-title":"SLC: Memory access granularity aware selective lossy compression for GPUs","author":"Lal Sohan","year":"2019","unstructured":"Sohan Lal , Jan Lucas , and Ben Juurlink . 2019 . SLC: Memory access granularity aware selective lossy compression for GPUs . In DATE. IEEE, IEEE , Grenoble, France , 1184--1189. Sohan Lal, Jan Lucas, and Ben Juurlink. 2019. SLC: Memory access granularity aware selective lossy compression for GPUs. In DATE. IEEE, IEEE, Grenoble, France, 1184--1189."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1250880"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1145\/2898361"},{"key":"e_1_3_2_1_22_1","volume-title":"Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, and Norman P. Jouppi.","author":"Li Sheng","year":"2009","unstructured":"Sheng Li , Jung Ho Ahn , Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, and Norman P. Jouppi. 2009 . McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures. In MICRO. IEEE, New York, New York, USA , 469--480. Sheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, and Norman P. Jouppi. 2009. McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures. In MICRO. IEEE, New York, New York, USA, 469--480."},{"key":"e_1_3_2_1_23_1","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065034"},{"key":"e_1_3_2_1_24_1","volume-title":"A tool to model large caches. HP lab. 27","author":"Muralimanohar Naveen","year":"2009","unstructured":"Naveen Muralimanohar , Rajeev Balasubramonian , and Norman P Jouppi . 2009. CACTI 6.0 : A tool to model large caches. HP lab. 27 ( 2009 ), 22--31. Naveen Muralimanohar, Rajeev Balasubramonian, and Norman P Jouppi. 2009. CACTI 6.0: A tool to model large caches. HP lab. 27 (2009), 22--31."},{"key":"e_1_3_2_1_25_1","first-page":"45","article-title":"Introducing the graph 500","volume":"19","author":"Murphy Richard C","year":"2010","unstructured":"Richard C Murphy , Kyle B Wheeler , Brian W Barrett , and James A Ang . 2010 . Introducing the graph 500 . Cray Users Group (CUG) 19 (2010), 45 -- 74 . Richard C Murphy, Kyle B Wheeler, Brian W Barrett, and James A Ang. 2010. Introducing the graph 500. Cray Users Group (CUG) 19 (2010), 45--74.","journal-title":"Cray Users Group (CUG)"},{"key":"e_1_3_2_1_26_1","volume-title":"COP: To Compress and Protect Main Memory. In 42nd Annual International Symposium on Computer Architecture","author":"Palframan David J.","unstructured":"David J. Palframan , Nam Sung Kim , and Mikko H. Lipasti . 2015 . COP: To Compress and Protect Main Memory. In 42nd Annual International Symposium on Computer Architecture ( Portland, Oregon) (ISCA '15). ACM, 682--693. David J. Palframan, Nam Sung Kim, and Mikko H. Lipasti. 2015. COP: To Compress and Protect Main Memory. In 42nd Annual International Symposium on Computer Architecture (Portland, Oregon) (ISCA '15). ACM, 682--693."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446722"},{"key":"e_1_3_2_1_28_1","volume-title":"Linearly compressed pages: a low-complexity, low-latency main memory compression framework","author":"Pekhimenko Gennady","unstructured":"Gennady Pekhimenko , Vivek Seshadri , Yoongu Kim , Hongyi Xin , Onur Mutlu , Phillip B Gibbons , Michael A Kozuch , and Todd C Mowry . 2016. Linearly compressed pages: a low-complexity, low-latency main memory compression framework . In MICRO. IEEE , Taipei, Taiwan , 172--184. Gennady Pekhimenko, Vivek Seshadri, Yoongu Kim, Hongyi Xin, Onur Mutlu, Phillip B Gibbons, Michael A Kozuch, and Todd C Mowry. 2016. Linearly compressed pages: a low-complexity, low-latency main memory compression framework. In MICRO. IEEE, Taipei, Taiwan, 172--184."},{"key":"e_1_3_2_1_29_1","volume-title":"PACT","author":"Pekhimenko Gennady","unstructured":"Gennady Pekhimenko , Vivek Seshadri , Onur Mutlu , Michael A Kozuch , Phillip B Gibbons , and Todd C Mowry . 2012. Base-delta-immediate compression: Practical data compression for on-chip caches . In PACT . ACM , Minneapolis, Minnesota, USA , 377--388. Gennady Pekhimenko, Vivek Seshadri, Onur Mutlu, Michael A Kozuch, Phillip B Gibbons, and Todd C Mowry. 2012. Base-delta-immediate compression: Practical data compression for on-chip caches. In PACT. ACM, Minneapolis, Minnesota, USA, 377--388."},{"key":"e_1_3_2_1_30_1","first-page":"980","article-title":"Approximate Memory Compression","volume":"28","author":"Ranjan Ashish","year":"2020","unstructured":"Ashish Ranjan , Arnab Raha , Vijay Raghunathan , and Anand Raghunathan . 2020 . Approximate Memory Compression . IEEE TVLSI 28 , 4 (2020), 980 -- 991 . Ashish Ranjan, Arnab Raha, Vijay Raghunathan, and Anand Raghunathan. 2020. Approximate Memory Compression. IEEE TVLSI 28, 4 (2020), 980--991.","journal-title":"IEEE TVLSI"},{"key":"e_1_3_2_1_31_1","first-page":"16","article-title":"DRAMSim2: A cycle accurate memory system simulator","volume":"10","author":"Rosenfeld Paul","year":"2011","unstructured":"Paul Rosenfeld , Elliott Cooper-Balis , and Bruce Jacob . 2011 . DRAMSim2: A cycle accurate memory system simulator . IEEE CAL 10 , 1 (2011), 16 -- 19 . Paul Rosenfeld, Elliott Cooper-Balis, and Bruce Jacob. 2011. DRAMSim2: A cycle accurate memory system simulator. IEEE CAL 10, 1 (2011), 16--19.","journal-title":"IEEE CAL"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/3406177"},{"key":"e_1_3_2_1_33_1","volume-title":"Decoupled sectored caches: conciliating low tag implementation cost and low miss ratio","author":"Seznec A.","unstructured":"A. Seznec . 1994. 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IEEE, Orlando, Florida, USA, 638--649."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.452.0271"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378453"},{"key":"e_1_3_2_1_37_1","volume-title":"SI (dec","author":"Waldspurger Carl A.","year":"2003","unstructured":"Carl A. Waldspurger . 2003. Memory Resource Management in VMware ESX Server. SIGOPS Oper. Syst. Rev. 36 , SI (dec 2003 ), 181--194. Carl A. Waldspurger. 2003. Memory Resource Management in VMware ESX Server. SIGOPS Oper. Syst. Rev. 36, SI (dec 2003), 181--194."},{"key":"e_1_3_2_1_38_1","volume-title":"Pmbench: A micro-benchmark for profiling paging performance on a system with low-latency SSDs. In Information Technology-New Generations","author":"Yang Jisoo","year":"2018","unstructured":"Jisoo Yang and Julian Seymour . 2018 . Pmbench: A micro-benchmark for profiling paging performance on a system with low-latency SSDs. In Information Technology-New Generations . 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Buri: Scaling big-memory computing with hardware-based memory expansion. ACM Transactions on Architecture and Code Optimization (TACO) 12, 3 (2015), 31.","journal-title":"ACM Transactions on Architecture and Code Optimization (TACO)"}],"event":{"name":"PACT '22: International Conference on Parallel Architectures and Compilation Techniques","location":"Chicago Illinois","acronym":"PACT '22","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IFIP WG 10.3 IFIP WG 10.3","IEEE CS"]},"container-title":["Proceedings of the International Conference on Parallel Architectures and Compilation Techniques"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3559009.3569653","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3559009.3569653","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:02:38Z","timestamp":1750186958000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3559009.3569653"}},"subtitle":["Flexible Compaction of Compressed Memory"],"short-title":[],"issued":{"date-parts":[[2022,10,8]]},"references-count":39,"alternative-id":["10.1145\/3559009.3569653","10.1145\/3559009"],"URL":"https:\/\/doi.org\/10.1145\/3559009.3569653","relation":{},"subject":[],"published":{"date-parts":[[2022,10,8]]},"assertion":[{"value":"2023-01-27","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}