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This in turn may affect the Quality-of-Service (QoS) delivered by these tasks. In this article, we focus towards the design of a QoS-aware memory controller targeted towards soft real-time systems. The proposed memory controller tries to generate an urgency-based schedule for the contending memory requests based on the allowable response time latencies associated with each request. The objective is to improve task-level response time predictability while maximizing acquired QoS. Exhaustive experiments carried out using real memory traces and standard simulation tools exhibit the practical efficacy of the proposed memory controller design.<\/jats:p>","DOI":"10.1145\/3561052","type":"journal-article","created":{"date-parts":[[2022,9,7]],"date-time":"2022-09-07T11:29:10Z","timestamp":1662550150000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["A Predictable QoS-aware Memory Request Scheduler for Soft Real-time Systems"],"prefix":"10.1145","volume":"22","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7580-2065","authenticated-orcid":false,"given":"Aswathy","family":"N S","sequence":"first","affiliation":[{"name":"Dept. of CSE, Indian Institute of Technology Guwahati, Guwahati, Assam, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5930-2180","authenticated-orcid":false,"given":"Arnab","family":"Sarkar","sequence":"additional","affiliation":[{"name":"ATDC, Indian Institute of Technology Kharagpur, Kharagpur, West Bengal, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9376-7686","authenticated-orcid":false,"given":"Hemangee","family":"Kapoor","sequence":"additional","affiliation":[{"name":"Dept. of CSE, Indian Institute of Technology Guwahati, Guwahati, Assam, India"}]}],"member":"320","published-online":{"date-parts":[[2023,1,24]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.5555\/2096007"},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2008.21"},{"key":"e_1_3_1_4_2","article-title":"DDR3 SDRAM specification","author":"Association JEDEC Solid State Technology","year":"2012","unstructured":"JEDEC Solid State Technology Association et\u00a0al. 2012. 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