{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,12]],"date-time":"2026-05-12T08:39:43Z","timestamp":1778575183300,"version":"3.51.4"},"reference-count":182,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2023,3,11]],"date-time":"2023-03-11T00:00:00Z","timestamp":1678492800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2023,6,30]]},"abstract":"<jats:p>This article presents a critical literature review on the security aspects of field-programmable gate array (FPGA) devices. FPGA devices present unique challenges to cybersecurity through their reconfigurable nature. The article also pays special attention to emerging system-on-chip (SoC) FPGA devices that incorporate a hard processing system (HPS) on the same die as the FPGA logic. While this incorporation reduces the need for vulnerable external signals, the HPS in SoC FPGA devices adds a level of complexity that is not present for stand-alone FPGA devices. This added complexity necessarily hands over the task of securing the device to developers. Even with standard security features in place, the HPS might still have unhindered access to the FPGA logic. A single software flaw could open up a breach that might allow an attacker to extract the FPGA\u2019s configuration data. A robust cybersecurity strategy is thus required for developers. As such, this work aims to provide the groundwork to build a solid threat-based cybersecurity design strategy that is specially adapted to SoC FPGA devices.<\/jats:p>","DOI":"10.1145\/3561515","type":"journal-article","created":{"date-parts":[[2022,9,15]],"date-time":"2022-09-15T09:56:18Z","timestamp":1663235778000},"page":"1-33","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":28,"title":["A Survey on FPGA Cybersecurity Design Strategies"],"prefix":"10.1145","volume":"16","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7075-9632","authenticated-orcid":false,"given":"Alexandre","family":"Proulx","sequence":"first","affiliation":[{"name":"Universit\u00e9 Laval, Qu\u00e9bec, QC, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7904-6137","authenticated-orcid":false,"given":"Jean-Yves","family":"Chouinard","sequence":"additional","affiliation":[{"name":"Universit\u00e9 Laval, Qu\u00e9bec, QC, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7368-9484","authenticated-orcid":false,"given":"Paul","family":"Fortier","sequence":"additional","affiliation":[{"name":"Universit\u00e9 Laval, Qu\u00e9bec, QC, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1766-7528","authenticated-orcid":false,"given":"Amine","family":"Miled","sequence":"additional","affiliation":[{"name":"Universit\u00e9 Laval, Qu\u00e9bec, QC, Canada"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,3,11]]},"reference":[{"key":"e_1_3_2_2_2","article-title":"SiliconToaster: A Cheap and Programmable EM Injector for Extracting Secrets","author":"Abdellatif Karim M.","year":"2020","unstructured":"Karim M. Abdellatif and Olivier H\u00e9riveaux. 2020. SiliconToaster: A Cheap and Programmable EM Injector for Extracting Secrets. Cryptology ePrint Archive, Report 2020\/1115. https:\/\/eprint.iacr.org\/2020\/1115.","journal-title":"Cryptology ePrint Archive, Report 2020\/1115"},{"key":"e_1_3_2_3_2","doi-asserted-by":"crossref","first-page":"182","DOI":"10.1007\/978-3-642-12510-2_13","volume-title":"Smart Card Research and Advanced Application","author":"Agoyan Michel","year":"2010","unstructured":"Michel Agoyan, Jean-Max Dutertre, David Naccache, Bruno Robisson, and Assia Tria. 2010. When clocks fail: On critical paths and clock faults. In Smart Card Research and Advanced Application, Dieter Gollmann, Jean-Louis Lanet, and Julien Iguchi-Cartigny (Eds.). Springer, Berlin, Germany, 182\u2013193."},{"key":"e_1_3_2_4_2","doi-asserted-by":"crossref","first-page":"1490","DOI":"10.23919\/DATE51398.2021.9474026","volume-title":"Proceedings of the 2021 Design, Automation, and Test in Europe Conference and Exhibition (DATE\u201921)","author":"Ahmed Qazi Arbab","year":"2021","unstructured":"Qazi Arbab Ahmed, Tobias Wiersema, and Marco Platzner. 2021. Malicious routing: Circumventing bitstream-level verification for FPGAs. In Proceedings of the 2021 Design, Automation, and Test in Europe Conference and Exhibition (DATE\u201921). 1490\u20131495. DOI:10.23919\/DATE51398.2021.9474026"},{"key":"e_1_3_2_5_2","doi-asserted-by":"crossref","first-page":"48","DOI":"10.1109\/FDTC.2019.00015","volume-title":"Proceedings of the 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC\u201919)","author":"Alam Mahbub","year":"2019","unstructured":"Mahbub Alam, Shahin Tajik, Fatemeh Ganji, Mark Tehranipoor, and Domenic Forte. 2019. RAM-Jam: Remote temperature and voltage fault attack on FPGAs using memory collisions. In Proceedings of the 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC\u201919). 48\u201355. DOI:10.1109\/FDTC.2019.00015"},{"key":"e_1_3_2_6_2","unstructured":"Amazonaws.com. 2020. PolarFire FPGA Design Flow Libero SoC (v12.6). Retrieved January 30 2022 from http:\/\/coredocs.s3.amazonaws.com\/Libero\/12_6_0\/Tool\/pf_des_flow_ug.pdf."},{"key":"e_1_3_2_7_2","unstructured":"AMD-Xilinx. 2007. UG002\u2014Virtex-II Platform FPGA User Guide. Retrieved January 30 2022 from https:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug002.pdf."},{"key":"e_1_3_2_8_2","unstructured":"AMD-Xilinx. 2014. UG109\u2014Programming ARM TrustZone Architecture on the Xilinx Zynq-7000 All Programmable SoC (v1.0). Retrieved September 23 2022 from https:\/\/docs.xilinx.com\/v\/u\/en-US\/ug1019-zynq-trustzone."},{"key":"e_1_3_2_9_2","unstructured":"AMD-Xilinx. 2019. UG585 Zynq-7000 SoC Technical Reference Manual v1.12.2. Retrieved January 30 2022 from https:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug585-Zynq-7000-TRM.pdf."},{"key":"e_1_3_2_10_2","unstructured":"AMD-Xilinx. 2020. UG892\u2014Vivado Design Flows Overview. Retrieved January 30 2022 from https:\/\/www.xilinx.com\/support\/documentation\/sw_manuals\/xilinx2020_2\/ug892-vivado-design-flows-overview.pdf."},{"key":"e_1_3_2_11_2","unstructured":"AMD-Xilinx. 2022. Design Advisory for Zynq-7000: FSBL Authentication Attack. Retrieved September 23 2022 from https:\/\/support.xilinx.com\/s\/article\/76974?language=en_US."},{"key":"e_1_3_2_12_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2021.06.001"},{"key":"e_1_3_2_13_2","unstructured":"Md. Armanuzzaman and Ziming Zhao. 2022. BYOTee: Towards building your own trusted execution environments using FPGA. arXiv: 2203.04214 (2022). DOI:10.48550\/ARXIV.2203.04214"},{"issue":"2","key":"e_1_3_2_14_2","doi-asserted-by":"crossref","first-page":"370","DOI":"10.1109\/JPROC.2005.862424","article-title":"The Sorcerer\u2019s apprentice guide to fault attacks","volume":"94","author":"Bar-El H.","year":"2006","unstructured":"H. Bar-El, H. Choukri, D. Naccache, M. Tunstall, and C. Whelan. 2006. The Sorcerer\u2019s apprentice guide to fault attacks. Proceedings of the IEEE 94, 2 (2006), 370\u2013382.","journal-title":"Proceedings of the IEEE"},{"key":"e_1_3_2_15_2","doi-asserted-by":"crossref","unstructured":"Elaine Barker. 2020. Guideline for Using Cryptographic Standards in the Federal Government: Cryptographic Mechanisms. Retrieved January 30 2022 from 10.6028\/NIST.SP.800-175B","DOI":"10.6028\/NIST.SP.800-175Br1"},{"key":"e_1_3_2_16_2","volume-title":"Proceedings of the 11th European Conference on Computer Systems (EuroSys\u201916)","author":"Bartolini Davide B.","year":"2016","unstructured":"Davide B. Bartolini, Philipp Miedl, and Lothar Thiele. 2016. On the capacity of thermal covert channels in multicores. In Proceedings of the 11th European Conference on Computer Systems (EuroSys\u201916). ACM, New York, NY, Article 24, 16 pages . 10.1145\/2901318.2901322"},{"key":"e_1_3_2_17_2","doi-asserted-by":"crossref","first-page":"1954","DOI":"10.1109\/ISCAS.2013.6572251","volume-title":"Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS\u201913)","author":"Bayon Pierre","year":"2013","unstructured":"Pierre Bayon, Lilian Bossuet, Alain Aubert, and Viktor Fischer. 2013. Electromagnetic analysis on ring oscillator-based true random number generators. In Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS\u201913). 1954\u20131957. DOI:10.1109\/ISCAS.2013.6572251"},{"key":"e_1_3_2_18_2","doi-asserted-by":"crossref","first-page":"151","DOI":"10.1007\/978-3-642-29912-4_12","volume-title":"Constructive Side-Channel Analysis and Secure Design","author":"Bayon Pierre","year":"2012","unstructured":"Pierre Bayon, Lilian Bossuet, Alain Aubert, Viktor Fischer, Fran\u00e7ois Poucheret, Bruno Robisson, and Philippe Maurine. 2012. Contactless electromagnetic active attack on ring oscillator based true random number generator. In Constructive Side-Channel Analysis and Secure Design, Werner Schindler and Sorin A. Huss (Eds.). Springer, Berlin, Germany, 151\u2013166."},{"key":"e_1_3_2_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2019.2900235"},{"key":"e_1_3_2_20_2","doi-asserted-by":"crossref","first-page":"108","DOI":"10.1109\/SOCC.2017.8226018","volume-title":"Proceedings of the 2017 30th IEEE International System-on-Chip Conference (SOCC\u201917)","author":"Benhani El Mehdi","year":"2017","unstructured":"El Mehdi Benhani, Cedric Marchand, Alain Aubert, and Lilian Bossuet. 2017. On the security evaluation of the ARM TrustZone extension in a heterogeneous SoC. In Proceedings of the 2017 30th IEEE International System-on-Chip Conference (SOCC\u201917). 108\u2013113. DOI:10.1109\/SOCC.2017.8226018"},{"key":"e_1_3_2_21_2","first-page":"735","volume-title":"Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL\u201912)","author":"Benz F.","year":"2012","unstructured":"F. Benz, A. Seffrin, and S. A. Huss. 2012. Bil: A tool-chain for bitstream reverse-engineering. In Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL\u201912). 735\u2013738."},{"key":"e_1_3_2_22_2","unstructured":"D. Black. 2019. Xilinx Says Its New FPGA Is World\u2019s Largest. Retrieved January 30 2022 from https:\/\/www.enterpriseai.news\/2019\/08\/21\/xilinx-says-its-new-fpga-is-worlds-largest\/."},{"key":"e_1_3_2_23_2","doi-asserted-by":"publisher","DOI":"10.1007\/s41635-017-0020-3"},{"key":"e_1_3_2_24_2","doi-asserted-by":"crossref","first-page":"16","DOI":"10.1007\/978-3-540-28632-5_2","volume-title":"Cryptographic Hardware and Embedded Systems\u2014CHES 2004","author":"Brier Eric","year":"2004","unstructured":"Eric Brier, Christophe Clavier, and Francis Olivier. 2004. Correlation power analysis with a leakage model. In Cryptographic Hardware and Embedded Systems\u2014CHES 2004, Marc Joye and Jean-Jacques Quisquater (Eds.). Springer, Berlin, Germany, 16\u201329."},{"key":"e_1_3_2_25_2","doi-asserted-by":"publisher","DOI":"10.1007\/s00145-010-9083-9"},{"key":"e_1_3_2_26_2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2013.2247460"},{"key":"e_1_3_2_27_2","volume-title":"Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES","author":"Chari Suresh","year":"2002","unstructured":"Suresh Chari, Josyula R. Rao, and Pankaj Rohatgi. 2002. Template attacks. In Proceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES\u201902)."},{"key":"e_1_3_2_28_2","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3096664"},{"key":"e_1_3_2_29_2","first-page":"1","volume-title":"Proceedings of the 2020 IEEE International Conference on Electronics, Computing, and Communication Technologies (CONECCT\u201920)","author":"Chithra Chithra","year":"2020","unstructured":"Chithra Chithra, J. Kokila, and N. Ramasubramanian. 2020. Detection of hardware Trojans using machine learning in SoC FPGAs. In Proceedings of the 2020 IEEE International Conference on Electronics, Computing, and Communication Technologies (CONECCT\u201920). 1\u20137. DOI:10.1109\/CONECCT50063.2020.9198475"},{"key":"e_1_3_2_30_2","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2021.3077887"},{"key":"e_1_3_2_31_2","unstructured":"Clifford. 2021. Project IceStorm. Retrieved February 9 2021 from http:\/\/www.clifford.at\/icestorm."},{"key":"e_1_3_2_32_2","volume-title":"Proceedings of the 11th USENIX Workshop on Offensive Technologies (WOOT\u201917)","author":"Cui Ang","year":"2017","unstructured":"Ang Cui and Rick Housley. 2017. BADFET: Defeating modern secure boot using second-order pulsed electromagnetic fault injection. In Proceedings of the 11th USENIX Workshop on Offensive Technologies (WOOT\u201917). https:\/\/www.usenix.org\/conference\/woot17\/workshop-program\/presentation\/cui."},{"key":"e_1_3_2_33_2","doi-asserted-by":"publisher","DOI":"10.1007\/s41635-021-00122-4"},{"key":"e_1_3_2_34_2","doi-asserted-by":"crossref","first-page":"7","DOI":"10.1109\/FDTC.2012.15","volume-title":"Proceedings of the 2012 Workshop on Fault Diagnosis and Tolerance in Cryptography","author":"Dehbaoui Amine","year":"2012","unstructured":"Amine Dehbaoui, Jean-Max Dutertre, Bruno Robisson, and Assia Tria. 2012. Electromagnetic transient faults injection on a hardware and a software implementations of AES. In Proceedings of the 2012 Workshop on Fault Diagnosis and Tolerance in Cryptography. 7\u201315. DOI:10.1109\/FDTC.2012.15"},{"key":"e_1_3_2_35_2","doi-asserted-by":"crossref","first-page":"487","DOI":"10.1109\/EuroSP51992.2021.00040","volume-title":"Proceedings of the 2021 IEEE European Symposium on Security and Privacy (EuroS&P\u201921)","author":"Dessouky Ghada","year":"2021","unstructured":"Ghada Dessouky, Ahmad-Reza Sadeghi, and Shaza Zeitouni. 2021. SoK: Secure FPGA multi-tenancy in the cloud: Challenges and opportunities. In Proceedings of the 2021 IEEE European Symposium on Security and Privacy (EuroS&P\u201921). 487\u2013506. DOI:10.1109\/EuroSP51992.2021.00040"},{"key":"e_1_3_2_36_2","doi-asserted-by":"crossref","first-page":"274","DOI":"10.1109\/ISSCC.2011.5746316","volume-title":"Proceedings of the 2011 IEEE International Solid-State Circuits Conference","author":"Doulcier-Verdier Marion","year":"2011","unstructured":"Marion Doulcier-Verdier, Jean-Max Dutertre, Jacques Fournier, Jean-Baptiste Rigaud, Bruno Robisson, and Assia Tria. 2011. A side-channel and fault-attack resistant AES circuit working on duplicated complemented values. In Proceedings of the 2011 IEEE International Solid-State Circuits Conference. 274\u2013276. DOI:10.1109\/ISSCC.2011.5746316"},{"key":"e_1_3_2_37_2","first-page":"1","volume-title":"Proceedings of the 2015 10th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC\u201915)","author":"Druyer R.","year":"2015","unstructured":"R. Druyer, L. Torres, P. Benoit, P. V. Bonzom, and P. Le-Quere. 2015. A survey on security features in modern FPGAs. In Proceedings of the 2015 10th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC\u201915). IEEE, Los Alamitos, CA, 1\u20138. http:\/\/ieeexplore.ieee.org\/document\/7238102\/."},{"key":"e_1_3_2_38_2","doi-asserted-by":"crossref","first-page":"284","DOI":"10.1109\/ISVLSI51109.2021.00059","volume-title":"Proceedings of the 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI\u201921)","author":"Duan Shijin","year":"2021","unstructured":"Shijin Duan, Wenhao Wang, Yukui Luo, and Xiaolin Xu. 2021. A survey of recent attacks and mitigation on FPGA systems. In Proceedings of the 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI\u201921). 284\u2013289. DOI:10.1109\/ISVLSI51109.2021.00059"},{"key":"e_1_3_2_39_2","doi-asserted-by":"crossref","first-page":"197","DOI":"10.1109\/HOST45689.2020.9300276","volume-title":"Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST\u201920)","author":"Dubey Anuj","year":"2020","unstructured":"Anuj Dubey, Rosario Cammarota, and Aydin Aysu. 2020. MaskedNet: The first hardware inference engine aiming power side-channel protection. In Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST\u201920). 197\u2013208. DOI:10.1109\/HOST45689.2020.9300276"},{"key":"e_1_3_2_40_2","first-page":"1","volume-title":"Proceedings of the 2019 IEEE International Test Conference (ITC\u201919)","author":"Duncan Adam","year":"2019","unstructured":"Adam Duncan, Fahim Rahman, Andrew Lukefahr, Farimah Farahmandi, and Mark Tehranipoor. 2019. FPGA bitstream security: A day in the life. In Proceedings of the 2019 IEEE International Test Conference (ITC\u201919). 1\u201310. DOI:10.1109\/ITC44170.2019.9000145"},{"key":"e_1_3_2_41_2","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-46117-5_31"},{"key":"e_1_3_2_42_2","first-page":"1","volume-title":"Proceedings of the 2021 IEEE Physical Assurance and Inspection of Electronics (PAINE\u201921)","author":"Elnaggar Rana","year":"2021","unstructured":"Rana Elnaggar, Sayak Ray, Majid Sabbagh, Bilgiday Yuce, Terry Wang, and Jason Fung. 2021. OPAL: On-the-go physical attack lab to evaluate power side-channel vulnerabilities on FPGAs. In Proceedings of the 2021 IEEE Physical Assurance and Inspection of Electronics (PAINE\u201921). 1\u20138. DOI:10.1109\/PAINE54418.2021.9707701"},{"key":"e_1_3_2_43_2","volume-title":"Proceedings of the 29th USENIX Security Symposium (USENIX Security\u201920)","author":"Ender Maik","year":"2020","unstructured":"Maik Ender, Amir Moradi, and Christof Paar. 2020. The unpatchable silicon: A full break of the bitstream encryption of Xilinx 7-series FPGAs. In Proceedings of the 29th USENIX Security Symposium (USENIX Security\u201920)."},{"key":"e_1_3_2_44_2","unstructured":"FIRST. 2015. CVSS v3.1 Specification Document\u2014Revision 1. Retrieved September 23 2022 from https:\/\/www.first.org\/cvss\/v3-1\/cvss-v31-specification_r1.pdf."},{"key":"e_1_3_2_45_2","doi-asserted-by":"crossref","first-page":"426","DOI":"10.1007\/978-3-540-85053-3_27","volume-title":"Cryptographic Hardware and Embedded Systems\u2014CHES 2008","author":"Gierlichs Benedikt","year":"2008","unstructured":"Benedikt Gierlichs, Lejla Batina, Pim Tuyls, and Bart Preneel. 2008. Mutual information analysis. In Cryptographic Hardware and Embedded Systems\u2014CHES 2008, Elisabeth Oswald and Pankaj Rohatgi (Eds.). Springer, Berlin, Germany, 426\u2013442."},{"key":"e_1_3_2_46_2","doi-asserted-by":"crossref","first-page":"204","DOI":"10.1145\/3373087.3375318","volume-title":"Proceedings of the 2020 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA\u201920)","author":"Glamo\u010danin Ognjen","year":"2020","unstructured":"Ognjen Glamo\u010danin, Louis Coulon, Francesco Regazzoni, and Mirjana Stojilovi\u0107. 2020. Built-in self-evaluation of first-order power side-channel leakage for FPGAs. In Proceedings of the 2020 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA\u201920). ACM, New York, NY, 204\u2013210. 10.1145\/3373087.3375318"},{"key":"e_1_3_2_47_2","article-title":"Voltage-Based Covert Channels Using FPGAs","author":"Gnad Dennis R. E.","year":"2019","unstructured":"Dennis R. E. Gnad, Cong Dang Khoa Nguyen, Syed Hashim Gillani, and Mehdi B. Tahoori. 2019. Voltage-Based Covert Channels Using FPGAs. Cryptology ePrint Archive, Report 2019\/1394. https:\/\/ia.cr\/2019\/1394.","journal-title":"Cryptology ePrint Archive, Report 2019\/1394"},{"key":"e_1_3_2_48_2","first-page":"1","volume-title":"Proceedings of the 2017 27th International Conference on Field Programmable Logic and Applications (FPL\u201917)","author":"Gnad Dennis R. E.","year":"2017","unstructured":"Dennis R. E. Gnad, Fabian Oboril, and Mehdi B. Tahoori. 2017. Voltage drop-based fault attacks on FPGAs using valid bitstreams. In Proceedings of the 2017 27th International Conference on Field Programmable Logic and Applications (FPL\u201917). 1\u20137."},{"key":"e_1_3_2_49_2","doi-asserted-by":"crossref","first-page":"109","DOI":"10.1007\/978-3-030-42068-0_7","volume-title":"Smart Card Research and Advanced Applications","author":"Gravellier Joseph","year":"2020","unstructured":"Joseph Gravellier, Jean-Max Dutertre, Yannick Teglia, Philippe Loubet Moundi, and Francis Olivier. 2020. Remote side-channel attacks on heterogeneous SoC. In Smart Card Research and Advanced Applications, Sonia Bela\u00efd and Tim G\u00fcneysu (Eds.). Springer International Publishing, Cham, Switzerland, 109\u2013125."},{"key":"e_1_3_2_50_2","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-021-00273-8"},{"key":"e_1_3_2_51_2","doi-asserted-by":"crossref","unstructured":"Y. Hamadi and D. Merceron. 1997. Reconfigurable architectures: A new vision for optimization problems. In Principles and Practice of Constraint Programming-CP97 . Lecture Notes in Computer Science Vol. 1330. Springer 209\u2013221.","DOI":"10.1007\/BFb0017441"},{"key":"e_1_3_2_52_2","doi-asserted-by":"crossref","first-page":"27","DOI":"10.1007\/978-3-319-49445-6_2","volume-title":"Security, Privacy, and Applied Cryptography Engineering","author":"He Wei","year":"2016","unstructured":"Wei He, Jakub Breier, and Shivam Bhasin. 2016. Cheap and cheerful: A low-cost digital sensor for detecting laser fault injection attacks. In Security, Privacy, and Applied Cryptography Engineering, Claude Carlet, M. Anwar Hasan, and Vishal Saraswat (Eds.). Springer International Publishing, Cham, Switzerland, 27\u201346."},{"key":"e_1_3_2_53_2","doi-asserted-by":"crossref","first-page":"102","DOI":"10.1109\/FDTC.2016.13","volume-title":"Proceedings of the 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC\u201916)","author":"He Wei","year":"2016","unstructured":"Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, and Makoto Nagata. 2016. Ring oscillator under laser: Potential of PLL-based countermeasure against laser fault injection. In Proceedings of the 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC\u201916). 102\u2013113. DOI:10.1109\/FDTC.2016.13"},{"key":"e_1_3_2_54_2","first-page":"39","volume-title":"Proceedings of the 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC\u201917)","author":"He Wei","year":"2017","unstructured":"Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, and Makoto Nagata. 2017. An FPGA-compatible PLL-based sensor against fault injection attack. In Proceedings of the 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC\u201917). 39\u201340. DOI:10.1109\/ASPDAC.2017.7858291"},{"key":"e_1_3_2_55_2","doi-asserted-by":"publisher","DOI":"10.1145\/3361147"},{"key":"e_1_3_2_56_2","unstructured":"Karen Horovitz and Ryan Kenny. 2018. Intel FPGA Secure Device Manager. Retrieved January 30 2022 from https:\/\/apps.dtic.mil\/sti\/pdfs\/AD1052301.pdf."},{"key":"e_1_3_2_57_2","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2965016"},{"key":"e_1_3_2_58_2","first-page":"1","article-title":"Temperature-based covert channel in FPGA systems","author":"Iakymchuk T.","year":"2011","unstructured":"T. Iakymchuk, Maciej Nikodem, and Krzysztof Kepa. 2011. Temperature-based covert channel in FPGA systems. In Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC\u201911).1\u20137.","journal-title":"Proceedings of the 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC\u201911)."},{"key":"e_1_3_2_59_2","first-page":"1","article-title":"IEEE standard for test access port and boundary-scan architecture","year":"2013","unstructured":"IEEE. 2013. IEEE standard for test access port and boundary-scan architecture. IEEE Std 1149.1-2013 (Revision of IEEE Std 1149.1-2001) (2013), 1\u2013444.","journal-title":"IEEE Std 1149.1-2013 (Revision of IEEE Std 1149.1-2001)"},{"key":"e_1_3_2_60_2","unstructured":"Intel. 2020. Intel\u00ae Stratix\u00ae 10 FPGA for Intel\u00ae Quartus\u00ae Prime Pro Advisory. Retrieved January 30 2022 from https:\/\/www.intel.com\/content\/www\/us\/en\/security-center\/advisory\/intel-sa-00388.html."},{"key":"e_1_3_2_61_2","unstructured":"Intel. 2020. UG20132\u2014Intel Quartus Prime Pro Edition Design Compilation. Retrieved January 30 2022 from https:\/\/www.intel.la\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/ug\/ug-qpp-compiler.pdf."},{"key":"e_1_3_2_62_2","unstructured":"Intel. 2021. UG20101\u2014Intel Stratix 10 SoC FPGA Boot User Guide (v21.1). Retrieved June 22 2021 from https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/ug\/ug-s10-soc-boot.pdf."},{"key":"e_1_3_2_63_2","unstructured":"Intel. 2021. UGS10CONFIG\u2014Intel Stratix 10 Configuration User Guide (v21.1). Retrieved June 22 2021 from https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/hb\/stratix-10\/ug-s10-config.pdf."},{"key":"e_1_3_2_64_2","first-page":"1","volume-title":"Proceedings of the 2019 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS\u201919)","author":"Iyer Vishnuvardhan V.","year":"2019","unstructured":"Vishnuvardhan V. Iyer and Ali E. Yilmaz. 2019. An adaptive acquisition approach to localize electromagnetic information leakage from cryptographic modules. In Proceedings of the 2019 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS\u201919). 1\u20136. DOI:10.1109\/WMCaS.2019.8732510"},{"key":"e_1_3_2_65_2","doi-asserted-by":"crossref","unstructured":"Nisha Jacob Johann Heyszl Andreas Zankl Carsten Rolfes and Georg Sigl. 2017. How to break secure boot on FPGA SoCs through malicious hardware. In Cryptographic Hardware and Embedded Systems\u2014CHES 2017 . Lecture Notes in Computer Science Vol. 10529. Springer 425\u2013442.","DOI":"10.1007\/978-3-319-66787-4_21"},{"key":"e_1_3_2_66_2","first-page":"1","volume-title":"Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS\u201918)","author":"Jeong Minyoung","year":"2018","unstructured":"Minyoung Jeong, Jaeheum Lee, Eungu Jung, Young Hwan Kim, and Kyoungrok Cho. 2018. Extract LUT logics from a downloaded bitstream data in FPGA. In Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS\u201918). 1\u20135. DOI:10.1109\/ISCAS.2018.8350950"},{"key":"e_1_3_2_67_2","unstructured":"Chenglu Jin Vasudev Gohil Ramesh Karri and Jeyavijayan Rajendran. 2020. Security of cloud FPGAs: A survey. arXiv:2005.04867 (2020). DOI:10.48550\/ARXIV.2005.04867"},{"key":"e_1_3_2_68_2","unstructured":"Jens-Peter Kaps Kris Gaj Abubakr Abdulgadir and Kamyar Mohajerani. 2022. General Framework for Evaluating LWC Finalists in Terms of Resistance to Side-Channel Attacks . National Institute of Standards and Technology."},{"issue":"12","key":"e_1_3_2_69_2","doi-asserted-by":"crossref","first-page":"2295","DOI":"10.1109\/TVLSI.2012.2231707","article-title":"Hardware designer\u2019s guide to fault attacks","volume":"21","author":"Karaklaji\u0107 Du\u0161ko","year":"2013","unstructured":"Du\u0161ko Karaklaji\u0107, J\u00f6rn-Marc Schmidt, and Ingrid Verbauwhede. 2013. Hardware designer\u2019s guide to fault attacks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, 12 (2013), 2295\u20132306.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"e_1_3_2_70_2","unstructured":"Toshihiro Katashita Yohei Hori Hirofumi Sakane and Akashi Satoh. 2011. Side-Channel Attack Standard Evaluation Board SASEBO-W for Smartcard Testing . National Institute of Standards and Technology."},{"key":"e_1_3_2_71_2","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1109\/GCCE.2013.6664860","volume-title":"Proceedings of the 2013 IEEE 2nd Global Conference on Consumer Electronics (GCCE\u201913)","author":"Katashita Toshihiro","year":"2013","unstructured":"Toshihiro Katashita, Akihiko Sasaki, and Yohei Hori. 2013. A novel smart card development platform for evaluating physical attacks and PUFs. In Proceedings of the 2013 IEEE 2nd Global Conference on Consumer Electronics (GCCE\u201913). 37\u201339. DOI:10.1109\/GCCE.2013.6664860"},{"key":"e_1_3_2_72_2","first-page":"1","volume-title":"Proceedings of the 2021 IEEE Physical Assurance and Inspection of Electronics (PAINE\u201921)","author":"Kim Yongseen","year":"2021","unstructured":"Yongseen Kim, Eun-Gu Jung, and ChangKyun Kim. 2021. Bitstream reverse engineering of Microsemi\u2019s VersaTile-based FPGAs. In Proceedings of the 2021 IEEE Physical Assurance and Inspection of Electronics (PAINE\u201921). 1\u20138. DOI:10.1109\/PAINE54418.2021.9707700"},{"key":"e_1_3_2_73_2","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-011-0006-y"},{"key":"e_1_3_2_74_2","first-page":"104","volume-title":"Advances in Cryptology\u2014CRYPTO\u201996","author":"Kocher Paul C.","year":"1996","unstructured":"Paul C. Kocher. 1996. Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems. In Advances in Cryptology\u2014CRYPTO\u201996, Neal Koblitz (Ed.). Springer, Berlin, Germany, 104\u2013113."},{"key":"e_1_3_2_75_2","first-page":"388","volume-title":"Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology (CRYPTO\u201999)","author":"Kocher Paul C.","year":"1999","unstructured":"Paul C. Kocher, Joshua Jaffe, and Benjamin Jun. 1999. Differential power analysis. In Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology (CRYPTO\u201999). 388\u2013397."},{"key":"e_1_3_2_76_2","first-page":"171","volume-title":"Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS\u201912)","author":"Korczyc Jakub","year":"2012","unstructured":"Jakub Korczyc and Andrzej Krasniewski. 2012. Evaluation of susceptibility of FPGA-based circuits to fault injection attacks based on clock glitching. In Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS\u201912). 171\u2013174. DOI:10.1109\/DDECS.2012.6219047"},{"key":"e_1_3_2_77_2","doi-asserted-by":"publisher","DOI":"10.1007\/s41635-019-00083-9"},{"key":"e_1_3_2_78_2","first-page":"1","volume-title":"Proceedings of the 2019 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD\u201919)","author":"Krautter Jonas","year":"2019","unstructured":"Jonas Krautter, Dennis R. E. Gnad, Falk Schellenberg, Amir Moradi, and Mehdi B. Tahoori. 2019. Active fences against voltage-based side channels in multi-tenant FPGAs. In Proceedings of the 2019 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD\u201919). 1\u20138. DOI:10.1109\/ICCAD45719.2019.8942094"},{"issue":"3","key":"e_1_3_2_79_2","doi-asserted-by":"crossref","first-page":"44","DOI":"10.46586\/tches.v2018.i3.44-68","article-title":"FPGAhammer: Remote voltage fault attacks on shared FPGAs, suitable for DFA on AES","volume":"2018","author":"Krautter Jonas","year":"2018","unstructured":"Jonas Krautter, Dennis R. E. Gnad, and Mehdi B. Tahoori. 2018. FPGAhammer: Remote voltage fault attacks on shared FPGAs, suitable for DFA on AES. IACR Transactions on Cryptographic Hardware and Embedded Systems 2018, 3 (82018), 44\u201368. https:\/\/tches.iacr.org\/index.php\/TCHES\/article\/view\/7268.","journal-title":"IACR Transactions on Cryptographic Hardware and Embedded Systems"},{"key":"e_1_3_2_80_2","unstructured":"Lattice. 2020. Lattice Diamond 3.12 User Guide. Retrieved January 30 2022 from http:\/\/www.latticesemi.com\/view_document?document_id=53077."},{"key":"e_1_3_2_81_2","unstructured":"Lattice. 2020. TN02001\u2014iCE40 Programming and Configuration (v3.2). Retrieved January 30 2022 from http:\/\/www.latticesemi.com\/view_document?document_id=46502."},{"key":"e_1_3_2_82_2","first-page":"1","volume-title":"Proceedings of the 2011 International Conference on Field-Programmable Technology","author":"Masle Adrien Le","year":"2011","unstructured":"Adrien Le Masle, Gary C. T. Chow, and Wayne Luk. 2011. Constant power reconfigurable computing. In Proceedings of the 2011 International Conference on Field-Programmable Technology. 1\u20138. DOI:10.1109\/FPT.2011.6132682"},{"issue":"1","key":"e_1_3_2_83_2","doi-asserted-by":"crossref","first-page":"197","DOI":"10.1109\/92.920833","article-title":"A bitstream reconfigurable FPGA implementation of the WSAT algorithm","volume":"9","author":"Leong P. H. W.","year":"2001","unstructured":"P. H. W. Leong, C. W. Sham, W. C. Wong, H. Y. Wong, W. S. Yuen, and M. P. Leong. 2001. A bitstream reconfigurable FPGA implementation of the WSAT algorithm. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9, 1 (Feb.2001), 197\u2013201.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"e_1_3_2_84_2","first-page":"1","volume-title":"Proceedings of the 2020 57th ACM\/IEEE Design Automation Conference (DAC\u201920)","author":"Liu Wenye","year":"2020","unstructured":"Wenye Liu, Chip-Hong Chang, Fan Zhang, and Xiaoxuan Lou. 2020. Imperceptible misclassification attack on deep learning accelerator by glitch injection. In Proceedings of the 2020 57th ACM\/IEEE Design Automation Conference (DAC\u201920). 1\u20136. DOI:10.1109\/DAC18072.2020.9218577"},{"key":"e_1_3_2_85_2","doi-asserted-by":"crossref","first-page":"147","DOI":"10.1007\/978-3-662-53140-2_8","volume-title":"Cryptographic Hardware and Embedded Systems\u2014CHES 2016","author":"Lohrke Heiko","year":"2016","unstructured":"Heiko Lohrke, Shahin Tajik, Christian Boit, and Jean-Pierre Seifert. 2016. No place to hide: Contactless probing of secret data on FPGAs. In Cryptographic Hardware and Embedded Systems\u2014CHES 2016, Benedikt Gierlichs and Axel Y. Poschmann (Eds.). Springer, Berlin, Germany, 147\u2013167."},{"key":"e_1_3_2_86_2","doi-asserted-by":"publisher","DOI":"10.13154\/tches.v2018.i3.573-595"},{"key":"e_1_3_2_87_2","unstructured":"Ting Lu Ryna Kenny and Sean Atsatt. 2021. WP01252\u2014Secure Device Manager for Intel\u00ae Stratix\u00ae 10 Devices Provides FPGA and SoC Security. Retrieved January 30 2022 from https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/wp\/wp-01252-secure-device-manager-for-fpga-soc-security.pdf."},{"key":"e_1_3_2_88_2","doi-asserted-by":"publisher","DOI":"10.1145\/3491214"},{"key":"e_1_3_2_89_2","first-page":"295","volume-title":"Proceedings of the 2021 58th ACM\/IEEE Design Automation Conference (DAC\u201921)","author":"Luo Yukui","year":"2021","unstructured":"Yukui Luo, Cheng Gongye, Yunsi Fei, and Xiaolin Xu. 2021. DeepStrike: Remotely-guided fault injection attacks on DNN accelerator in cloud-FPGA. In Proceedings of the 2021 58th ACM\/IEEE Design Automation Conference (DAC\u201921). 295\u2013300. DOI:10.1109\/DAC18074.2021.9586262"},{"key":"e_1_3_2_90_2","first-page":"331","volume-title":"Proceedings of the 2019 International Conference on Field-Programmable Technology (ICFPT\u201919)","author":"Luo Yukui","year":"2019","unstructured":"Yukui Luo and Xiaolin Xu. 2019. HILL: A hardware isolation framework against information leakage on multi-tenant FPGA long-wires. In Proceedings of the 2019 International Conference on Field-Programmable Technology (ICFPT\u201919). 331\u2013334. DOI:10.1109\/ICFPT47387.2019.00060"},{"key":"e_1_3_2_91_2","doi-asserted-by":"crossref","first-page":"43","DOI":"10.1109\/FDTC.2018.00015","volume-title":"Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC\u201918)","author":"Madau Maxime","year":"2018","unstructured":"Maxime Madau, Michel Agoyan, Josep Balasch, Milo\u0161 Gruji\u0107, Patrick Haddad, Philippe Maurine, Vladimir Ro\u017ei\u0107, Dave Singel\u00e9e, Bohan Yang, and Ingrid Verbauwhede. 2018. The impact of pulsed electromagnetic fault injection on true random number generators. In Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC\u201918). 43\u201348. DOI:10.1109\/FDTC.2018.00015"},{"key":"e_1_3_2_92_2","doi-asserted-by":"crossref","first-page":"1745","DOI":"10.23919\/DATE.2019.8715263","volume-title":"Proceedings of the 2019 Design, Automation, and Test in Europe Conference and Exhibition (DATE\u201919)","author":"Mahmoud Dina","year":"2019","unstructured":"Dina Mahmoud and Mirjana Stojilovi\u0107. 2019. Timing violation induced faults in multi-tenant FPGAs. In Proceedings of the 2019 Design, Automation, and Test in Europe Conference and Exhibition (DATE\u201919). 1745\u20131750. DOI:10.23919\/DATE.2019.8715263"},{"key":"e_1_3_2_93_2","doi-asserted-by":"publisher","DOI":"10.1145\/3498337"},{"key":"e_1_3_2_94_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.149"},{"key":"e_1_3_2_95_2","volume-title":"Proceedings of the 16th International Conference on Availability, Reliability, and Security (ARES\u201921)","author":"Mart\u00ednez-Rodr\u00edguez Macarena C.","year":"2021","unstructured":"Macarena C. Mart\u00ednez-Rodr\u00edguez, Ignacio M. Delgado-Lozano, and Billy Bob Brumley. 2021. SoK: Remote power analysis. In Proceedings of the 16th International Conference on Availability, Reliability, and Security (ARES\u201921). ACM, New York, NY, Article 7, 12 pages. 10.1145\/3465481.3465773"},{"key":"e_1_3_2_96_2","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2014.2374072"},{"key":"e_1_3_2_97_2","volume-title":"Proceedings of the 24th USENIX Security Symposium (USENIX Security\u201915)","author":"Masti Ramya Jayaram","year":"2015","unstructured":"Ramya Jayaram Masti, Devendra Rai, Aanjhan Ranganathan, Christian M\u00fcller, Lothar Thiele, and Srdjan Capkun. 2015. Thermal covert channels on multi-core platforms. In Proceedings of the 24th USENIX Security Symposium (USENIX Security\u201915). https:\/\/www.usenix.org\/conference\/usenixsecurity15\/technical-sessions\/presentation\/masti."},{"key":"e_1_3_2_98_2","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1145\/3373087.3375390","volume-title":"Proceedings of the 2020 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA\u201920)","author":"Matas Kaspar","year":"2020","unstructured":"Kaspar Matas, Tuan La, Nikola Grunchevski, Khoa Pham, and Dirk Koch. 2020. Invited tutorial: FPGA hardware security for datacenters and beyond. In Proceedings of the 2020 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA\u201920). ACM, New York, NY, 11\u201320. 10.1145\/3373087.3375390"},{"key":"e_1_3_2_99_2","first-page":"1","volume-title":"Proceedings of the 2016 IEEE 5th Global Conference on Consumer Electronics","author":"Matsubayashi Masato","year":"2016","unstructured":"Masato Matsubayashi, Akashi Satoh, and Jun Ishii. 2016. Clock glitch generator on SAKURA-G for fault injection attack against a cryptographic circuit. In Proceedings of the 2016 IEEE 5th Global Conference on Consumer Electronics. 1\u20134. DOI:10.1109\/GCCE.2016.7800490"},{"key":"e_1_3_2_100_2","doi-asserted-by":"crossref","first-page":"346","DOI":"10.1007\/978-3-540-85053-3_22","volume-title":"Cryptographic Hardware and Embedded Systems\u2014CHES 2008","author":"Mentens Nele","year":"2008","unstructured":"Nele Mentens, Benedikt Gierlichs, and Ingrid Verbauwhede. 2008. Power and fault analysis resistance in hardware through dynamic reconfiguration. In Cryptographic Hardware and Embedded Systems\u2014CHES 2008, Elisabeth Oswald and Pankaj Rohatgi (Eds.). Springer, Berlin, Germany, 346\u2013362."},{"key":"e_1_3_2_101_2","unstructured":"Microsemi. 2019. Microchip\u2014FPGA and SoC Product Catalog. Retrieved January 30 2022 from https:\/\/www.microsemi.com\/document-portal\/doc_download\/1244242-fpga-soc-catalog."},{"key":"e_1_3_2_102_2","doi-asserted-by":"crossref","first-page":"288","DOI":"10.1109\/ICFPT51103.2020.00050","volume-title":"Proceedings of the 2020 International Conference on Field-Programmable Technology (ICFPT\u201920)","author":"Mirzargar Seyedeh Sharareh","year":"2020","unstructured":"Seyedeh Sharareh Mirzargar, Gai\u00ebtan Renault, Andrea Guerrieri, and Mirjana Stojilovi\u0107. 2020. Nonintrusive and adaptive monitoring for locating voltage attacks in virtualized FPGAs. In Proceedings of the 2020 International Conference on Field-Programmable Technology (ICFPT\u201920). 288\u2013289. DOI:10.1109\/ICFPT51103.2020.00050"},{"key":"e_1_3_2_103_2","doi-asserted-by":"crossref","first-page":"202","DOI":"10.1109\/FPL.2019.00039","volume-title":"Proceedings of the 2019 29th International Conference on Field Programmable Logic and Applications (FPL\u201919)","author":"Mirzargar Seyedeh Sharareh","year":"2019","unstructured":"Seyedeh Sharareh Mirzargar and Mirjana Stojilovi\u0107. 2019. Physical side-channel attacks and covert communication on FPGAs: A survey. In Proceedings of the 2019 29th International Conference on Field Programmable Logic and Applications (FPL\u201919). 202\u2013210. DOI:10.1109\/FPL.2019.00039"},{"key":"e_1_3_2_104_2","article-title":"CVE-2020-12312.","year":"2020","unstructured":"MITRE. 2020. CVE-2020-12312.Available from MITRE, CVE-ID CVE-2020-12312. Retrieved May 21, 2022 from https:\/\/cve.mitre.org\/cgi-bin\/cvename.cgi?name=CVE-2020-12312.","journal-title":"Available from MITRE, CVE-ID CVE-2020-12312"},{"key":"e_1_3_2_105_2","article-title":"CVE-2020-8737.","year":"2020","unstructured":"MITRE. 2020. CVE-2020-8737.Available from MITRE, CVE-ID CVE-2020-8737. Retrieved May 21, 2022 from https:\/\/cve.mitre.org\/cgi-bin\/cvename.cgi?name=CVE-2020-8737.","journal-title":"Available from MITRE, CVE-ID CVE-2020-8737"},{"key":"e_1_3_2_106_2","article-title":"CVE-2021-27208.","year":"2021","unstructured":"MITRE. 2021. CVE-2021-27208.Available from MITRE, CVE-ID CVE-2021-27208. Retrieved May 21, 2022 from https:\/\/cve.mitre.org\/cgi-bin\/cvename.cgi?name=CVE-2021-27208.","journal-title":"Available from MITRE, CVE-ID CVE-2021-27208"},{"key":"e_1_3_2_107_2","unstructured":"MITRE. 2022. CVE. Retrieved May 21 2022 from https:\/\/cve.mitre.org\/."},{"key":"e_1_3_2_108_2","article-title":"CVE-2021-44850.","year":"2022","unstructured":"MITRE. 2022. CVE-2021-44850.Available from MITRE, CVE-ID CVE-2021-44850. Retrieved May 21, 2022 from https:\/\/cve.mitre.org\/cgi-bin\/cvename.cgi?name=CVE-2021-44850.","journal-title":"Available from MITRE, CVE-ID CVE-2021-44850"},{"key":"e_1_3_2_109_2","article-title":"CVE-2022-23822.","year":"2022","unstructured":"MITRE. 2022. CVE-2022-23822.Available from MITRE, CVE-ID CVE-2022-23822. Retrieved May 21, 2022 from https:\/\/cve.mitre.org\/cgi-bin\/cvename.cgi?name=CVE-2022-23822.","journal-title":"Available from MITRE, CVE-ID CVE-2022-23822"},{"key":"e_1_3_2_110_2","first-page":"111","volume-title":"Proceedings of the 18th ACM Conference on Computer and Communications Security (CCS\u201911)","author":"Moradi Amir","year":"2011","unstructured":"Amir Moradi, Alessandro Barenghi, Timo Kasper, and Christof Paar. 2011. On the vulnerability of FPGA bitstream encryption against power analysis attacks: Extracting keys from Xilinx Virtex-II FPGAs. In Proceedings of the 18th ACM Conference on Computer and Communications Security (CCS\u201911). ACM, New York, NY, 111\u2013124. 10.1145\/2046707.2046722"},{"key":"e_1_3_2_111_2","doi-asserted-by":"crossref","unstructured":"Amir Moradi Markus Kasper and Christof Paar. 2012. Black-box side-channel attacks highlight the importance of countermeasures\u2014An analysis of the Xilinx Virtex-4 and Virtex-5 bitstream encryption mechanism. In Topics in Cryptology\u2014CT-RSA 2012 . Lecture Notes in Computer Science Vol. 7178. Springer 1\u201318.","DOI":"10.1007\/978-3-642-27954-6_1"},{"key":"e_1_3_2_112_2","doi-asserted-by":"crossref","first-page":"91","DOI":"10.1145\/2435264.2435282","volume-title":"Proceedings of the ACM\/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA\u201913)","author":"Moradi Amir","year":"2013","unstructured":"Amir Moradi, David Oswald, Christof Paar, and Pawel Swierczynski. 2013. Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: Facilitating black-box analysis using software reverse-engineering. In Proceedings of the ACM\/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA\u201913). ACM, New York, NY, 91\u2013100. 10.1145\/2435264.2435282"},{"key":"e_1_3_2_113_2","doi-asserted-by":"crossref","first-page":"71","DOI":"10.1007\/978-3-319-43283-0_5","volume-title":"Constructive Side-Channel Analysis and Secure Design","author":"Moradi Amir","year":"2016","unstructured":"Amir Moradi and Tobias Schneider. 2016. Improved side-channel analysis attacks on Xilinx bitstream encryption of 5, 6, and 7 series. In Constructive Side-Channel Analysis and Secure Design, Fran\u00e7ois-Xavier Standaert and Elisabeth Oswald (Eds.). Springer International Publishing, Cham, Switzerland, 71\u201387."},{"key":"e_1_3_2_114_2","volume-title":"Proceedings of the Conference on Hardware and Architectural Support for Security and Privacy (HASP\u201920)","author":"Moraitis Michail","year":"2020","unstructured":"Michail Moraitis and Elena Dubrova. 2020. FPGA bitstream modification with interconnect in mind. In Proceedings of the Conference on Hardware and Architectural Support for Security and Privacy (HASP\u201920). ACM, New York, NY, Article 5, 9 pages. 10.1145\/3458903.3458908"},{"key":"e_1_3_2_115_2","unstructured":"Michael Muckin and Scott Fitch. 2019. A Threat-Driven Approach to Cyber Security. Retrieved January 30 2022 from https:\/\/www.lockheedmartin.com\/content\/dam\/lockheed-martin\/rms\/documents\/cyber\/LM-White-Paper-Threat-Driven-Approach.pdf."},{"key":"e_1_3_2_116_2","first-page":"983","volume-title":"Proceedings of the 2021 6th International Conference on Communication and Electronics Systems (ICCES\u201921)","author":"Mukherjee Shyamapada","year":"2021","unstructured":"Shyamapada Mukherjee, Swapnanil kr Saikia, Stuti Anand, Ritu Chouhan, and Hiresh Das. 2021. A counter measure to prevent timing-based side-channel attack on FPGA. In Proceedings of the 2021 6th International Conference on Communication and Electronics Systems (ICCES\u201921). 983\u2013988. DOI:10.1109\/ICCES51350.2021.9489054"},{"issue":"4","key":"e_1_3_2_117_2","doi-asserted-by":"crossref","first-page":"49","DOI":"10.1109\/MM.2020.2998435","article-title":"SymbiFlow and VPR: An open-source design flow for commercial and novel FPGAs","volume":"40","author":"Murray Kevin E.","year":"2020","unstructured":"Kevin E. Murray, Mohamed A. Elgammal, Vaughn Betz, Tim Ansell, Keith Rothman, and Alessandro Comodi. 2020. SymbiFlow and VPR: An open-source design flow for commercial and novel FPGAs. IEEE Micro 40, 4 (2020), 49\u201357.","journal-title":"IEEE Micro"},{"key":"e_1_3_2_118_2","first-page":"640","volume-title":"Proceedings of the 2020 IEEE 38th International Conference on Computer Design (ICCD\u201920)","author":"Ngo Kalle","year":"2020","unstructured":"Kalle Ngo, Elena Dubrova, and Michail Moraitis. 2020. Attacking Trivium at the bitstream level. In Proceedings of the 2020 IEEE 38th International Conference on Computer Design (ICCD\u201920). 640\u2013647. DOI:10.1109\/ICCD50377.2020.00110"},{"key":"e_1_3_2_119_2","volume-title":"Voltage-Based Covert Channel Communication between Logically Separated IP Cores in FPGAs","author":"Nguyen Cong","year":"2018","unstructured":"Cong Nguyen. 2018. Voltage-Based Covert Channel Communication between Logically Separated IP Cores in FPGAs. Bachelor\u2019s Thesis. Karlsruhe Institute of Technology. https:\/\/cdnc.itec.kit.edu\/downloads\/Other\/online_thesis_final_Khoa_Nguyen.pdf."},{"key":"e_1_3_2_120_2","unstructured":"NIST. 2001. Announcing the Advanced Encryption Standard. Retrieved January 30 2022 from https:\/\/nvlpubs.nist.gov\/nistpubs\/FIPS\/NIST.FIPS.197.pdf."},{"key":"e_1_3_2_121_2","unstructured":"NIST. 2022. NVD. Retrieved January 30 2022 from https:\/\/nvd.nist.gov\/."},{"key":"e_1_3_2_122_2","doi-asserted-by":"crossref","first-page":"264","DOI":"10.1145\/1344671.1344729","volume-title":"Proceedings of the 16th International ACM\/SIGDA Symposium on Field Programmable Gate Arrays (FPGA\u201908)","author":"Note Jean-Baptiste","year":"2008","unstructured":"Jean-Baptiste Note and \u00c9ric Rannaud. 2008. From the bitstream to the netlist. In Proceedings of the 16th International ACM\/SIGDA Symposium on Field Programmable Gate Arrays (FPGA\u201908). ACM, New York, NY, 264. 10.1145\/1344671.1344729"},{"key":"e_1_3_2_123_2","volume-title":"Fault Injection Using Crowbars on Embedded SystemsCryptology ePrint Archive, Paper 2016\/810","author":"O\u2019Flynn Colin","year":"2016","unstructured":"Colin O\u2019Flynn. 2016. Fault Injection Using Crowbars on Embedded Systems. Cryptology ePrint Archive, Paper 2016\/810. https:\/\/eprint.iacr.org\/2016\/810."},{"key":"e_1_3_2_124_2","doi-asserted-by":"crossref","first-page":"243","DOI":"10.1007\/978-3-319-10175-0_17","volume-title":"Constructive Side-Channel Analysis and Secure Design","author":"O\u2019Flynn Colin","year":"2014","unstructured":"Colin O\u2019Flynn and Zhizhang (David) Chen. 2014. ChipWhisperer: An open-source platform for hardware embedded security research. In Constructive Side-Channel Analysis and Secure Design, Emmanuel Prouff (Ed.). Springer International Publishing, Cham, Switzerland, 243\u2013260."},{"key":"e_1_3_2_125_2","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-016-0128-3"},{"key":"e_1_3_2_126_2","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3173287"},{"key":"e_1_3_2_127_2","first-page":"1","volume-title":"Proceedings of the 2021 IEEE Physical Assurance and Inspection of Electronics (PAINE\u201921)","author":"Paquette Michael","year":"2021","unstructured":"Michael Paquette, Brian Marquis, Rachel Bainbridge, and Joe Chapman. 2021. Visualizing electromagnetic fault injection with timing sensors. In Proceedings of the 2021 IEEE Physical Assurance and Inspection of Electronics (PAINE\u201921). 1\u20138. DOI:10.1109\/PAINE54418.2021.9707696"},{"key":"e_1_3_2_128_2","unstructured":"Ed Parson. 2018. XAPP1098\u2014Developing Tamper-Resistant Designs with UltraScale and UltraScale+ FPGAs (v1.3). Retrieved January 30 2022 from https:\/\/www.xilinx.com\/support\/documentation\/application_notes\/xapp1098-tamper-resist-designs.pdf."},{"key":"e_1_3_2_129_2","unstructured":"Ed Peterson. 2015. WP468\u2014Leveraging Asymmetric Authentication to Enhance Security-Critical Applications Using Zynq-7000 All Programmable SoCs (v1.0). Retrieved January 30 2022 from https:\/\/www.xilinx.com\/support\/documentation\/white_papers\/wp468_asym-auth-zynq-7000.pdf."},{"key":"e_1_3_2_130_2","unstructured":"Ed Peterson. 2021. XAPP1175\u2014Secure Boot of Zynq-7000 SoC (v2.2). Retrieved January 30 2022 from https:\/\/www.xilinx.com\/support\/documentation\/application_notes\/xapp1175_zynq_secure_boot.pdf."},{"key":"e_1_3_2_131_2","unstructured":"PrjTrellis. 2021. Welcome to Project Trellis\u2014Project Trellis 0.0-672-gf93243b Documentation. Retrieved February 9 2021 from https:\/\/prjtrellis.readthedocs.io\/en\/latest."},{"key":"e_1_3_2_132_2","doi-asserted-by":"crossref","first-page":"194","DOI":"10.1109\/FPL.2019.00038","volume-title":"Proceedings of the 2019 29th International Conference on Field Programmable Logic and Applications (FPL\u201919)","author":"Provelengios George","year":"2019","unstructured":"George Provelengios, Daniel Holcomb, and Russell Tessier. 2019. Characterizing power distribution attacks in multi-user FPGA environments. In Proceedings of the 2019 29th International Conference on Field Programmable Logic and Applications (FPL\u201919). 194\u2013201. DOI:10.1109\/FPL.2019.00038"},{"issue":"1","key":"e_1_3_2_133_2","article-title":"Clock glitch fault injection attacks on an FPGA AES implementation","volume":"1","author":"Qiao Yifei","year":"2017","unstructured":"Yifei Qiao, Zhaojun Lu, Hailong Liu, and Zhenglin Liu. 2017. Clock glitch fault injection attacks on an FPGA AES implementation. Journal of Electrotechnology, Electrical Engineering and Management 1, 1 (March2017). http:\/\/clausiuspress.com\/article\/68.html.","journal-title":"Journal of Electrotechnology, Electrical Engineering and Management"},{"key":"e_1_3_2_134_2","first-page":"45","volume-title":"Proceedings of the 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201918)","author":"Ramesh Chethan","year":"2018","unstructured":"Chethan Ramesh, Shivukumar B. Patil, Siva Nishok Dhanuskodi, George Provelengios, Sebastien Pillement, Daniel Holcomb, and Russell Tessier. 2018. FPGA side channel attacks without physical access. In Proceedings of the 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201918). 45\u201352. DOI:10.1109\/FCCM.2018.00016"},{"key":"e_1_3_2_135_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.3013196"},{"issue":"2","key":"e_1_3_2_136_2","article-title":"Power side-channel attack analysis: A review of 20 years of study for the layman","volume":"4","author":"Randolph Mark","year":"2020","unstructured":"Mark Randolph and William Diehl. 2020. Power side-channel attack analysis: A review of 20 years of study for the layman. Cryptography 4, 2 (2020), 15 . https:\/\/www.mdpi.com\/2410-387X\/4\/2\/15.","journal-title":"Cryptography"},{"key":"e_1_3_2_137_2","doi-asserted-by":"crossref","first-page":"378","DOI":"10.1109\/iSES52644.2021.00093","volume-title":"Proceedings of the 2021 IEEE International Symposium on Smart Electronic Systems (iSES\u201921)","author":"Ren Wei","year":"2021","unstructured":"Wei Ren, Junhao Pan, and Deming Chen. 2021. AccGuard: Secure and trusted computation on remote FPGA accelerators. In Proceedings of the 2021 IEEE International Symposium on Smart Electronic Systems (iSES\u201921). IEEE, Los Alamitos, CA, 378\u2013383. 10.1109\/iSES52644.2021.00093"},{"key":"e_1_3_2_138_2","unstructured":"Galen Schretlen. \u2018Discovering and exploiting CVE-2021-27208 CVE-2021-44850\u2019. ROPchain 2022 https:\/\/blog.ropcha.in."},{"key":"e_1_3_2_139_2","first-page":"1","volume-title":"Proceedings of the 2021 IEEE Latin American Conference on Computational Intelligence (LA-CCI\u201921)","author":"Rosero-Montalvo Paul D.","year":"2021","unstructured":"Paul D. Rosero-Montalvo. 2021. A survey on security concerns and their actual solutions for using FPGAs in cloud computing. In Proceedings of the 2021 IEEE Latin American Conference on Computational Intelligence (LA-CCI\u201921). 1\u20136. DOI:10.1109\/LA-CCI48322.2021.9769794"},{"key":"e_1_3_2_140_2","doi-asserted-by":"crossref","first-page":"130","DOI":"10.1109\/HST.2015.7140251","volume-title":"Proceedings of the 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST\u201915)","author":"Sasdrich Pascal","year":"2015","unstructured":"Pascal Sasdrich, Amir Moradi, Oliver Mischke, and Tim G\u00fcneysu. 2015. Achieving side-channel protection with dynamic logic reconfiguration on modern FPGAs. In Proceedings of the 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST\u201915). 130\u2013136. DOI:10.1109\/HST.2015.7140251"},{"key":"e_1_3_2_141_2","doi-asserted-by":"crossref","first-page":"1111","DOI":"10.23919\/DATE.2018.8342177","volume-title":"Proceedings of the 2018 Design, Automation, and Test in Europe Conference and Exhibition (DATE\u201918)","author":"Schellenberg Falk","year":"2018","unstructured":"Falk Schellenberg, Dennis R. E. Gnad, Amir Moradi, and Mehdi B. Tahoori. 2018. An inside job: Remote power analysis attacks on FPGAs. In Proceedings of the 2018 Design, Automation, and Test in Europe Conference and Exhibition (DATE\u201918). 1111\u20131116. DOI:10.23919\/DATE.2018.8342177"},{"key":"e_1_3_2_142_2","doi-asserted-by":"crossref","first-page":"197","DOI":"10.1145\/3373087.3375319","volume-title":"Proceedings of the 2020 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA\u201920)","author":"Seifoori Zeinab","year":"2020","unstructured":"Zeinab Seifoori, Seyedeh Sharareh Mirzargar, and Mirjana Stojilovi\u0107. 2020. Closing leaks: Routing against crosstalk side-channel attacks. In Proceedings of the 2020 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA\u201920). ACM, New York, NY, 197\u2013203. 10.1145\/3373087.3375319"},{"key":"e_1_3_2_143_2","doi-asserted-by":"crossref","first-page":"193","DOI":"10.1007\/978-3-319-31271-2_12","volume-title":"Smart Card Research and Advanced Applications","author":"Selmke Bodo","year":"2016","unstructured":"Bodo Selmke, Stefan Brummer, Johann Heyszl, and Georg Sigl. 2016. Precise laser fault injections into 90 nm and 45 nm SRAM-cells. In Smart Card Research and Advanced Applications, Naofumi Homma and Marcel Medwed (Eds.). Springer International Publishing, Cham, Switzerland, 193\u2013205."},{"key":"e_1_3_2_144_2","doi-asserted-by":"crossref","first-page":"36","DOI":"10.1109\/FDTC.2016.16","volume-title":"Proceedings of the 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC\u201916)","author":"Selmke Bodo","year":"2016","unstructured":"Bodo Selmke, Johann Heyszl, and Georg Sigl. 2016. Attack on a DFA protected AES by simultaneous laser fault injections. In Proceedings of the 2016 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC\u201916). 36\u201346. DOI:10.1109\/FDTC.2016.16"},{"key":"e_1_3_2_145_2","first-page":"271","volume-title":"Proceedings of the 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201919)","author":"Shen Linda L.","year":"2019","unstructured":"Linda L. Shen, Ibrahim Ahmed, and Vaughn Betz. 2019. Fast voltage transients on FPGAs: Impact and mitigation strategies. In Proceedings of the 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201919). 271\u2013279. DOI:10.1109\/FCCM.2019.00044"},{"key":"e_1_3_2_146_2","volume-title":"Semi-Invasive Attacks\u2014A New Approach to Hardware Security Analysis","author":"Skorobogatov Sergei","year":"2005","unstructured":"Sergei Skorobogatov. 2005. Semi-Invasive Attacks\u2014A New Approach to Hardware Security Analysis. Technical Report UCAM-CL-TR-630. Computer Laboratory, University of Cambridge."},{"key":"e_1_3_2_147_2","doi-asserted-by":"crossref","first-page":"244","DOI":"10.1109\/DSD.2017.69","volume-title":"Proceedings of the 2017 Euromicro Conference on Digital System Design (DSD\u201917)","author":"Skorobogatov Sergei","year":"2017","unstructured":"Sergei Skorobogatov. 2017. How microprobing can attack encrypted memory. In Proceedings of the 2017 Euromicro Conference on Digital System Design (DSD\u201917). 244\u2013251."},{"key":"e_1_3_2_148_2","unstructured":"SOGIS. 2020. Application of Attack Potential to Smartcards and Similar Devices Version 3.1. Retrieved January 30 2022 from https:\/\/www.sogis.eu\/documents\/cc\/domains\/sc\/JIL-Application-of-Attack-Potential-to-Smartcards-v3-1.pdf."},{"key":"e_1_3_2_149_2","volume-title":"Reconfigurable Hardware OS Prototype\u2014Part FPGA","author":"Steinegger Simon","year":"2004","unstructured":"Simon Steinegger. 2004. Reconfigurable Hardware OS Prototype\u2014Part FPGA. Retrieved January 30, 2022 from https:\/\/pub.tik.ee.ethz.ch\/students\/2003-2004-Wi\/DA-2004-05.pdf."},{"key":"e_1_3_2_150_2","doi-asserted-by":"crossref","first-page":"278","DOI":"10.1109\/ISVLSI51109.2021.00058","volume-title":"Proceedings of the 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI\u201921)","author":"Sunkavilli Sandeep","year":"2021","unstructured":"Sandeep Sunkavilli, Zhiming Zhang, and Qiaoyan Yu. 2021. New security threats on FPGAs: From FPGA design tools perspective. In Proceedings of the 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI\u201921). 278\u2013283. DOI:10.1109\/ISVLSI51109.2021.00058"},{"key":"e_1_3_2_151_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2646367"},{"key":"e_1_3_2_152_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2399455"},{"key":"e_1_3_2_153_2","unstructured":"F4PGA. 2022. Project X-Ray. Retrieved October 10 2022 from https:\/\/f4pga.readthedocs.io\/projects\/prjxray\/en\/latest\/db_dev_process\/readme.html."},{"key":"e_1_3_2_154_2","unstructured":"F4PGA. 2022. FPGA Assembly (FASM). Retrieved October 10 2022 from https:\/\/fasm.readthedocs.io\/en\/latest\/."},{"key":"e_1_3_2_155_2","doi-asserted-by":"crossref","first-page":"84","DOI":"10.1109\/HST.2014.6855574","volume-title":"Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST\u201914)","author":"S\u00f6ll Oliver","year":"2014","unstructured":"Oliver S\u00f6ll, Thomas Korak, Michael Muehlberghuber, and Michael Hutter. 2014. EM-based detection of hardware trojans on FPGAs. In Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST\u201914). 84\u201387. DOI:10.1109\/HST.2014.6855574"},{"key":"e_1_3_2_156_2","first-page":"186","volume-title":"Proceedings of the 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS\u201917)","author":"Tajik Shahin","year":"2017","unstructured":"Shahin Tajik, Julian Fietkau, Heiko Lohrke, Jean-Pierre Seifert, and Christian Boit. 2017. PUFMon: Security monitoring of FPGAs using physically unclonable functions. In Proceedings of the 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS\u201917). 186\u2013191. DOI:10.1109\/IOLTS.2017.8046216"},{"key":"e_1_3_2_157_2","doi-asserted-by":"crossref","first-page":"85","DOI":"10.1109\/FDTC.2015.19","volume-title":"Proceedings of the 2015 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC\u201915)","author":"Tajik Shahin","year":"2015","unstructured":"Shahin Tajik, Heiko Lohrke, Fatemeh Ganji, Jean-Pierre Seifert, and Christian Boit. 2015. Laser fault attack on physically unclonable functions. In Proceedings of the 2015 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC\u201915). 85\u201396. DOI:10.1109\/FDTC.2015.19"},{"key":"e_1_3_2_158_2","doi-asserted-by":"crossref","first-page":"1661","DOI":"10.1145\/3133956.3134039","volume-title":"Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security (CCS\u201917)","author":"Tajik Shahin","year":"2017","unstructured":"Shahin Tajik, Heiko Lohrke, Jean-Pierre Seifert, and Christian Boit. 2017. On the power of optical contactless probing: Attacking bitstream encryption of FPGAs. In Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications Security (CCS\u201917). 1661\u20131674."},{"key":"e_1_3_2_159_2","volume-title":"Black Hat DC","author":"Tarnovsky Christopher","year":"2008","unstructured":"Christopher Tarnovsky. 2008. Security failures in secure devices. In Black Hat DC, Vol. 74. Black Hat."},{"key":"e_1_3_2_160_2","doi-asserted-by":"crossref","first-page":"298","DOI":"10.1145\/3289602.3293920","volume-title":"Proceedings of the 2019 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA\u201919)","author":"Tian Shanquan","year":"2019","unstructured":"Shanquan Tian and Jakub Szefer. 2019. Temporal thermal covert channels in cloud FPGAs. In Proceedings of the 2019 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA\u201919). ACM, New York, NY, 298\u2013303. 10.1145\/3289602.3293920"},{"key":"e_1_3_2_161_2","first-page":"1","volume-title":"Proceedings of the 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC\u201917)","author":"Timmers Niek","year":"2017","unstructured":"Niek Timmers and Cristofaro Mune. 2017. Escalating privileges in Linux using voltage fault injection. In Proceedings of the 2017 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC\u201917). 1\u20138. DOI:10.1109\/FDTC.2017.16"},{"key":"e_1_3_2_162_2","unstructured":"Niek Timmers and Albert Spruyt. 2016. Bypassing Secure Boot Using Fault Injection. Retrieved September 23 2022 from https:\/\/www.riscure.com\/publication\/bypassing-secure-boot-using-fault-injection."},{"key":"e_1_3_2_163_2","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1109\/IVSW.2017.8031556","volume-title":"Proceedings of the 2017 IEEE 2nd International Verification and Security Workshop (IVSW\u201917)","author":"Trimberger Steve","year":"2017","unstructured":"Steve Trimberger and Steve McNeil. 2017. Security of FPGAs in data centers. In Proceedings of the 2017 IEEE 2nd International Verification and Security Workshop (IVSW\u201917). 117\u2013122. DOI:10.1109\/IVSW.2017.8031556"},{"key":"e_1_3_2_164_2","doi-asserted-by":"publisher","DOI":"10.1145\/3419100"},{"key":"e_1_3_2_165_2","first-page":"147","volume-title":"Proceedings of the 2020 IEEE International Symposium on Smart Electronic Systems (iSES\u201920).","author":"Wang Huanyu","year":"2020","unstructured":"Huanyu Wang and Elena Dubrova. 2020. Tandem deep learning side-channel attack against FPGA implementation of AES. In Proceedings of the 2020 IEEE International Symposium on Smart Electronic Systems (iSES\u201920).147\u2013150. DOI:10.1109\/iSES50453.2020.00041"},{"issue":"5","key":"e_1_3_2_166_2","doi-asserted-by":"crossref","first-page":"63","DOI":"10.1109\/MDAT.2017.2729398","article-title":"Probing attacks on integrated circuits: Challenges and research opportunities","volume":"34","author":"Wang Huanyu","year":"2017","unstructured":"Huanyu Wang, Domenic Forte, Mark M. Tehranipoor, and Qihang Shi. 2017. Probing attacks on integrated circuits: Challenges and research opportunities. IEEE Design & Test 34, 5 (2017), 63\u201371.","journal-title":"IEEE Design & Test"},{"key":"e_1_3_2_167_2","first-page":"393","volume-title":"Proceedings of the 34th Annual Computer Security Applications Conference (ACSAC\u201918)","author":"Wei Lingxiao","year":"2018","unstructured":"Lingxiao Wei, Bo Luo, Yu Li, Yannan Liu, and Qiang Xu. 2018. I know what you see: Power side-channel attack on convolutional neural network accelerators. In Proceedings of the 34th Annual Computer Security Applications Conference (ACSAC\u201918). ACM, New York, NY, 393\u2013406. 10.1145\/3274694.3274696"},{"key":"e_1_3_2_168_2","doi-asserted-by":"crossref","first-page":"301","DOI":"10.1109\/DAC18074.2021.9586207","volume-title":"Proceedings of the 2021 58th ACM\/IEEE Design Automation Conference (DAC\u201921)","author":"Xia Ke","year":"2021","unstructured":"Ke Xia, Yukui Luo, Xiaolin Xu, and Sheng Wei. 2021. SGX-FPGA: Trusted execution environment for CPU-FPGA heterogeneous architecture. In Proceedings of the 2021 58th ACM\/IEEE Design Automation Conference (DAC\u201921). IEEE, Los Alamitos, CA, 301\u2013306. 10.1109\/DAC18074.2021.9586207"},{"key":"e_1_3_2_169_2","first-page":"87","volume-title":"Proceedings of the 2020 International Conference on Computer Communication and Network Security (CCNS\u201920)","author":"Yang Peng","year":"2020","unstructured":"Peng Yang, Fang Luo, Qingyu Ou, and Dawei Zhou. 2020. Design and analysis of clock fault injection for AES. In Proceedings of the 2020 International Conference on Computer Communication and Network Security (CCNS\u201920). 87\u201391. DOI:10.1109\/CCNS50731.2020.00027"},{"key":"e_1_3_2_170_2","first-page":"68","volume-title":"Proceedings of the 2018 IEEE 27th Asian Test Symposium (ATS\u201918)","author":"Ye Jing","year":"2018","unstructured":"Jing Ye, Yu Hu, and Xiaowei Li. 2018. Hardware Trojan in FPGA CNN accelerator. In Proceedings of the 2018 IEEE 27th Asian Test Symposium (ATS\u201918). 68\u201373. DOI:10.1109\/ATS.2018.00024"},{"key":"e_1_3_2_171_2","first-page":"209","volume-title":"Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST\u201920)","author":"Yu Honggang","year":"2020","unstructured":"Honggang Yu, Haocheng Ma, Kaichen Yang, Yiqiang Zhao, and Yier Jin. 2020. DeepEM: Deep neural networks model recovery through EM side-channel information leakage. In Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST\u201920). 209\u2013218. DOI:10.1109\/HOST45689.2020.9300274"},{"key":"e_1_3_2_172_2","unstructured":"Yang Yu. 2020. Why deep learning makes it difficult to keep secrets in FPGAs. In Proceedings of the 2020 Workshop in Dynamic and Novel Advances in Machine Learning and Intelligent Cyber Security (DYNAMICS\u201920) ."},{"key":"e_1_3_2_173_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3066338"},{"key":"e_1_3_2_174_2","doi-asserted-by":"crossref","unstructured":"Wong Hiu Yung Yuen Wing Seung Kin Hong Lee and Philip Heng Wai Leong. 1999. A runtime reconfigurable implementation of the GSAT algorithm. In Field Programmable Logic and Applications . Lecture Notes in Computer Science Vol. 1673. Springer 526\u2013531.","DOI":"10.1007\/978-3-540-48302-1_64"},{"key":"e_1_3_2_175_2","doi-asserted-by":"publisher","DOI":"10.1145\/3340557"},{"key":"e_1_3_2_176_2","doi-asserted-by":"crossref","first-page":"38379","DOI":"10.1109\/ACCESS.2019.2901949","article-title":"A comprehensive FPGA reverse engineering tool-chain: From bitstream to RTL code","volume":"7","author":"Zhang Tao","year":"2019","unstructured":"Tao Zhang, Jian Wang, Shize Guo, and Zhe Chen. 2019. A comprehensive FPGA reverse engineering tool-chain: From bitstream to RTL code. IEEE Access 7 (2019), 38379\u201338389. https:\/\/ieeexplore.ieee.org\/document\/8653869\/.","journal-title":"IEEE Access"},{"key":"e_1_3_2_177_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2879878"},{"key":"e_1_3_2_178_2","doi-asserted-by":"crossref","first-page":"229","DOI":"10.1109\/SP.2018.00049","volume-title":"Proceedings of the 2018 IEEE Symposium on Security and Privacy (SP\u201918)","author":"Zhao Mark","year":"2018","unstructured":"Mark Zhao and G. Edward Suh. 2018. FPGA-based remote power side-channel attacks. In Proceedings of the 2018 IEEE Symposium on Security and Privacy (SP\u201918). 229\u2013244. DOI:10.1109\/SP.2018.00049"},{"key":"e_1_3_2_179_2","volume-title":"Proceedings of the 56th Annual Design Automation Conference (DAC\u201919)","author":"Zhao Pu","year":"2019","unstructured":"Pu Zhao, Siyue Wang, Cheng Gongye, Yanzhi Wang, Yunsi Fei, and Xue Lin. 2019. Fault sneaking attack: A stealthy framework for misleading deep neural networks. In Proceedings of the 56th Annual Design Automation Conference (DAC\u201919). ACM, New York, NY, Article 165, 6 pages. 10.1145\/3316781.3317825"},{"key":"e_1_3_2_180_2","first-page":"1","volume-title":"Proceedings of the 2006 International Conference on Field Programmable Logic and Applications.","author":"Ziener Daniel","year":"2006","unstructured":"Daniel Ziener, Stefan Assmus, and Juurgen Teich. 2006. Identifying FPGA IP-cores based on lookup table content analysis. In Proceedings of the 2006 International Conference on Field Programmable Logic and Applications.1\u20136."},{"key":"e_1_3_2_181_2","first-page":"1","volume-title":"Proceedings of the 2014 Design, Automation, and Test in Europe Conference and Exhibition (DATE\u201914)","author":"Zussa Loic","year":"2014","unstructured":"Loic Zussa, Amine Dehbaoui, Karim Tobich, Jean-Max Dutertre, Philippe Maurine, Ludovic Guillaume-Sage, Jessy Clediere, and Assia Tria. 2014. Efficiency of a glitch detector against electromagnetic fault injection. In Proceedings of the 2014 Design, Automation, and Test in Europe Conference and Exhibition (DATE\u201914). 1\u20136. DOI:10.7873\/DATE.2014.216"},{"key":"e_1_3_2_182_2","article-title":"Investigation of timing constraints violation as a fault injection means","author":"Zussa Lo\u00efc","year":"2012","unstructured":"Lo\u00efc Zussa, Jean-Max Dutertre, Jessy Cl\u00e9di\u00e8re, Bruno Robisson, and Assia Tria. 2012. Investigation of timing constraints violation as a fault injection means. In Proceedings of the 27th Conference on Design of Circuits and Integrated Systems (DCIS\u201912).https:\/\/hal-emse.ccsd.cnrs.fr\/emse-00742652.","journal-title":"Proceedings of the 27th Conference on Design of Circuits and Integrated Systems (DCIS\u201912)."},{"key":"e_1_3_2_183_2","doi-asserted-by":"crossref","first-page":"110","DOI":"10.1109\/IOLTS.2013.6604060","volume-title":"Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS\u201913)","author":"Zussa Lo\u00efc","year":"2013","unstructured":"Lo\u00efc Zussa, Jean-Max Dutertre, Jessy Cl\u00e9di\u00e8re, and Assia Tria. 2013. Power supply glitch induced faults on FPGA: An in-depth analysis of the injection mechanism. In Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS\u201913). 110\u2013115. DOI:10.1109\/IOLTS.2013.6604060"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3561515","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3561515","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T19:00:35Z","timestamp":1750186835000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3561515"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,3,11]]},"references-count":182,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2023,6,30]]}},"alternative-id":["10.1145\/3561515"],"URL":"https:\/\/doi.org\/10.1145\/3561515","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"value":"1936-7406","type":"print"},{"value":"1936-7414","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,3,11]]},"assertion":[{"value":"2022-02-13","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-08-14","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-03-11","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}