{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,20]],"date-time":"2025-12-20T22:06:28Z","timestamp":1766268388434,"version":"3.41.0"},"reference-count":38,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2022,12,9]],"date-time":"2022-12-09T00:00:00Z","timestamp":1670544000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"CONACYT","award":["420129\/264560"],"award-info":[{"award-number":["420129\/264560"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2023,1,31]]},"abstract":"<jats:p>This article proposes an electrical analysis of a new defect mechanism, to be named as b-open defect, which may occur in nanometer technologies due to the use of the Self-Aligned Double Patterning (SADP) technique. In metal lines making use of the SADP technique, a single dust particle may cause the simultaneous occurrence of a bridge defect and an open defect. When the two defects impact the same gates, the electrical effects of the bridge and the open combine and exhibit a new specific electrical behavior; we call this new defect behavior a b-open. As a consequence, existing test generation methodologies may miss defect detection. The electrical behavior of the b-open defect is first analyzed graphically and then validated through extensive SPICE simulations. The test pattern conditions to detect the b-open defect are finally determined, and it is shown that the b-open defect requires specific test generation.<\/jats:p>","DOI":"10.1145\/3564244","type":"journal-article","created":{"date-parts":[[2022,9,16]],"date-time":"2022-09-16T09:28:10Z","timestamp":1663320490000},"page":"1-19","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["B-open Defect: A Novel Defect Model in FinFET Technology"],"prefix":"10.1145","volume":"19","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9939-0974","authenticated-orcid":false,"given":"Freddy","family":"Forero","sequence":"first","affiliation":[{"name":"National Institute for Astrophysics, Optics and Electronics (INAOE), Tonantzintla, Puebla, Mexico"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4440-3800","authenticated-orcid":false,"given":"Victor","family":"Champac","sequence":"additional","affiliation":[{"name":"National Institute for Astrophysics, Optics and Electronics (INAOE), Tonantzintla, Puebla, Mexico"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3896-8231","authenticated-orcid":false,"given":"Michel","family":"Renovell","sequence":"additional","affiliation":[{"name":"Laboratory of Informatics, Robotics and Microelectronics of Montpellier(LIRMM), Montpellier, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2022,12,9]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2005.881001"},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2011.2169807"},{"key":"e_1_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2012.6401565"},{"key":"e_1_3_1_5_2","first-page":"181","volume-title":"IEEE 24th Asian Test Symposium (ATS\u201915)","author":"Chiang Kuan-Ying","year":"2015","unstructured":"Kuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, Cheng-Sheng Pan, and James Chien-Mo Li. 2015. Fault simulation and test pattern generation for cross-gate defects in FinFET circuits. In IEEE 24th Asian Test Symposium (ATS\u201915). IEEE, 181\u2013186."},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-017-5674-9"},{"key":"e_1_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2017.7928960"},{"key":"e_1_3_1_8_2","first-page":"1","volume-title":"IEEE 32nd VLSI Test Symposium (VTS\u201914)","author":"Harutyunyan Gurgen","year":"2014","unstructured":"Gurgen Harutyunyan, G. Tshagharyan, V. Vardanian, and Yervant Zorian. 2014. Fault modeling and test algorithm creation strategy for FinFET-based memories. In IEEE 32nd VLSI Test Symposium (VTS\u201914). IEEE, 1\u20136."},{"key":"e_1_3_1_9_2","first-page":"1","volume-title":"IEEE East-West Design & Test Symposium (EWDTS\u201915)","author":"Tshagharyan G.","year":"2015","unstructured":"G. Tshagharyan, G. Harutyunyan, S. Shoukourian, and Y. Zorian. 2015. Overview study on fault modeling and test methodology development for FinFET-based memories. In IEEE East-West Design & Test Symposium (EWDTS\u201915). IEEE, 1\u20134."},{"key":"e_1_3_1_10_2","first-page":"1","volume-title":"East-West Design & Test Symposium (EWDTS)","author":"Harutyunyan G.","year":"2014","unstructured":"G. Harutyunyan, S. Shoukourian, V. Vardanian, and Y. Zorian. 2014. Extending fault periodicity table for testing faults in memories under 20nm. In East-West Design & Test Symposium (EWDTS). IEEE, 1\u20134."},{"key":"e_1_3_1_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2397934"},{"key":"e_1_3_1_12_2","doi-asserted-by":"publisher","DOI":"10.1117\/12.879500"},{"key":"e_1_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2622625"},{"key":"e_1_3_1_14_2","doi-asserted-by":"crossref","first-page":"72740G","DOI":"10.1117\/12.814435","volume-title":"Optical Microlithography XXII","author":"Bencher Christopher","year":"2009","unstructured":"Christopher Bencher, Huixiong Dai, and Yongmei Chen. 2009. Gridded design rule scaling: Taking the CPU toward the 16nm node. In Optical Microlithography XXII, Vol. 7274. International Society for Optics and Photonics, 72740G."},{"key":"e_1_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.1145\/37888.37914"},{"key":"e_1_3_1_16_2","first-page":"83241X","volume-title":"Metrology, Inspection, and Process Control for Microlithography XXVI","year":"2012","unstructured":"Gurminder Singh, Kfir Dotan, Saar Shabtay, Man-Ping Cai, Noam Shachar, Chris Ngai, Chris Bencher, Liyan Miao, and Yongmei Chen. 2012. Small particle defect characterization on critical layers of 22nm Spacer Self-Aligned Double Patterning (SADP). In Metrology, Inspection, and Process Control for Microlithography XXVI, Vol. 8324. International Society for Optics and Photonics, 83241X."},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1994.292283"},{"key":"e_1_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805784"},{"key":"e_1_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/43.177407"},{"key":"e_1_3_1_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2397934"},{"key":"e_1_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1994.527999"},{"key":"e_1_3_1_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843859"},{"key":"e_1_3_1_23_2","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.77"},{"key":"e_1_3_1_24_2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2014.7046976"},{"key":"e_1_3_1_25_2","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2015.7313862"},{"key":"e_1_3_1_26_2","unstructured":"BSIM-CMG Model. 2018 [Online]. Retrieved from http:\/\/bsim.berkeley.edu\/models\/bsimcmg."},{"key":"e_1_3_1_27_2","unstructured":"Predictive Technology Model (PTM) 2018 [Online]. Available: http:\/\/ptm.asu.edu\/."},{"key":"e_1_3_1_28_2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1991.164111"},{"key":"e_1_3_1_29_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2323216"},{"key":"e_1_3_1_30_2","first-page":"1","volume-title":"International Test Conference","author":"Cho Kyoung Youn","year":"2005","unstructured":"Kyoung Youn Cho, S. Mitra, and E. J. McCluskey. 2005. Gate exhaustive testing. In International Test Conference. IEEE, 1\u20137."},{"key":"e_1_3_1_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805784"},{"key":"e_1_3_1_32_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.871626"},{"key":"e_1_3_1_33_2","first-page":"181","volume-title":"IEEE VLSI Test Symposium","author":"Spinner Stefan","year":"2008","unstructured":"Stefan Spinner, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, and Wu-Tung Cheng. 2008. Automatic test pattern generation for interconnect open defects. In IEEE VLSI Test Symposium. IEEE, 181\u2013186."},{"key":"e_1_3_1_34_2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271073"},{"key":"e_1_3_1_35_2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355762"},{"key":"e_1_3_1_36_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3071940"},{"key":"e_1_3_1_37_2","doi-asserted-by":"publisher","DOI":"10.1007\/BF00135337"},{"key":"e_1_3_1_38_2","first-page":"2D.1.1\u20132D.1.4","volume-title":"IEEE International Reliability Physics Symposium (IRPS\u201913)","year":"2013","unstructured":"Kyong Taek Lee, Wonchang Kang, Eun-Ae Chung, Gunrae Kim, Hyewon Shim, Hyunwoo Lee, Hyejin Kim, Minhyeok Choe, Nae-In Lee, Anuj Patel, Junekyun Park, and Jongwoo Park. 2013. Technology scaling on high- & metal-gate FinFET BTI reliability. In IEEE International Reliability Physics Symposium (IRPS\u201913). IEEE, 2D.1.1\u20132D.1.4."},{"key":"e_1_3_1_39_2","first-page":"1","volume-title":"IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems","author":"Gupta V.","year":"2018","unstructured":"V. Gupta, S. Khandelwal, J. Mathew, and M. Ottavi. 2018. 45nm bit-interleaving differential 10T low leakage FinFET based SRAM with column-wise write access control. In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. IEEE, 1\u20136."}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3564244","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3564244","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T01:10:33Z","timestamp":1750295433000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3564244"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,12,9]]},"references-count":38,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2023,1,31]]}},"alternative-id":["10.1145\/3564244"],"URL":"https:\/\/doi.org\/10.1145\/3564244","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"type":"print","value":"1550-4832"},{"type":"electronic","value":"1550-4840"}],"subject":[],"published":{"date-parts":[[2022,12,9]]},"assertion":[{"value":"2021-06-08","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-08-28","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-12-09","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}