{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,12]],"date-time":"2026-03-12T01:13:41Z","timestamp":1773278021947,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":18,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,1,16]],"date-time":"2023-01-16T00:00:00Z","timestamp":1673827200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"National Science Foundation of China","award":["Grant 92164301 and Grant 62204003"],"award-info":[{"award-number":["Grant 92164301 and Grant 62204003"]}]},{"name":"Zhejiang Provincial Key R&D program","award":["Grant 2021C01035"],"award-info":[{"award-number":["Grant 2021C01035"]}]},{"name":"The 111 Project","award":["Grant B18001"],"award-info":[{"award-number":["Grant B18001"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,1,16]]},"DOI":"10.1145\/3566097.3567860","type":"proceedings-article","created":{"date-parts":[[2023,1,31]],"date-time":"2023-01-31T18:40:49Z","timestamp":1675190449000},"page":"228-233","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["RIMAC"],"prefix":"10.1145","author":[{"given":"Peiyu","family":"Chen","sequence":"first","affiliation":[{"name":"Peking University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Meng","family":"Wu","sequence":"additional","affiliation":[{"name":"Peking University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yufei","family":"Ma","sequence":"additional","affiliation":[{"name":"Peking University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Le","family":"Ye","sequence":"additional","affiliation":[{"name":"Peking University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ru","family":"Huang","sequence":"additional","affiliation":[{"name":"Peking University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,1,31]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"CVPR","year":"2016","unstructured":"Kaiming He et al. Deep residual learning for image recognition. In CVPR, 2016."},{"key":"e_1_3_2_1_2_1","volume-title":"ICLR","year":"2015","unstructured":"Karen Simonyan et al. Very deep convolutional networks for large-scale image recognition. In ICLR, 2015."},{"key":"e_1_3_2_1_3_1","volume-title":"ISCA","author":"Chi P.","year":"2016","unstructured":"P. Chi et al. PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory. In ISCA, 2016."},{"key":"e_1_3_2_1_4_1","volume-title":"ISCA","author":"Shafiee A.","year":"2016","unstructured":"A. Shafiee et al. Isaac: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars. In ISCA, 2016."},{"key":"e_1_3_2_1_5_1","volume-title":"DAC","year":"2021","unstructured":"HanCheon Yun et al. Optimizing adc utilization through value-aware bypass in reram-based dnn accelerator. In DAC, 2021."},{"key":"e_1_3_2_1_6_1","volume-title":"DAC","year":"2020","unstructured":"Qilin Zheng et al. Lattice: An adc\/dac-less reram-based processing-in-memory architecture for accelerating deep convolution neural networks. In DAC, 2020."},{"key":"e_1_3_2_1_7_1","unstructured":"Zongwei Wang et al. Modulation of nonlinear resistive switching behavior of a taox-based resistive device through interface engineering. Nanotechnology."},{"key":"e_1_3_2_1_8_1","volume-title":"VLSI","author":"Tang K.","year":"2019","unstructured":"K. Tang et al. Considerations of integrating computing-in-memory and processing-in-sensor into convolutional neural network accelerators for low-power edge devices. In VLSI, 2019."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744870"},{"key":"e_1_3_2_1_10_1","volume-title":"VLSI","author":"Su F.","year":"2017","unstructured":"F. Su et al. A 462gops\/j rram-based nonvolatile intelligent processor for energy harvesting ioe system featuring nonvolatile logics and processing-in-memory. In VLSI, 2017."},{"key":"e_1_3_2_1_11_1","volume-title":"ISSCC","year":"2020","unstructured":"Qi Liu et al. 33.2 a fully integrated analog reram based 78.4tops\/w compute-in-memory chip with fully parallel mac computing. In ISSCC, 2020."},{"key":"e_1_3_2_1_12_1","volume-title":"ISSCC","author":"Bang S.","year":"2017","unstructured":"S. Bang et al. 14.7 a 288&mu;w programmable deep-learning processor with 270kb on-chip weight storage using non-uniform memory hierarchy for mobile intelligence. In ISSCC, 2017."},{"key":"e_1_3_2_1_13_1","volume-title":"VLSI","author":"Mochida R.","year":"2018","unstructured":"R. Mochida et al. A 4m synapses integrated analog reram based 66.5 tops\/w neural-network processor with cell current controlled writing and flexible network architecture. In VLSI, 2018."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2958568"},{"key":"e_1_3_2_1_15_1","volume-title":"Nature Communications","year":"2017","unstructured":"Peng Yao et al. Face classification using electronics synapses. Nature Communications, 2017."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2279571"},{"key":"e_1_3_2_1_17_1","volume-title":"JSSC","author":"Lin C.","year":"2009","unstructured":"C. Lin et al. A 12 bit 2.9 gs\/s dac with im3 &lt; -60 dbc beyond 1 ghz in 65 nm cmos. JSSC, 2009."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2010973"}],"event":{"name":"ASPDAC '23: 28th Asia and South Pacific Design Automation Conference","location":"Tokyo Japan","acronym":"ASPDAC '23","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEICE","IEEE CAS","IPSJ"]},"container-title":["Proceedings of the 28th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3566097.3567860","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3566097.3567860","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,7]],"date-time":"2026-01-07T17:33:39Z","timestamp":1767807219000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3566097.3567860"}},"subtitle":["An Array-Level ADC\/DAC-Free ReRAM-Based in-Memory DNN Processor with Analog Cache and Computation"],"short-title":[],"issued":{"date-parts":[[2023,1,16]]},"references-count":18,"alternative-id":["10.1145\/3566097.3567860","10.1145\/3566097"],"URL":"https:\/\/doi.org\/10.1145\/3566097.3567860","relation":{},"subject":[],"published":{"date-parts":[[2023,1,16]]},"assertion":[{"value":"2023-01-31","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}