{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,7]],"date-time":"2026-01-07T18:47:08Z","timestamp":1767811628533,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":25,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,1,16]],"date-time":"2023-01-16T00:00:00Z","timestamp":1673827200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,1,16]]},"DOI":"10.1145\/3566097.3567890","type":"proceedings-article","created":{"date-parts":[[2023,1,31]],"date-time":"2023-01-31T18:40:49Z","timestamp":1675190449000},"page":"146-151","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["Approximate Logic Synthesis by Genetic Algorithm with an Error Rate Guarantee"],"prefix":"10.1145","author":[{"given":"Chun-Ting","family":"Lee","sequence":"first","affiliation":[{"name":"National Tsing Hua University, Hsinchu, Taiwan, R.O.C."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yi-Ting","family":"Li","sequence":"additional","affiliation":[{"name":"National Tsing Hua University, Hsinchu, Taiwan, R.O.C."}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yung-Chih","family":"Chen","sequence":"additional","affiliation":[{"name":"National Taiwan University of Science and Technology, Taipei, Taiwan, R.O.C"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chun-Yao","family":"Wang","sequence":"additional","affiliation":[{"name":"National Tsing Hua University, Hsinchu, Taiwan, R.O.C."}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,1,31]]},"reference":[{"key":"e_1_3_2_1_1_1","author":"Barbareschi M.","year":"2022","unstructured":"M. Barbareschi et al., \"A Catalog-based AIG-Rewriting Approach to the Design of Approximate Components,\" IEEE Trans. Emerg. Topics Comput., 2022.","journal-title":"Trans. Emerg. Topics Comput."},{"key":"e_1_3_2_1_2_1","first-page":"1","volume-title":"Proc. DAC","author":"Echavarria J.","year":"2020","unstructured":"J. Echavarria et al., \"Probabilistic Error Propagation through Approximated Boolean Networks,\" Proc. DAC, 2020, pp. 1--6."},{"key":"e_1_3_2_1_3_1","first-page":"175","volume-title":"Proc. DAC","author":"Fiduccia C. M.","year":"1982","unstructured":"C. M. Fiduccia et al., \"A Linear-Time Heuristic for Improving Network Partitions,\" Proc. DAC, 1982, pp. 175--181."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2013.6569370"},{"key":"e_1_3_2_1_5_1","volume-title":"An Introductory Analysis with Applications to Biology, Control, and Artificial Intelligence,\" MIT Press","author":"Holland J. H.","year":"1992","unstructured":"J. H. Holland, \"Adaptation in Natural and Artificial Systems: An Introductory Analysis with Applications to Biology, Control, and Artificial Intelligence,\" MIT Press, 1992."},{"key":"e_1_3_2_1_6_1","volume-title":"Optimization of Combinational Logic Circuits with Genetic Programming,\" Elektronika ir Elektrotechnika","author":"Karakatic S.","year":"2013","unstructured":"S. Karakatic et al., \"Optimization of Combinational Logic Circuits with Genetic Programming,\" Elektronika ir Elektrotechnika, 2013."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1970.tb01770.x"},{"key":"e_1_3_2_1_8_1","first-page":"130","volume-title":"Proc. ICCAD","author":"Kim Y.","year":"2013","unstructured":"Y. Kim et al., \"An Energy Efficient Approximate Adder with Carry Skip for Error Resilient Neuromorphic VLSI Systems,\" Proc. ICCAD, 2013, pp. 130--137."},{"key":"e_1_3_2_1_9_1","first-page":"346","volume-title":"VLSID","author":"Kulkarni P.","year":"2011","unstructured":"P. Kulkarni et al., \"Trading Accuracy for Power with an Underdesigned Multiplier Architecture,\" Proc. VLSID, 2011, pp. 346--351."},{"key":"e_1_3_2_1_10_1","first-page":"1","volume-title":"Proc. EDSSC","author":"Kyaw K. Y.","year":"2010","unstructured":"K. Y. Kyaw et al., \"Low-Power High-Speed Multiplier for Error-Tolerant Application,\" Proc. EDSSC, 2010, pp. 1--4."},{"key":"e_1_3_2_1_11_1","first-page":"773","author":"Lai Y.-A","year":"2018","unstructured":"Y.-A Lai et al., \"Efficient Synthesis of Approximate Threshold Logic Circuits with an Error Rate Guarantee,\" Proc. DATE, 2018, pp. 773--778.","journal-title":"Proc. DATE"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2012.146"},{"key":"e_1_3_2_1_13_1","first-page":"1","volume-title":"Proc. DATE","author":"Liu C.","year":"2014","unstructured":"C. Liu et al., \"A Low-Power, High-Performance Approximate Multiplier with Configurable Partial Error Recovery,\" Proc. DATE, 2014, pp. 1--4."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218627"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1963.263531"},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317878"},{"key":"e_1_3_2_1_17_1","first-page":"1","volume-title":"Proc. DAC","author":"Su S.","year":"2018","unstructured":"S. Su et al., \"Efficient Batch Statistical Error Estimation for Iterative Multi-level Approximate Logic Synthesis,\" Proc. DAC, 2018, pp. 1--6."},{"key":"e_1_3_2_1_18_1","first-page":"266","author":"Tam K. S.","year":"2021","unstructured":"K. S. Tam et al., \"An Efficient Approximate Node Merging with an Error Rate Guarantee,\" Proc. ASP-DAC, 2021, pp. 266--271.","journal-title":"Proc. ASP-DAC"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEVC.2014.2336175"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.280"},{"key":"e_1_3_2_1_21_1","first-page":"1372","volume-title":"Proc. DATE","author":"Wendler A.","year":"2020","unstructured":"A. Wendler et al., \"A fast BDD Minimization Framework for Approximate Computing,\" Proc. DATE, 2020, pp. 1372--1377."},{"key":"e_1_3_2_1_22_1","unstructured":"S. Yang \"Logic Synthesis and Optimization Benchmarks \" Microelectronics Center of North Carolina Tech. Rep. 1991."},{"key":"e_1_3_2_1_23_1","first-page":"69","volume-title":"Proc. ISIC","author":"Zhu N.","year":"2009","unstructured":"N. Zhu et al., \"An Enhanced Low-Power High-Speed Adder for Error-Tolerant Application,\" Proc. ISIC, 2009, pp. 69--72."},{"key":"e_1_3_2_1_24_1","unstructured":"Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification [Online]. Available: http:\/\/www.eecs.berkeley.edu\/~alanmi\/abc"},{"key":"e_1_3_2_1_25_1","unstructured":"http:\/\/iwls.org\/iwls2005\/benchmarks.html"}],"event":{"name":"ASPDAC '23: 28th Asia and South Pacific Design Automation Conference","location":"Tokyo Japan","acronym":"ASPDAC '23","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEICE","IEEE CAS","IPSJ"]},"container-title":["Proceedings of the 28th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3566097.3567890","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3566097.3567890","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,7]],"date-time":"2026-01-07T17:36:49Z","timestamp":1767807409000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3566097.3567890"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,1,16]]},"references-count":25,"alternative-id":["10.1145\/3566097.3567890","10.1145\/3566097"],"URL":"https:\/\/doi.org\/10.1145\/3566097.3567890","relation":{},"subject":[],"published":{"date-parts":[[2023,1,16]]},"assertion":[{"value":"2023-01-31","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}