{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,16]],"date-time":"2026-05-16T00:03:11Z","timestamp":1778889791470,"version":"3.51.4"},"publisher-location":"New York, NY, USA","reference-count":19,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,1,16]],"date-time":"2023-01-16T00:00:00Z","timestamp":1673827200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,1,16]]},"DOI":"10.1145\/3566097.3567898","type":"proceedings-article","created":{"date-parts":[[2023,1,31]],"date-time":"2023-01-31T18:40:49Z","timestamp":1675190449000},"page":"529-534","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["A Robust FPGA Router with Concurrent Intra-CLB Rerouting"],"prefix":"10.1145","author":[{"given":"Jiarui","family":"Wang","sequence":"first","affiliation":[{"name":"Peking University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jing","family":"Mai","sequence":"additional","affiliation":[{"name":"Peking University, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhixiong","family":"Di","sequence":"additional","affiliation":[{"name":"Southwest Jiaotong University, Chengdu, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yibo","family":"Lin","sequence":"additional","affiliation":[{"name":"Peking University, Bejing, China and Beijing Advanced Innovation Center for Integrated Circuits, Beijing, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,1,31]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Ultrascale architecture clocking resources. [Online]. Available: https:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug572-ultrascale-clocking.pdf"},{"key":"e_1_3_2_1_2_1","unstructured":"Ultrascale architecture clb slices. [Online]. Available: https:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug574-ultrascale-clb.pdf"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/2629579"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1995.242049"},{"key":"e_1_3_2_1_5_1","first-page":"215","volume-title":"Physical Design Workshop","author":"Lemieux G. G.","year":"1993","unstructured":"G. G. Lemieux and S. D. Brown, \"detailed routing algorithm for allocating wire segments in field-programmable gate arrays,\" in Proc. Physical Design Workshop, 1993, pp. 215--226."},{"key":"e_1_3_2_1_6_1","first-page":"338","volume-title":"Air: A fast but lazy timing-driven fpga router,\" in 2020 25th Asia and South Pacific Design Automation Conference (ASPDAC)","author":"Murray K. E.","year":"2020","unstructured":"K. E. Murray, S. Zhong, and V. Betz, \"Air: A fast but lazy timing-driven fpga router,\" in 2020 25th Asia and South Pacific Design Automation Conference (ASPDAC), 2020, pp. 338--344."},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2768416"},{"key":"e_1_3_2_1_8_1","first-page":"53","volume-title":"Croute: A fast high-quality timing-driven connection-based fpga router,\" in 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","author":"Vercruyce D.","year":"2019","unstructured":"D. Vercruyce, E. Vansteenkiste, and D. Stroobandt, \"Croute: A fast high-quality timing-driven connection-based fpga router,\" in 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2019, pp. 53--60."},{"key":"e_1_3_2_1_9_1","first-page":"577","volume-title":"Fine-grained parallel routing for fpgas with selective expansion,\" in 2018 IEEE 36th International Conference on Computer Design (ICCD)","author":"Shen M.","year":"2018","unstructured":"M. Shen and N. Xiao, \"Fine-grained parallel routing for fpgas with selective expansion,\" in 2018 IEEE 36th International Conference on Computer Design (ICCD), 2018, pp. 577--586."},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"crossref","unstructured":"M. Shen \"Load balance-aware multi-core parallel routing for large-scale fpgas \" in 2018 IEEE 36th International Conference on Computer Design (ICCD) 2018 pp. 595--602.","DOI":"10.1109\/ICCD.2018.00095"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174246"},{"key":"e_1_3_2_1_12_1","volume-title":"Accelerating fpga routing through algorithmic enhancements and connection-aware parallelization,\" ACM transactions on reconfigurable technology and systems","author":"Zhou Y.","unstructured":"Y. Zhou, D. Vercruyce, and D. Stroobandt, \"Accelerating fpga routing through algorithmic enhancements and connection-aware parallelization,\" ACM transactions on reconfigurable technology and systems, vol. 13, no. 4, pp. 1--26, 2020."},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3031259"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/3388617"},{"key":"e_1_3_2_1_15_1","first-page":"943","volume-title":"Formulating data-arrival synchronizers in integer linear programming for cgra mapping,\" in 2021 58th ACM\/IEEE Design Automation Conference (DAC)","author":"Guo Y.","year":"2021","unstructured":"Y. Guo, J. Wang, J. Zhang, and G. Luo, \"Formulating data-arrival synchronizers in integer linear programming for cgra mapping,\" in 2021 58th ACM\/IEEE Design Automation Conference (DAC), 2021, pp. 943--948."},{"key":"e_1_3_2_1_16_1","unstructured":"Gurobi Optimization Inc. \"Gurobi optimizer reference manual \" http:\/\/www.gurobi.com 2022."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2021.3104255"},{"key":"e_1_3_2_1_18_1","first-page":"139","volume-title":"Routability-driven FPGA placement contest,\" in ACM International Symposium on Physical Design (ISPD)","author":"Yang S.","year":"2016","unstructured":"S. Yang, A. Gayasen, C. Mulpuri, S. Reddy, and R. Aggarwal, \"Routability-driven FPGA placement contest,\" in ACM International Symposium on Physical Design (ISPD), 2016, pp. 139--143."},{"key":"e_1_3_2_1_19_1","article-title":"\"elfplace: Electrostatics-based placement for large-scale heterogeneous fpgas","author":"Meng Y.","year":"2021","unstructured":"Y. Meng, W. Li, Y. Lin, and D. Z. Pan, \"elfplace: Electrostatics-based placement for large-scale heterogeneous fpgas,\" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2021.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)"}],"event":{"name":"ASPDAC '23: 28th Asia and South Pacific Design Automation Conference","location":"Tokyo Japan","acronym":"ASPDAC '23","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEICE","IEEE CAS","IPSJ"]},"container-title":["Proceedings of the 28th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3566097.3567898","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3566097.3567898","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,7]],"date-time":"2026-01-07T17:36:26Z","timestamp":1767807386000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3566097.3567898"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,1,16]]},"references-count":19,"alternative-id":["10.1145\/3566097.3567898","10.1145\/3566097"],"URL":"https:\/\/doi.org\/10.1145\/3566097.3567898","relation":{},"subject":[],"published":{"date-parts":[[2023,1,16]]},"assertion":[{"value":"2023-01-31","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}