{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,14]],"date-time":"2026-04-14T00:40:08Z","timestamp":1776127208562,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":20,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,1,16]],"date-time":"2023-01-16T00:00:00Z","timestamp":1673827200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,1,16]]},"DOI":"10.1145\/3566097.3567911","type":"proceedings-article","created":{"date-parts":[[2023,1,31]],"date-time":"2023-01-31T18:40:49Z","timestamp":1675190449000},"page":"7-12","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["Chiplet Placement for 2.5D IC with Sequence Pair Based Tree and Thermal Consideration"],"prefix":"10.1145","author":[{"given":"Hong-Wen","family":"Chiou","sequence":"first","affiliation":[{"name":"National Yang Ming Chiao Tung University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jia-Hao","family":"Jiang","sequence":"additional","affiliation":[{"name":"National Yang Ming Chiao Tung University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu-Teng","family":"Chang","sequence":"additional","affiliation":[{"name":"National Yang Ming Chiao Tung University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu-Min","family":"Lee","sequence":"additional","affiliation":[{"name":"National Yang Ming Chiao Tung University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chi-Wen","family":"Pan","sequence":"additional","affiliation":[{"name":"National Yang Ming Chiao Tung University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,1,31]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"System on integrated chips (SoIC) for 3D heterogeneous integration,\" in IEEE ECTC","author":"Chen M.-F.","year":"2019","unstructured":"M.-F. Chen, F.-C. Chen, W.-C. Chiou, and C. Doug, \"System on integrated chips (SoIC) for 3D heterogeneous integration,\" in IEEE ECTC, 2019."},{"key":"e_1_3_2_1_2_1","unstructured":"2D vs. 2.5D vs. 3D ICs https:\/\/www.eetimes.com\/2d-vs-2-5d-vs-3d-ics-101\/."},{"key":"e_1_3_2_1_3_1","volume-title":"2.2 AMD chiplet architecture for high-performance server and desktop products,\" in IEEE ISSCC","author":"Naffziger S.","year":"2020","unstructured":"S. Naffziger, K. Lepak, M. Paraschou, and M. Subramony, \"2.2 AMD chiplet architecture for high-performance server and desktop products,\" in IEEE ISSCC, 2020."},{"key":"e_1_3_2_1_4_1","volume-title":"A 7nm 4GHz Arm\u00ae-core-based CoWoS\u00ae chiplet design for high performance computing,\" in Symposium on VLSI Circuits","author":"Lin M.-S.","year":"2019","unstructured":"M.-S. Lin, T.-C. Huang, C.-C. Tsai, K.-H. Tam, C.-H. Hsieh, T. Chen, W.-H. Huang, J. Hu, Y.-C. Chen, S. K. Goel, C.-M. Fu, S. Rusu, C.-C. Li, S.-Y. Yang, M. Wong, S.-C. Yang, and F. Lee, \"A 7nm 4GHz Arm\u00ae-core-based CoWoS\u00ae chiplet design for high performance computing,\" in Symposium on VLSI Circuits, 2019."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2012.6248841"},{"key":"e_1_3_2_1_6_1","volume-title":"DAC","author":"Ho Y.-K.","year":"2013","unstructured":"Y.-K. Ho and Y. W. Chang, \"Multiple chip planning for chip-interposer codesign,\" in Proc. DAC, 2013."},{"key":"e_1_3_2_1_7_1","volume-title":"DAC","author":"Liu W. H.","year":"2014","unstructured":"W. H. Liu, M. S. Chang, and T. C. Wang, \"Floorplanning and signal assignment for silicon interposer-based 3D ICs,\" in Proc. DAC, 2014."},{"key":"e_1_3_2_1_8_1","volume-title":"ASP-DAC","author":"Osmolovskyi S.","year":"2018","unstructured":"S. Osmolovskyi, J. Knechtel, I. L. Markov, and J. Lienig, \"Optimal die placement for interposer-based 3D ICs,\" in Proc. ASP-DAC, 2018."},{"issue":"12","key":"e_1_3_2_1_9_1","first-page":"5183","article-title":"Cross-layer co-optimization of network design and chiplet placement in 2.5-D systems","volume":"39","author":"Coskun A.","year":"2020","unstructured":"A. Coskun, F. Eris, A. Joshi, A. B. Kahng, Y. Ma, A. Narayan, and V. Srinivas, \"Cross-layer co-optimization of network design and chiplet placement in 2.5-D systems,\" IEEE TCAD, vol. 39, no. 12, pp. 5183--5196, 2020.","journal-title":"IEEE TCAD"},{"key":"e_1_3_2_1_10_1","volume-title":"DATE","author":"Ma Y.","year":"2021","unstructured":"Y. Ma, L. Delshadtehrani, C. Demirkiran, J. L. Abellan, and A. Joshi, \"TAP-2.5D: A thermally-aware chiplet placement methodology for 2.5D systems,\" in Proc. DATE, 2021."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/43.552084"},{"key":"e_1_3_2_1_12_1","volume-title":"Parallel programming in OpenMP. Morgan kaufmann","author":"Chandra R.","year":"2001","unstructured":"R. Chandra, L. Dagum, D. Kohr, R. Menon, D. Maydan, and J. McDonald, Parallel programming in OpenMP. Morgan kaufmann, 2001."},{"key":"e_1_3_2_1_13_1","volume-title":"Fundamentals of heat and mass transfer","author":"Bergman T. L.","year":"2011","unstructured":"T. L. Bergman, T. L. Bergman, F. P. Incropera, D. P. Dewitt, and A. S. Lavine, Fundamentals of heat and mass transfer. John Wiley & Sons, 2011."},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.5555\/352229"},{"issue":"6","key":"e_1_3_2_1_15_1","first-page":"1404","article-title":"Fast thermal aware placement with accurate thermal analysis based on green function","volume":"22","author":"Liu S. S.-Y.","year":"2013","unstructured":"S. S.-Y. Liu, R.-G. Luo, S. Aroonsantidecha, C.-Y. Chin, and H.-M. Chen, \"Fast thermal aware placement with accurate thermal analysis based on green function,\" IEEE TVLSI, vol. 22, no. 6, pp. 1404--1415, 2013.","journal-title":"IEEE TVLSI"},{"key":"e_1_3_2_1_16_1","unstructured":"SuperLU 5.3.0 https:\/\/portal.nersc.gov\/project\/sparse\/superlu\/."},{"key":"e_1_3_2_1_17_1","unstructured":"ANSYS Icepak https:\/\/www.ansys.com\/products\/electronics\/ansys-icepak."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"crossref","unstructured":"S. Osmolovskyi and Jens Lienig \"Placement framework for interposer-based 3D ICs \" 2017 https:\/\/www.ifte.de\/english\/research\/interposer-design\/index.html.","DOI":"10.1109\/ASPDAC.2018.8297375"},{"key":"e_1_3_2_1_19_1","unstructured":"MCNC benchmark https:\/\/s2.smu.edu\/~manikas\/Benchmarks\/MCNC_Benchmark_Netlists.html."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382591"}],"event":{"name":"ASPDAC '23: 28th Asia and South Pacific Design Automation Conference","location":"Tokyo Japan","acronym":"ASPDAC '23","sponsor":["SIGDA ACM Special Interest Group on Design Automation","IEEE CEDA","IEICE","IEEE CAS","IPSJ"]},"container-title":["Proceedings of the 28th Asia and South Pacific Design Automation Conference"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3566097.3567911","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3566097.3567911","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,7]],"date-time":"2026-01-07T17:34:51Z","timestamp":1767807291000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3566097.3567911"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,1,16]]},"references-count":20,"alternative-id":["10.1145\/3566097.3567911","10.1145\/3566097"],"URL":"https:\/\/doi.org\/10.1145\/3566097.3567911","relation":{},"subject":[],"published":{"date-parts":[[2023,1,16]]},"assertion":[{"value":"2023-01-31","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}