{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T17:12:52Z","timestamp":1774631572127,"version":"3.50.1"},"reference-count":23,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2023,6,22]],"date-time":"2023-06-22T00:00:00Z","timestamp":1687392000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2023,9,30]]},"abstract":"<jats:p>The spectral correlation density (SCD) is an important tool in cyclostationary signal detection and classification. Even using efficient techniques based on the fast Fourier transform (FFT), real-time implementations are challenging because of the high computational complexity. A key dimension for computational optimization lies in minimizing the wordlength employed. In this article, we analyze the relationship between wordlength and signal-to-quantization noise in fixed-point implementations of the SCD function. A canonical SCD estimation algorithm, the FFT accumulation method (FAM) using fixed-point arithmetic, is studied. We derive closed-form expressions for SQNR and compare them at wordlengths ranging from 14 to 26 bits. The differences between the calculated SQNR and bit-exact simulations are less than 1\u00a0dB. Furthermore, an HLS-based FPGA design is implemented on a Xilinx Zynq UltraScale+ XCZU28DR-2FFVG1517E RFSoC. Using less than 25% of the logic fabric on the device, it consumes 7.7\u00a0W total on-chip power and has a power efficiency of 12.4\u00a0GOPS\/W, which is an order of magnitude improvement over an Nvidia Tesla K40 graphics processing unit (GPU) implementation. In terms of throughput, it achieves 50\u00a0MS\/sec, which is a speedup of 1.6 over a recent optimized FPGA implementation.<\/jats:p>","DOI":"10.1145\/3567429","type":"journal-article","created":{"date-parts":[[2022,10,10]],"date-time":"2022-10-10T12:04:14Z","timestamp":1665403454000},"page":"1-28","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["Fixed-point FPGA Implementation of the FFT Accumulation Method for Real-time Cyclostationary Analysis"],"prefix":"10.1145","volume":"16","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7638-6323","authenticated-orcid":false,"given":"Carol Jingyi","family":"Li","sequence":"first","affiliation":[{"name":"The University of Sydney, Faculty of Engineering, School of Electrical and Information Engineering, Australia"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1963-6354","authenticated-orcid":false,"given":"Xiangwei","family":"Li","sequence":"additional","affiliation":[{"name":"Nanyang Technological University, School of Computer Science and Engineering, Singapore"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4662-1892","authenticated-orcid":false,"given":"Binglei","family":"Lou","sequence":"additional","affiliation":[{"name":"The University of Sydney, Faculty of Engineering, School of Electrical and Information Engineering, Australia"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4636-753X","authenticated-orcid":false,"given":"Craig T.","family":"Jin","sequence":"additional","affiliation":[{"name":"The University of Sydney, Faculty of Engineering, School of Electrical and Information Engineering, Australia"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5370-4464","authenticated-orcid":false,"given":"David","family":"Boland","sequence":"additional","affiliation":[{"name":"The University of Sydney, Faculty of Engineering, School of Electrical and Information Engineering, Australia"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3923-3499","authenticated-orcid":false,"given":"Philip H. W.","family":"Leong","sequence":"additional","affiliation":[{"name":"The University of Sydney, The University of Sydney Nano Institute, Faculty of Engineering, School of Electrical and Information Engineering, Australia"}]}],"member":"320","published-online":{"date-parts":[[2023,6,22]]},"reference":[{"key":"e_1_3_4_2_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.ymssp.2017.01.011"},{"key":"e_1_3_4_3_2","first-page":"70","volume-title":"Proceedings of the Wireless Innovation Forum Conference on Wireless Communications Technologies and Software Defined Radio (WInnComm\u201915)","author":"Bidyanta Nilangshu","year":"2015","unstructured":"Nilangshu Bidyanta, G. Vanhoy, M. Hirzallah, A. Akoglu, B. Ryu, and T. Bose. 2015. GPU and FPGA based architecture design for real-time signal classification. In Proceedings of the Wireless Innovation Forum Conference on Wireless Communications Technologies and Software Defined Radio (WInnComm\u201915). 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