{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,31]],"date-time":"2025-07-31T00:46:48Z","timestamp":1753922808162,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":25,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,3,26]],"date-time":"2023-03-26T00:00:00Z","timestamp":1679788800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"SPAWAR","award":["N660011824048"],"award-info":[{"award-number":["N660011824048"]}]},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["2212345"],"award-info":[{"award-number":["2212345"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,3,26]]},"DOI":"10.1145\/3569052.3578916","type":"proceedings-article","created":{"date-parts":[[2023,3,22]],"date-time":"2023-03-22T17:51:55Z","timestamp":1679507515000},"page":"101-102","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["The ALIGN Automated Analog Layout Engine"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5353-2364","authenticated-orcid":false,"given":"Sachin S.","family":"Sapatnekar","sequence":"first","affiliation":[{"name":"University of Minnesota, Minneapolis, MN, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,3,26]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"77","volume-title":"DAC","author":"Kunal K.","year":"2019","unstructured":"K. Kunal, et al., \"ALIGN: Open-source analog layout automation from the ground up,\" in Proc. DAC, pp. 77--80, 2019."},{"key":"e_1_3_2_1_2_1","first-page":"2008","article-title":"ALIGN: A system for automating analog layout","author":"Dhar T.","year":"2020","unstructured":"T. Dhar, et al., \"ALIGN: A system for automating analog layout,\" IEEE Des. Test, 2020. Available at arXiv:2008.10682.","journal-title":"IEEE Des. Test"},{"volume-title":"Analog layout, intelligently generated from netlists,\" Software reposi- tory, accessed","year":"2023","key":"e_1_3_2_1_3_1","unstructured":"\"ALIGN: Analog layout, intelligently generated from netlists,\" Software reposi- tory, accessed January 29, 2023. https:\/\/github.com\/ALIGN-analoglayout\/ALIGN- public."},{"key":"e_1_3_2_1_4_1","volume-title":"DATE","author":"Kunal K.","year":"2020","unstructured":"K. Kunal, et al., \"GANA: Graph convolutional network based automated netlist annotation for analog circuits,\" in Proc. DATE, 2020."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415685"},{"key":"e_1_3_2_1_6_1","volume-title":"Comput. Aid. D.","author":"Kunal K.","year":"2023","unstructured":"K. Kunal, et al., \"GNN-based hierarchical annotation for analog circuits,\" IEEE T. Comput. Aid. D., 2023. (early access)."},{"key":"e_1_3_2_1_7_1","volume-title":"ICCAD","author":"Sharma A. K.","year":"2021","unstructured":"A. K. Sharma, et al., \"Performance-aware common-centroid placement and routing of transistor arrays in analog circuits,\" in Proc. ICCAD, 2021."},{"key":"e_1_3_2_1_8_1","volume-title":"ASP-DAC","author":"Karmokar N.","year":"2022","unstructured":"N. Karmokar, et al., \"Common-centroid layout for active and passive devices: A review and the road ahead,\" in Proc. ASP-DAC, 2022."},{"key":"e_1_3_2_1_9_1","first-page":"166","volume-title":"DATE","author":"Karmokar N.","year":"2022","unstructured":"N. Karmokar, et al., \"Constructive common-centroid placement and routing for binary-weighted capacitor arrays,\" in Proc. DATE, pp. 166--171, 2022."},{"key":"e_1_3_2_1_10_1","volume-title":"Comput. Aid. D.","author":"Karmokar N.","year":"2023","unstructured":"N. Karmokar, et al., \"Constructive placement and routing for common-centroid capacitor arrays in binary-weighted and split DACs,\" IEEE T. Comput. Aid. D., 2023. (early access)."},{"key":"e_1_3_2_1_11_1","volume-title":"DATE","author":"Karmokar N.","year":"2023","unstructured":"N. Karmokar, et al., \"Minimum unit capacitance calculation for binary-weighted capacitor arrays,\" in Proc. DATE, 2023."},{"key":"e_1_3_2_1_12_1","first-page":"1224","volume-title":"DATE","author":"Sharma A. K.","year":"2021","unstructured":"A. K. Sharma, et al., \"Common-centroid layouts for analog circuits: Advantages and limitations,\" in Proc. DATE, pp. 1224--1229, 2021."},{"key":"e_1_3_2_1_13_1","first-page":"159","volume-title":"ISPD","year":"2022","unstructured":"Ramprasath S., et al., \"Analog\/mixed-signal layout optimization using optimal well taps,\" in Proc. ISPD, pp. 159--166, 2022."},{"volume-title":"Des. Automat. El.","year":"2023","key":"e_1_3_2_1_14_1","unstructured":"Ramprasath S., et al., \"A generalized methodology for well island generation and well-tap insertion in analog\/mixed-signal layouts,\" ACM T. Des. Automat. El., 2023. (in press)."},{"key":"e_1_3_2_1_15_1","volume-title":"DATE","author":"Lin Y.","year":"2022","unstructured":"Y. Lin, et al., \"Are analytical techniques worthwhile for analog IC placement?,\" in Proc. DATE, 2022."},{"key":"e_1_3_2_1_16_1","volume-title":"DATE","author":"Dhar T.","year":"2022","unstructured":"T. Dhar, et al., \"A charge flow formulation for guiding analog\/mixed-signal place- ment,\" in Proc. DATE, 2022."},{"key":"e_1_3_2_1_17_1","first-page":"158","article-title":"Fast and efficient constraint evaluation of analog layout using machine learning models","author":"Dhar T.","year":"2021","unstructured":"T. Dhar, et al., \"Fast and efficient constraint evaluation of analog layout using machine learning models,\" in Proc. ASP-DAC, pp. 158--163, 2021.","journal-title":"Proc. ASP-DAC"},{"key":"e_1_3_2_1_18_1","volume-title":"ISVLSI","author":"Li Y.","year":"2020","unstructured":"Y. Li, et al., \"Exploring a machine learning approach to performance driven analog IC placement,\" in Proc. ISVLSI, 2020."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415624"},{"key":"e_1_3_2_1_20_1","first-page":"1","volume-title":"A circuit attention network-based actor-critic learning approach to robust analog transistor sizing,\" in Proceedings of Workshop on Machine Learning for CAD","author":"Li Y.","year":"2021","unstructured":"Y. Li, et al., \"A circuit attention network-based actor-critic learning approach to robust analog transistor sizing,\" in Proceedings of Workshop on Machine Learning for CAD, pp. 1--6, 2021."},{"key":"e_1_3_2_1_21_1","volume-title":"Des. Automat. El.","volume":"28","author":"Li Y.","year":"2022","unstructured":"Y. Li, et al., \"Performance-driven wire sizing for analog integrated circuits,\" ACM T. Des. Automat. El., vol. 28, Dec. 2022."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643445"},{"key":"e_1_3_2_1_23_1","first-page":"2","article-title":"A digital LDO in 22nm CMOS with a 4b self-triggered binary search windowed flash ADC featuring automatic analog layout generator framework","author":"Liu X.","year":"2022","unstructured":"X. Liu, et al., \"A digital LDO in 22nm CMOS with a 4b self-triggered binary search windowed flash ADC featuring automatic analog layout generator framework,\" in Proc. A-SSCC, pp. 2--4, 2022.","journal-title":"Proc. A-SSCC"},{"key":"e_1_3_2_1_24_1","first-page":"96","article-title":"A 1-to-3GHz co-channel blocker resistant, spatially and spectrally passive MIMO receiver in 65nm CMOS with 6dBm in-band\/in-notch B1dB","volume":"64","author":"Poojary J.","year":"2021","unstructured":"J. Poojary and R. Harjani, \"A 1-to-3GHz co-channel blocker resistant, spatially and spectrally passive MIMO receiver in 65nm CMOS with 6dBm in-band\/in-notch B1dB,\" in Proceedings of the IEEE International Solid-State Circuits Conference, vol. 64, pp. 96--98, 2021.","journal-title":"Proceedings of the IEEE International Solid-State Circuits Conference"},{"key":"e_1_3_2_1_25_1","volume-title":"DATE","author":"Kamineni S.","year":"2023","unstructured":"S. Kamineni, et al., \"AuxcellGen: A framework for autonomous generation of analog and memory unit cells,\" in Proc. DATE, 2023"}],"event":{"name":"ISPD '23: International Symposium on Physical Design","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Virtual Event USA","acronym":"ISPD '23"},"container-title":["Proceedings of the 2023 International Symposium on Physical Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3569052.3578916","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3569052.3578916","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T17:51:41Z","timestamp":1750182701000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3569052.3578916"}},"subtitle":["Progress, Learnings, and Open Issues"],"short-title":[],"issued":{"date-parts":[[2023,3,26]]},"references-count":25,"alternative-id":["10.1145\/3569052.3578916","10.1145\/3569052"],"URL":"https:\/\/doi.org\/10.1145\/3569052.3578916","relation":{},"subject":[],"published":{"date-parts":[[2023,3,26]]},"assertion":[{"value":"2023-03-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}