{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:42:30Z","timestamp":1780674150406,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":16,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,3,26]],"date-time":"2023-03-26T00:00:00Z","timestamp":1679788800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,3,26]]},"DOI":"10.1145\/3569052.3578925","type":"proceedings-article","created":{"date-parts":[[2023,3,22]],"date-time":"2023-03-22T17:51:55Z","timestamp":1679507515000},"page":"62-70","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["On Legalization of Die Bonding Bumps and Pads for 3D ICs"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3966-1749","authenticated-orcid":false,"given":"Sai","family":"Pentapati","sequence":"first","affiliation":[{"name":"Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0393-0230","authenticated-orcid":false,"given":"Anthony","family":"Agnesina","sequence":"additional","affiliation":[{"name":"NVIDIA Corporation, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7842-7774","authenticated-orcid":false,"given":"Moritz","family":"Brunion","sequence":"additional","affiliation":[{"name":"University of Bremen, Bremen, Germany"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0116-1351","authenticated-orcid":false,"given":"Yen-Hsiang","family":"Huang","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, Atlanta, Georgia"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2267-5282","authenticated-orcid":false,"given":"Sung Kyu","family":"Lim","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2023,3,26]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993637"},{"key":"e_1_3_2_1_2_1","volume-title":"https:\/\/www.anandtech.com\/show\/16725","author":"Cache Ryzen Chiplets AMD","year":"2018","unstructured":"AMD 3D V-Cache Ryzen Chiplets. https:\/\/www.anandtech.com\/show\/16725, 2018."},{"key":"e_1_3_2_1_3_1","volume-title":"Design-Process-Technology Co-optimization XV. SPIE","author":"Dragomir","year":"2021","unstructured":"Dragomir Milojevic et al. Fine-pitch 3D system integration and advanced CMOS nodes: technology and system design perspective. In Design-Process-Technology Co-optimization XV. SPIE, 2021."},{"key":"e_1_3_2_1_4_1","volume-title":"DATE","author":"Lennart","year":"2020","unstructured":"Lennart Bamberg et al. Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs. DATE, 2020."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2016.2544837"},{"key":"e_1_3_2_1_6_1","volume-title":"2020 IEEE\/ACM International Conference On Computer Aided Design (ICCAD)","author":"Sai","year":"2020","unstructured":"Sai Pentapati et al. Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICs. In 2020 IEEE\/ACM International Conference On Computer Aided Design (ICCAD), 2020."},{"key":"e_1_3_2_1_7_1","volume-title":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","author":"Imed","year":"2019","unstructured":"Imed Jani et al. Characterization of Fine Pitch Hybrid Bonding Pads using Electrical Misalignment Test Vehicle. In 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC32862.2020.00099"},{"key":"e_1_3_2_1_9_1","article-title":"Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-level 3D ICs","author":"Ku B. W.","year":"2019","unstructured":"B. W. Ku et al. Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-level 3D ICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"e_1_3_2_1_10_1","volume-title":"Eisenmann. Force-Directed Placement of VLSI Circuits. In Proceedings of the 2015 Symposium on International Symposium on Physical Design","author":"Hans","year":"2015","unstructured":"Hans Eisenmann. Force-Directed Placement of VLSI Circuits. In Proceedings of the 2015 Symposium on International Symposium on Physical Design, 2015."},{"key":"e_1_3_2_1_11_1","volume-title":"Proceedings of the 2016 on International Symposium on Physical Design","author":"Jingwei","year":"2016","unstructured":"Jingwei Lu et al. EPlace-3D: Electrostatics Based Placement for 3D-ICs. In Proceedings of the 2016 on International Symposium on Physical Design, 2016."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.1257591"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1007\/BF02278710"},{"key":"e_1_3_2_1_14_1","volume-title":"Handbook of Algorithms for Physical Design Automation","author":"Pan David Z.","year":"2008","unstructured":"David Z. Pan, Bill Halpin, and Haoxing Ren. Timing-Driven Placement. In Handbook of Algorithms for Physical Design Automation, 2008."},{"key":"e_1_3_2_1_15_1","volume-title":"Practical Bayesian Optimization of Machine Learning Algorithms. In NIPS","author":"Snoek Jasper","year":"2012","unstructured":"Jasper Snoek, H. Larochelle, and Ryan P. Adams. Practical Bayesian Optimization of Machine Learning Algorithms. In NIPS, 2012."},{"key":"e_1_3_2_1_16_1","volume-title":"Bayesian Optimization: Open source constrained global optimization tool for Python","author":"Nogueira Fernando","year":"2014","unstructured":"Fernando Nogueira. Bayesian Optimization: Open source constrained global optimization tool for Python, 2014--."}],"event":{"name":"ISPD '23: International Symposium on Physical Design","location":"Virtual Event USA","acronym":"ISPD '23","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the 2023 International Symposium on Physical Design"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3569052.3578925","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3569052.3578925","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T17:51:41Z","timestamp":1750182701000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3569052.3578925"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,3,26]]},"references-count":16,"alternative-id":["10.1145\/3569052.3578925","10.1145\/3569052"],"URL":"https:\/\/doi.org\/10.1145\/3569052.3578925","relation":{},"subject":[],"published":{"date-parts":[[2023,3,26]]},"assertion":[{"value":"2023-03-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}