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Syst."],"published-print":{"date-parts":[[2023,7,31]]},"abstract":"<jats:p>\n            Performing\n            <jats:bold>chemical mechanical polishing (CMP)<\/jats:bold>\n            modeling for physical verification on an\n            <jats:bold>integrated circuit (IC)<\/jats:bold>\n            chip is vital to minimize its manufacturing yield loss. Traditional CMP models calculate post-CMP topography height of the IC\u2019s layout based on physical principles and empirical experiments, which is computationally costly and time-consuming. In this work, we propose a CmpCNN framework based on\n            <jats:bold>convolutional neural networks (CNNs)<\/jats:bold>\n            with a transfer learning method to accelerate the CMP modeling process. It utilizes a multi-input strategy by feeding the binary image of layout and its density into our CNN-based model to extract features more efficiently. The transfer learning method is adopted to different CMP process parameters and different categories of circuits to further improve its prediction accuracy and convergence speed. Experimental results show that our CmpCNN framework achieves a competitive\n            <jats:bold>root mean square error (<\/jats:bold>\n            <jats:italic>RMSE<\/jats:italic>\n            <jats:bold>)<\/jats:bold>\n            of 2.7733\u00c5 with 1.89\u00d7 reduction compared to the prior work, and a 57\u00d7 speedup compared to the commercial CMP simulation tool.\n          <\/jats:p>","DOI":"10.1145\/3569941","type":"journal-article","created":{"date-parts":[[2022,10,27]],"date-time":"2022-10-27T12:27:23Z","timestamp":1666873643000},"page":"1-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["CmpCNN: CMP Modeling with Transfer Learning CNN Architecture"],"prefix":"10.1145","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9353-8584","authenticated-orcid":false,"given":"Qing","family":"Zhang","sequence":"first","affiliation":[{"name":"Department of Micro-Nano Electronics and MoE Key Lab of Artificial Intelligence, Shanghai Jiao Tong University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1541-5412","authenticated-orcid":false,"given":"Huajie","family":"Huang","sequence":"additional","affiliation":[{"name":"Department of Micro-Nano Electronics and MoE Key Lab of Artificial Intelligence, Shanghai Jiao Tong University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1857-5609","authenticated-orcid":false,"given":"Jizuo","family":"Li","sequence":"additional","affiliation":[{"name":"Department of Micro-Nano Electronics and MoE Key Lab of Artificial Intelligence, Shanghai Jiao Tong University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4101-6207","authenticated-orcid":false,"given":"Yuhang","family":"Zhang","sequence":"additional","affiliation":[{"name":"Department of Micro-Nano Electronics and MoE Key Lab of Artificial Intelligence, Shanghai Jiao Tong University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6322-8614","authenticated-orcid":false,"given":"Yongfu","family":"Li","sequence":"additional","affiliation":[{"name":"Department of Micro-Nano Electronics and MoE Key Lab of Artificial Intelligence, Shanghai Jiao Tong University, Shanghai, China"}]}],"member":"320","published-online":{"date-parts":[[2023,5,17]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.mser.2004.06.002"},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1145\/2886097"},{"key":"e_1_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1007\/s10853-018-2357-6"},{"key":"e_1_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3001380"},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1117\/12.2514467"},{"key":"e_1_3_1_7_2","first-page":"173","volume-title":"Proceedings of Design-Process-Technology Co-optimization for Manufacturability X","author":"Katakamsetty Ushasree","year":"2016","unstructured":"Ushasree Katakamsetty, Jansen Chee, Yongfu Li, Colin Hui, Jaime Bravo, Tamba Gbondo-Tugbawa, Brian Lee, Kuang-Han Chen, Aaron Gower-Hall, and Sang-Min Han. 2016. Hotspot detection and removal flow using multi-level silicon-calibrated CMP models. In Proceedings of Design-Process-Technology Co-optimization for Manufacturability X. 173\u2013182."},{"key":"e_1_3_1_8_2","first-page":"225","volume-title":"Proceedings of Design-Process-Technology Co-optimization for Manufacturability XI","author":"Katakamsetty Ushasree","year":"2017","unstructured":"Ushasree Katakamsetty, Jiansheng Jansen Chee, Yongfu Li, Chiu Wing Hui, Yaodong Huang, and Ernesto Gene de la Garza. 2017. Cutting-edge CMP modeling for front-end-of-line (FEOL) and full stack hotspot detection for advanced technologies. In Proceedings of Design-Process-Technology Co-optimization for Manufacturability XI. 225\u2013232."},{"key":"e_1_3_1_9_2","volume-title":"Proceedings of International Conference on Planarization\/CMP Technology (ICPT)","author":"Katakamsetty Ushasree","year":"2018","unstructured":"Ushasree Katakamsetty, Yongfu Li, Ernesto Gene de la Garza, D. Xu, L. Cheng, E. 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