{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,12]],"date-time":"2026-01-12T21:34:46Z","timestamp":1768253686622,"version":"3.49.0"},"reference-count":33,"publisher":"Association for Computing Machinery (ACM)","issue":"5","license":[{"start":{"date-parts":[[2024,8,14]],"date-time":"2024-08-14T00:00:00Z","timestamp":1723593600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"NIH","award":["RF1MH120034-01"],"award-info":[{"award-number":["RF1MH120034-01"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2024,9,30]]},"abstract":"<jats:p>We present the Sparse Synchronous model (SSM) of computation, which allows a programmer to specify software timing more precisely than the traditional \u201cheartbeat\u201d of mainstream operating systems or the synchronous languages. SSM is a mix of semantics inspired by discrete event simulators and the synchronous languages designed to operate in resource-constrained environments such as microcontrollers. SSM provides precise timing prescriptions, concurrency, and determinism. We implement SSM in SSML, a toy language along with a runtime system that includes a scheduler, memory manager, and an interface that works with a real-time operating system to keep the model synchronized with the real world. Experimentally, we find our implementation is able to perform jitter-free I\/O in the 10s of kHz on a microcontroller.<\/jats:p>","DOI":"10.1145\/3572920","type":"journal-article","created":{"date-parts":[[2022,12,14]],"date-time":"2022-12-14T12:14:44Z","timestamp":1671020084000},"page":"1-30","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":3,"title":["The Sparse Synchronous Model on Real Hardware"],"prefix":"10.1145","volume":"23","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6355-3767","authenticated-orcid":false,"given":"John","family":"Hui","sequence":"first","affiliation":[{"name":"Columbia University, New York, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2609-4861","authenticated-orcid":false,"given":"Stephen A.","family":"Edwards","sequence":"additional","affiliation":[{"name":"Columbia University, New York, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2024,8,14]]},"reference":[{"key":"e_1_3_2_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2010.5558636"},{"key":"e_1_3_2_3_2","doi-asserted-by":"publisher","DOI":"10.1017\/S095679680000157X"},{"key":"e_1_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45749-6_17"},{"key":"e_1_3_2_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.805826"},{"key":"e_1_3_2_6_2","doi-asserted-by":"publisher","DOI":"10.1016\/0167-6423(92)90005-V"},{"key":"e_1_3_2_7_2","doi-asserted-by":"publisher","DOI":"10.4230\/DagSemProc.09481.1"},{"key":"e_1_3_2_8_2","doi-asserted-by":"publisher","DOI":"10.1002\/spe.4380210406"},{"key":"e_1_3_2_9_2","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.919"},{"key":"e_1_3_2_10_2","volume-title":"Safe Reactive Programming: The FunLoft Language","author":"Boussinot Fr\u00e9d\u00e9ric","year":"2010","unstructured":"Fr\u00e9d\u00e9ric Boussinot. 2010. Safe Reactive Programming: The FunLoft Language. Lambert Academic Publishing."},{"key":"e_1_3_2_11_2","doi-asserted-by":"publisher","DOI":"10.1145\/99583.99616"},{"key":"e_1_3_2_12_2","doi-asserted-by":"publisher","DOI":"10.1145\/28395.28434"},{"key":"e_1_3_2_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/FDL50818.2020.9232938"},{"key":"e_1_3_2_14_2","volume-title":"IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language (1364\u20131995)","year":"1996","unstructured":"IEEE Computer Society 1996. IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language (1364\u20131995). IEEE Computer Society, Los Alamitos, CA."},{"key":"e_1_3_2_15_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-31954-2_2"},{"key":"e_1_3_2_16_2","doi-asserted-by":"publisher","DOI":"10.1023\/A:1018998524196"},{"key":"e_1_3_2_17_2","article-title":"Compiling Functional Languages","author":"Leroy Xavier","year":"2002","unstructured":"Xavier Leroy. 2002. Compiling Functional Languages. Presentation at Spring School \u201cSemantics of Programming Languages.\u201d Retrieved from https:\/\/xavierleroy.org\/talks\/compilation-agay.pdf.","journal-title":"Presentation at Spring School \u201cSemantics of Programming Languages.\u201d"},{"key":"e_1_3_2_18_2","doi-asserted-by":"publisher","DOI":"10.1145\/3448128"},{"key":"e_1_3_2_19_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-41131-2_4"},{"key":"e_1_3_2_20_2","doi-asserted-by":"publisher","DOI":"10.1145\/2790449.2790509"},{"key":"e_1_3_2_21_2","doi-asserted-by":"publisher","DOI":"10.1145\/1069774.1069782"},{"key":"e_1_3_2_22_2","doi-asserted-by":"publisher","DOI":"10.1145\/2692956.2663188"},{"key":"e_1_3_2_23_2","article-title":"The FreeHDL Compiler\/Simulator System","author":"Naroska Edwin","year":"1998","unstructured":"Edwin Naroska. 1998. The FreeHDL Compiler\/Simulator System. Retrieved from http:\/\/freehdl.seul.org\/.","journal-title":"Retrieved from"},{"key":"e_1_3_2_24_2","doi-asserted-by":"publisher","DOI":"10.5555\/1534411"},{"key":"e_1_3_2_25_2","volume-title":"Advanced Topics in Types and Programming Languages","author":"Pottier Fran\u0146ois","year":"2004","unstructured":"Fran\u0146ois Pottier and Didier R\u00e9my. 2004. The essence of ML type inference. In Advanced Topics in Types and Programming Languages, Benjamin C. Pierce (Ed.). MIT Press, Cambridge, MA, Chapter 10."},{"key":"e_1_3_2_26_2","doi-asserted-by":"publisher","DOI":"10.1145\/3453483.3454032"},{"key":"e_1_3_2_27_2","doi-asserted-by":"publisher","DOI":"10.1145\/3211332.3211334"},{"key":"e_1_3_2_28_2","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715081"},{"key":"e_1_3_2_29_2","volume-title":"IEEE Standard VHDL Reference Manual (1076\u20131987)","year":"1988","unstructured":"The Institute of Electrical and Electronics Engineers (IEEE). 1988. IEEE Standard VHDL Reference Manual (1076\u20131987)."},{"key":"e_1_3_2_30_2","doi-asserted-by":"publisher","DOI":"10.1109\/FDL.2017.8303893"},{"key":"e_1_3_2_31_2","doi-asserted-by":"publisher","DOI":"10.1145\/2627350"},{"key":"e_1_3_2_32_2","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2007.5"},{"key":"e_1_3_2_33_2","volume-title":"From Ptides to PtidyOS, Designing Distributed Real-Time Embedded Systems","author":"Zou Jia","year":"2011","unstructured":"Jia Zou. 2011. From Ptides to PtidyOS, Designing Distributed Real-Time Embedded Systems. Ph. D. Dissertation. EECS Department, University of California, Berkeley."},{"key":"e_1_3_2_34_2","doi-asserted-by":"publisher","DOI":"10.1109\/RTAS.2009.39"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3572920","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3572920","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T17:51:38Z","timestamp":1750182698000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3572920"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,8,14]]},"references-count":33,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2024,9,30]]}},"alternative-id":["10.1145\/3572920"],"URL":"https:\/\/doi.org\/10.1145\/3572920","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"value":"1539-9087","type":"print"},{"value":"1558-3465","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,8,14]]},"assertion":[{"value":"2022-01-15","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-10-24","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2024-08-14","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}