{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T15:44:30Z","timestamp":1781883870127,"version":"3.54.5"},"reference-count":35,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2023,3,6]],"date-time":"2023-03-06T00:00:00Z","timestamp":1678060800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"crossref","award":["62072214 and 61572232"],"award-info":[{"award-number":["62072214 and 61572232"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100021171","name":"Guangdong Basic and Applied Basic Research Foundation","doi-asserted-by":"crossref","award":["2021B1515120048"],"award-info":[{"award-number":["2021B1515120048"]}],"id":[{"id":"10.13039\/501100021171","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Industry University Research Collaboration Project of Zhuhai","award":["ZH22017001210048PWC"],"award-info":[{"award-number":["ZH22017001210048PWC"]}]},{"name":"Open Project Program of Wuhan National Laboratory for Optoelectronics","award":["2020WNLOKF006"],"award-info":[{"award-number":["2020WNLOKF006"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Storage"],"published-print":{"date-parts":[[2023,5,31]]},"abstract":"<jats:p>\n            Garbage collection (GC) plays a pivotal role in the performance of 3D NAND flash memory, where Copyback has been widely used to accelerate valid page migration during GC. Unfortunately, copyback is constrained by the parity symmetry issue: data read from an odd\/even page must be written to an odd\/even page. After migrating two odd\/even consecutive pages, a free page between the two migrated pages will be wasted. Such wasted pages noticeably lower free space on flash memory and cause extra GCs, thereby degrading solid-state-disk (SSD) performance. To address this problem, we propose a page-state-aware cache scheme called\n            <jats:italic>PSA-Cache<\/jats:italic>\n            , which prevents page waste to boost the performance of NAND Flash-based SSDs. To facilitate making write-back scheduling decisions, PSA-Cache regulates write-back priorities for cached pages according to the state of pages in victim blocks. With high write-back-priority pages written back to flash chips, PSA-Cache effectively fends off page waste by breaking odd\/even consecutive pages in subsequent garbage collections. We quantitatively evaluate the performance of PSA-Cache in terms of the number of wasted pages, the number of GCs, and response time. We compare PSA-Cache with two state-of-the-art schemes, GCaR and TTflash, in addition to a baseline scheme LRU. The experimental results unveil that PSA-Cache outperforms the existing schemes. In particular, PSA-Cache curtails the number of wasted pages of GCaR and TTflash by 25.7% and 62.1%, respectively. PSA-Cache immensely cuts back the number of GC counts by up to 78.7% with an average of 49.6%. Furthermore, PSA-Cache slashes the average write response time by up to 85.4% with an average of 30.05%.\n          <\/jats:p>","DOI":"10.1145\/3574324","type":"journal-article","created":{"date-parts":[[2022,12,6]],"date-time":"2022-12-06T13:09:50Z","timestamp":1670332190000},"page":"1-27","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":6,"title":["PSA-Cache: A Page-state-aware Cache Scheme for Boosting 3D NAND Flash Performance"],"prefix":"10.1145","volume":"19","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1741-1319","authenticated-orcid":false,"given":"Shujie","family":"Pang","sequence":"first","affiliation":[{"name":"Department of Computer Science, Jinan University, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1522-8943","authenticated-orcid":false,"given":"Yuhui","family":"Deng","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Jinan University, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2128-9838","authenticated-orcid":false,"given":"Genxiong","family":"Zhang","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Jinan University, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1460-322X","authenticated-orcid":false,"given":"Yi","family":"Zhou","sequence":"additional","affiliation":[{"name":"TSYS School of Computer Science, Columbus State University, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7265-8299","authenticated-orcid":false,"given":"Yaoqin","family":"Huang","sequence":"additional","affiliation":[{"name":"Department of Computer Science, Jinan University, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8345-3587","authenticated-orcid":false,"given":"Xiao","family":"Qin","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Software Engineering, Auburn University, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2023,3,6]]},"reference":[{"issue":"1","key":"e_1_3_1_2_2","first-page":"140","article-title":"Error analysis and retention-aware error management for nand flash memory","volume":"17","author":"Cai Yu","year":"2013","unstructured":"Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Adrian Cristal, Osman S. Unsal, and Ken Mai. 2013. Error analysis and retention-aware error management for nand flash memory. Intel. Technol. J. 17, 1 (2013), 140\u2013165.","journal-title":"Intel. Technol. J."},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1145\/1027794.1027801"},{"key":"e_1_3_1_4_2","volume-title":"Proceedings of the International Journal of Electrical Energy","volume":"2","author":"Chang W.","year":"2014","unstructured":"W. Chang, Y. Lim, and J. Cho. 2014. An efficient copy-back operation scheme using dedicated flash memory controller in solid-state disks. In Proceedings of the International Journal of Electrical Energy, Vol. 2."},{"key":"e_1_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2010.12.003"},{"issue":"10","key":"e_1_3_1_6_2","first-page":"2230","article-title":"Aging capacitor supported cache management scheme for solid-state drives","volume":"39","author":"Gao Congming","year":"2019","unstructured":"Congming Gao, Liang Shi, Qiao Li, Kai Liu, Chun Jason Xue, Jun Yang, and Youtao Zhang. 2019. Aging capacitor supported cache management scheme for solid-state drives. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 39, 10 (2019), 2230\u20132239.","journal-title":"IEEE Trans. Comput.-Aided Design Integr. Circ. Syst."},{"key":"e_1_3_1_7_2","first-page":"1","volume-title":"Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium","author":"Hong Duwon","year":"2019","unstructured":"Duwon Hong, Myungsuk Kim, Jisung Park, Myoungsoo Jung, and Jihong Kim. 2019. Improving SSD performance using adaptive restricted-copyback operations. In Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium. 1\u20136."},{"key":"e_1_3_1_8_2","first-page":"57","volume-title":"Proceedings of the USENIX Annual Technical Conference","author":"Hu Xiameng","year":"2015","unstructured":"Xiameng Hu, Xiaolin Wang, Yechen Li, Lan Zhou, Yingwei Luo, Chen Ding, Song Jiang, and Zhenlin Wang. 2015. LAMA: Optimized locality-aware memory allocation for key-value cache. In Proceedings of the USENIX Annual Technical Conference. 57\u201369."},{"key":"e_1_3_1_9_2","first-page":"54","volume-title":"Proceedings of the IEEE International Conference on Networking, Architecture, and Storage","author":"Hu Yang","year":"2015","unstructured":"Yang Hu, Hong Jiang, Dan Feng, Hao Luo, and Lei Tian. 2015. PASS: A proactive and adaptive SSD buffer scheme for data-intensive workloads. In Proceedings of the IEEE International Conference on Networking, Architecture, and Storage. 54\u201363."},{"key":"e_1_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1145\/1995896.1995912"},{"key":"e_1_3_1_11_2","first-page":"192","volume-title":"Proceedings of the IEEE Symposium on VLSI Technology","author":"Jang Jaehoon","year":"2009","unstructured":"Jaehoon Jang, Han-Soo Kim, Wonseok Cho, Hoosung Cho, Jinho Kim, Sun Il Shim, Jae-Hun Jeong, Byoung-Keun Son, Dong Woo Kim, Jae-Joo Shim, et\u00a0al. 2009. Vertical cell array using TCAT (terabit cell array transistor) technology for ultra high density NAND flash memory. In Proceedings of the IEEE Symposium on VLSI Technology. 192\u2013193."},{"key":"e_1_3_1_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2012.6227449"},{"key":"e_1_3_1_13_2","first-page":"1","volume-title":"Proceedings of the 15th USENIX Conference on File and Storage Technologies","author":"Kim H.","year":"2008","unstructured":"H. Kim and S. Ahn. 2008. BPLRU: A buffer management scheme for improving random writes in flash storage. In Proceedings of the 15th USENIX Conference on File and Storage Technologies. 1\u201314."},{"key":"e_1_3_1_14_2","volume-title":"UMASS Trace Repository","author":"Software Laboratory for Advanced System","year":"2007","unstructured":"Laboratory for Advanced System Software. 2007. UMASS Trace Repository. Retrieved from http:\/\/traces.cs.umass.edu\/index.php\/Storage\/Storage."},{"key":"e_1_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2011.5762711"},{"key":"e_1_3_1_16_2","first-page":"67","volume-title":"Proceedings of the 16th USENIX Conference on File and Storage Technologies","author":"Liu Chun Yi","year":"2018","unstructured":"Chun Yi Liu, Jagadish B. Kotra, Myoungsoo Jung, and Mahmut T. Kandemir. 2018. Pen: Design and evaluation of partial-erase for 3D NAND-based high density SSDs. In Proceedings of the 16th USENIX Conference on File and Storage Technologies. 67\u201382."},{"key":"e_1_3_1_17_2","unstructured":"Antonio Manuel and D\u2019Abreu. 2015. Partial block erase for a three dimensional (3D) memory. (May 192015). U.S. Patent 9286989."},{"key":"e_1_3_1_18_2","unstructured":"Eun Chu Oh and Junjin Kong. 2015. Nonvolatile memory device and sub-block managing method thereof. (Feb. 242015). U.S. Patent 8964481."},{"key":"e_1_3_1_19_2","volume-title":"Open NAND Flash Interface Specification Revision 5.0","year":"2021","unstructured":"ONFI. 2021. Open NAND Flash Interface Specification Revision 5.0. Retrieved from https:\/\/www.onfi.org\/specifications."},{"key":"e_1_3_1_20_2","volume-title":"Samsung 980 Pro NVMe SSD.","unstructured":"Samsung. Samsung 980 Pro NVMe SSD. Retrieved from https:\/\/www.samsung.com\/cn\/memory-storage\/nvme-ssd\/980-pro-nvme-m-2-1tb-mz-v8p500bw."},{"key":"e_1_3_1_21_2","volume-title":"Samsung k9xxg08uxa Nand Flash Memory Datasheet","unstructured":"Samsung. Samsung k9xxg08uxa Nand Flash Memory Datasheet. Retrieved from http:\/\/www.samsung.com\/products\/semiconductor\/flash\/technicallinfo\/datasheets."},{"key":"e_1_3_1_22_2","first-page":"1","volume-title":"Proceedings of the 26th IEEE Symposium on Mass Storage Systems and Technologies","author":"Shim Hyotaek","year":"2010","unstructured":"Hyotaek Shim, Bon-Keun Seo, Jin-Soo Kim, and Seungryoul Maeng. 2010. An adaptive partitioning scheme for DRAM-based cache in solid state drives. In Proceedings of the 26th IEEE Symposium on Mass Storage Systems and Technologies. 1\u201312."},{"key":"e_1_3_1_23_2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2020.3006655"},{"key":"e_1_3_1_24_2","volume-title":"MSR Cambridge Traces","author":"IOTTA SNIA","year":"2007","unstructured":"SNIA IOTTA. 2007. MSR Cambridge Traces. Retrieved from http:\/\/iotta.snia.org\/traces\/block-io\/388?only=386."},{"key":"e_1_3_1_25_2","volume-title":"NAND Memory Toggle DDR1.0 Technical Data Sheet","year":"2013","unstructured":"TOSHIBA. 2013. NAND Memory Toggle DDR1.0 Technical Data Sheet. Tokyo, Japan."},{"key":"e_1_3_1_26_2","volume-title":"3D Flash Memory Toggle DDR2.0 Technical Data Sheet","year":"2016","unstructured":"TOSHIBA. 2016. 3D Flash Memory Toggle DDR2.0 Technical Data Sheet. Tokyo, Japan."},{"key":"e_1_3_1_27_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3001262"},{"key":"e_1_3_1_28_2","first-page":"1","volume-title":"Proceedings of the 55th Design Automation Conference","author":"Wu Fei","year":"2018","unstructured":"Fei Wu, Jiaona Zhou, Shunzhuo Wang, Yajuan Du, Chengmo Yang, and Changsheng Xie. 2018. FastGC: Accelerate garbage collection via an efficient copyback-based data migration in SSDs. In Proceedings of the 55th Design Automation Conference. 1\u20136."},{"key":"e_1_3_1_29_2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2017.2692757"},{"key":"e_1_3_1_30_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.2974346"},{"key":"e_1_3_1_31_2","first-page":"15","volume-title":"Proceedings of the 15th USENIX Conference on File and Storage Technologies","author":"Yan Shiqin","year":"2017","unstructured":"Shiqin Yan, Huaicheng Li, Mingzhe Hao, Michael Hao Tong, Swaminatahan Sundararaman, Andrew A. Chien, and Haryadi S. Gunawi. 2017. Tiny-tail flash: Near-perfect elimination of garbage collection tail latencies in NAND SSDs. In Proceedings of the 15th USENIX Conference on File and Storage Technologies. 15\u201328."},{"key":"e_1_3_1_32_2","first-page":"66","volume-title":"Proceedings of the International Conference on Smart Computing","author":"Yang Ming-Chang","year":"2014","unstructured":"Ming-Chang Yang, Yu-Ming Chang, Che-Wei Tsao, Po-Chun Huang, Yuan-Hao Chang, and Tei-Wei Kuo. 2014. Garbage collection and wear leveling for flash memory: Past and future. In Proceedings of the International Conference on Smart Computing. 66\u201373."},{"key":"e_1_3_1_33_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3214679"},{"key":"e_1_3_1_34_2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2019.2934458"},{"key":"e_1_3_1_35_2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2020.2994075"},{"issue":"2","key":"e_1_3_1_36_2","article-title":"Understanding and alleviating the impact of the flash address translation on solid state devices","volume":"13","author":"Zhou You","year":"2017","unstructured":"You Zhou, Fei Wu, Ping Huang, Xubin He, Changsheng Xie, and Jian Zhou. 2017. Understanding and alleviating the impact of the flash address translation on solid state devices. ACM Trans. Stor. 13, 2 (2017).","journal-title":"ACM Trans. Stor."}],"container-title":["ACM Transactions on Storage"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3574324","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3574324","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T18:43:51Z","timestamp":1750272231000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3574324"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,3,6]]},"references-count":35,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2023,5,31]]}},"alternative-id":["10.1145\/3574324"],"URL":"https:\/\/doi.org\/10.1145\/3574324","relation":{},"ISSN":["1553-3077","1553-3093"],"issn-type":[{"value":"1553-3077","type":"print"},{"value":"1553-3093","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,3,6]]},"assertion":[{"value":"2022-04-05","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-11-22","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-03-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}