{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,29]],"date-time":"2026-03-29T02:27:36Z","timestamp":1774751256715,"version":"3.50.1"},"reference-count":45,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2023,3,1]],"date-time":"2023-03-01T00:00:00Z","timestamp":1677628800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"European High Performance Computing Joint Undertaking (JU) under Framework Partnership","award":["800928 and 101036168"],"award-info":[{"award-number":["800928 and 101036168"]}]},{"name":"European Union\u2019s Horizon 2020 research and innovation programme"},{"name":"EPI-SGA2 project","award":["PCI2022-132935"],"award-info":[{"award-number":["PCI2022-132935"]}]},{"DOI":"10.13039\/501100004837","name":"Spanish Ministry of Science and Innovation","doi-asserted-by":"crossref","award":["PID2019-107255GB-C21\/AEI\/10.13039\/501100011033"],"award-info":[{"award-number":["PID2019-107255GB-C21\/AEI\/10.13039\/501100011033"]}],"id":[{"id":"10.13039\/501100004837","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Archit. Code Optim."],"published-print":{"date-parts":[[2023,6,30]]},"abstract":"<jats:p>\n            The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores for the High Performance Computing (HPC) application domain. In this article,\n            <jats:xref ref-type=\"fn\">\n              <jats:sup>1<\/jats:sup>\n            <\/jats:xref>\n            we present Vitruvius+, the vector processing acceleration engine that represents the core of vector instruction execution in the HPC challenge that comes within the EuroHPC initiative. It implements the RISC-V vector extension (RVV) 0.7.1 and can be easily connected to a scalar core using the Open Vector Interface standard. Vitruvius+ natively supports long vectors: 256 double precision floating-point elements in a single vector register. It is composed of a set of identical vector pipelines (lanes), each containing a slice of the Vector Register File and functional units (one integer, one floating point). The vector instruction execution scheme is hybrid in-order\/out-of-order and is supported by register renaming and arithmetic\/memory instruction decoupling. On a stand-alone synthesis, Vitruvius+ reaches a maximum frequency of 1.4 GHz in typical conditions (TT\/0.80V\/25\u00b0C) using\n            <jats:sc>GlobalFoundries<\/jats:sc>\n            22FDX FD-SOI. The silicon implementation has a total area of 1.3 mm\n            <jats:sup>2<\/jats:sup>\n            and maximum estimated power of \u223c920 mW for one instance of Vitruvius+ equipped with eight vector lanes.\n          <\/jats:p>","DOI":"10.1145\/3575861","type":"journal-article","created":{"date-parts":[[2022,12,9]],"date-time":"2022-12-09T12:10:15Z","timestamp":1670587815000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":52,"title":["Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications"],"prefix":"10.1145","volume":"20","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8558-5690","authenticated-orcid":false,"given":"Francesco","family":"Minervini","sequence":"first","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6729-4187","authenticated-orcid":false,"given":"Oscar","family":"Palomar","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0544-9697","authenticated-orcid":false,"given":"Osman","family":"Unsal","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1385-7962","authenticated-orcid":false,"given":"Enrico","family":"Reggiani","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1840-2855","authenticated-orcid":false,"given":"Josue","family":"Quiroga","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0607-5615","authenticated-orcid":false,"given":"Joan","family":"Marimon","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7714-0277","authenticated-orcid":false,"given":"Carlos","family":"Rojas","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2407-1228","authenticated-orcid":false,"given":"Roger","family":"Figueras","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7458-979X","authenticated-orcid":false,"given":"Abraham","family":"Ruiz","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7984-5596","authenticated-orcid":false,"given":"Alberto","family":"Gonzalez","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7453-1803","authenticated-orcid":false,"given":"Jonnatan","family":"Mendoza","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5092-3829","authenticated-orcid":false,"given":"Ivan","family":"Vargas","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6560-1016","authenticated-orcid":false,"given":"C\u00e9sar","family":"Hernandez","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1704-9364","authenticated-orcid":false,"given":"Joan","family":"Cabre","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8934-7411","authenticated-orcid":false,"given":"Lina","family":"Khoirunisya","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7183-0023","authenticated-orcid":false,"given":"Mustapha","family":"Bouhali","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8291-509X","authenticated-orcid":false,"given":"Julian","family":"Pavon","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1290-3253","authenticated-orcid":false,"given":"Francesc","family":"Moll","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0214-9904","authenticated-orcid":false,"given":"Mauro","family":"Olivieri","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8365-7002","authenticated-orcid":false,"given":"Mario","family":"Kovac","sequence":"additional","affiliation":[{"name":"University of Zagreb, FER, Zagreb, Croatia"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7486-4627","authenticated-orcid":false,"given":"Mate","family":"Kovac","sequence":"additional","affiliation":[{"name":"University of Zagreb, FER, Zagreb, Croatia"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4558-7269","authenticated-orcid":false,"given":"Leon","family":"Dragic","sequence":"additional","affiliation":[{"name":"University of Zagreb, FER, Zagreb, Croatia"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2917-2482","authenticated-orcid":false,"given":"Mateo","family":"Valero","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1277-9296","authenticated-orcid":false,"given":"Adrian","family":"Cristal","sequence":"additional","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}]}],"member":"320","published-online":{"date-parts":[[2023,3]]},"reference":[{"key":"e_1_3_2_2_2","unstructured":"Rob Aitken. 2021. Performance per Watt Is the New Moore\u2019s Law. Retrieved December 15 2022 from https:\/\/www.arm.com\/blogs\/blueprint\/performance-per-watt."},{"key":"e_1_3_2_3_2","unstructured":"AndesCore. 2020. AndesCore NX27V Processor 64-bit CPU with RISC-V Vector Extension. Retrieved May 29 2022 from http:\/\/www.andestech.com\/en\/products-solutions\/andescore-processors\/riscv-nx27v\/."},{"key":"e_1_3_2_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/COOLCHIPS52128.2021.9410320"},{"key":"e_1_3_2_5_2","unstructured":"Imad Al Assir Mohamad El Iskandarani Hadi Rayan Al Sandid and Mazen A. R. Saghir. 2021. Arrow: A RISC-V vector accelerator for machine learning inference. arxiv:2107.07169 (2021)."},{"key":"e_1_3_2_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00016"},{"key":"e_1_3_2_7_2","unstructured":"Schmidt Colin Ou Albert and Asanovi\u0107 Krste. 218. Hwacha V4: Decoupled Data Parallel Custom Extension. Retrieved December 15 2022 from https:\/\/riscv.org\/wp-content\/uploads\/2018\/12\/Hwacha-A-Data-Parallel-RISC-V-Extension-and-Implementation-Schmidt-Ou-.pdf."},{"key":"e_1_3_2_8_2","unstructured":"Control Data Corporation. 1975. Control Data STAR-100 Computer . Control Data Corporation. http:\/\/bitsavers.trailing-edge.com\/pdf\/cdc\/cyber\/cyber_200\/60256000_STAR-100hw_Dec75.pdf."},{"key":"e_1_3_2_9_2","article-title":"Intel AVX-512 Instructions and Their Use in the Implementation of Math Functions","author":"Cornea Marius","year":"2015","unstructured":"Marius Cornea. 2015. Intel AVX-512 Instructions and Their Use in the Implementation of Math Functions. Intel Corporation.","journal-title":"Intel Corporation."},{"key":"e_1_3_2_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2034764"},{"key":"e_1_3_2_11_2","doi-asserted-by":"publisher","DOI":"10.1109\/2.44900"},{"key":"e_1_3_2_12_2","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000108"},{"key":"e_1_3_2_13_2","doi-asserted-by":"publisher","DOI":"10.5555\/525424.822650"},{"key":"e_1_3_2_14_2","doi-asserted-by":"publisher","DOI":"10.1145\/277830.277935"},{"key":"e_1_3_2_15_2","unstructured":"EuroHPC. 2018. The European High Performance Computing Joint Undertaking (EuroHPC JU). Retrieved May 29 2022 from https:\/\/eurohpc-ju.europa.eu\/."},{"key":"e_1_3_2_16_2","unstructured":"European Processor Initiative. 2019. EPI Accelerator. Retrieved May 29 2022 from https:\/\/www.european-processor-initiative.eu\/accelerator\/."},{"key":"e_1_3_2_17_2","unstructured":"Exascale Computing Project. 2018. Exascale Computing Project. Retrieved May 29 2022 from https:\/\/www.exascaleproject.org\/."},{"key":"e_1_3_2_18_2","unstructured":"Fujitsu Post-K. 2019. Fujitsu Begins Production of Post-K. Retrieved December 15 2022 from https:\/\/www.fujitsu.com\/global\/about\/resources\/news\/press-releases\/2019\/0415-01.html."},{"key":"e_1_3_2_19_2","first-page":"3","volume-title":"CCF Transactions on High Performance Computing","author":"Gagliardi Fabrizio","year":"2019","unstructured":"Fabrizio Gagliardi, Miquel Moreto, Mauro Olivieri, and Mateo Valero. 2019. The international race towards Exascale in Europe. CCF Transactions on High Performance Computing 1 (2019), 3\u201313."},{"key":"e_1_3_2_20_2","unstructured":"GREEN500 List. 2022. GREEN500 List\u2014June 2022. Retrieved December 15 2022 from https:\/\/www.top500.org\/lists\/green500\/2022\/06\/."},{"key":"e_1_3_2_21_2","unstructured":"Jonathan Koomey. 2016. Our Latest on Energy Efficiency of Computing over Time Now Out in Electronic Design. Retrieved December 15 2022 from https:\/\/www.koomey.com\/post\/153838038643."},{"key":"e_1_3_2_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2014.6942056"},{"key":"e_1_3_2_23_2","doi-asserted-by":"crossref","unstructured":"Y. Lu. 2019. Paving the way for China exascale computing. CCF Transactions on High Performance Computing 1 (2019) 63\u201372.","DOI":"10.1007\/s42514-019-00010-y"},{"key":"e_1_3_2_24_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2950087"},{"key":"e_1_3_2_25_2","unstructured":"Kim McMahon. 2022. Intel Corporation Makes Deep Investment in RISC-V Community to Accelerate Innovation in Open Computing. Retrieved May 30 2022 from https:\/\/riscv.org\/blog\/2022\/02\/intel-corporation-makes-deep-investment-in-risc-v-community-to-accelerate-innovation-in-open-computing."},{"key":"e_1_3_2_26_2","unstructured":"Sebastian Moss. 2018. Fujitsu Reveals Specs of A64FX Its Post-K Supercomputer CPU. Retrieved December 15 2022 from https:\/\/www.datacenterdynamics.com\/en\/news\/fujitsu-reveals-specs-a64fx-its-post-k-supercomputer-cpu\/."},{"key":"e_1_3_2_27_2","unstructured":"Sam Naffziger and Jonathan Koomey. 2016. Energy Efficiency of Computing: What\u2019s Next? Retrieved December 15 2022 from https:\/\/www.electronicdesign.com\/technologies\/microprocessors\/article\/21802037\/energy-efficiency-of-computing-whats-next."},{"key":"e_1_3_2_28_2","unstructured":"NEC. 2020. SX-Aurora TSUBASA. Retrieved December 15 2022 from https:\/\/www.nec.com\/en\/global\/solutions\/hpc\/sx\/architecture.html."},{"key":"e_1_3_2_29_2","article-title":"Supercomputer Fugaku CPU A64FX realizing high performance, high-density packaging, and low power consumption","author":"Okazaki Ryohei","year":"2020","unstructured":"Ryohei Okazaki, Takekazu Tabata, Sota Sakashita, Kenichi Kitamura, Noriko Takagi, Hideki Sakata, Takeshi Ishibashi, Takeo Nakamura, and Yuichiro Ajima. 2020. Supercomputer Fugaku CPU A64FX realizing high performance, high-density packaging, and low power consumption. Fujitsu Technical Review 2020 (2020), 1\u20139.","journal-title":"Fujitsu Technical Review"},{"key":"e_1_3_2_30_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI49217.2020.000-5"},{"key":"e_1_3_2_31_2","doi-asserted-by":"publisher","DOI":"10.4230\/LIPIcs.ECRTS.2021.1"},{"key":"e_1_3_2_32_2","doi-asserted-by":"publisher","DOI":"10.1145\/3422667"},{"key":"e_1_3_2_33_2","article-title":"Neon Technology Introduction","author":"Reddy Venu Gopal","year":"2008","unstructured":"Venu Gopal Reddy. 2008. Neon Technology Introduction. ARM Corporation.","journal-title":"ARM Corporation."},{"key":"e_1_3_2_34_2","unstructured":"Antonio Regalado. 2022. MIT Technology Review: Covid Variant Tracking. Retrieved May 30 2022 from https:\/\/www.technologyreview.com\/2022\/02\/23\/1044975\/covid-19-variant-tracking-scientists\/."},{"key":"e_1_3_2_35_2","unstructured":"RISC-V V-extension. 2022. RISC-V V-extension. Retrieved May 29 2022 from https:\/\/github.com\/riscv\/riscv-v-spec."},{"key":"e_1_3_2_36_2","doi-asserted-by":"publisher","DOI":"10.1145\/359327.359336"},{"key":"e_1_3_2_37_2","unstructured":"David Schor. 2018. SX-Aurora-Microarchitectures-NEC. Retrieved December 15 2022 from https:\/\/en.wikichip.org\/wiki\/nec\/microarchitectures\/sx-aurora."},{"key":"e_1_3_2_38_2","unstructured":"GitHub. 2020. OVI: Open Vector Interface. Retrieved December 15 2022 from https:\/\/github.com\/semidynamics\/OpenVectorInterface."},{"key":"e_1_3_2_39_2","unstructured":"Semidynamics. 2021. Semidynamics High Bandwidth RISC-V IP Core Avispado. Retrieved December 15 2022 from https:\/\/semidynamics.com\/products\/avispado."},{"key":"e_1_3_2_40_2","unstructured":"SiFive. 2022. SiFive Intelligence X280. (2022). Retrieved August 21 2022 from https:\/\/www.sifive.com\/cores\/intelligence-x280."},{"key":"e_1_3_2_41_2","unstructured":"SiFive. 2022. SiFive Performance P270. Retrieved August 21 2022 from https:\/\/www.sifive.com\/cores\/performance-p270."},{"key":"e_1_3_2_42_2","unstructured":"GitHub. 2014. Spike RISC-V ISA Simulator. Retrieved May 30 2022 from https:\/\/github.com\/riscv\/riscv-isa-sim."},{"key":"e_1_3_2_43_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.35"},{"key":"e_1_3_2_44_2","unstructured":"European Processor Initiative. 2021. EPI EPAC 1.0 RISC-V Test Chip Taped-out. Retrieved December 15 2022 from https:\/\/www.european-processor-initiative.eu\/epi-epac1-0-risc-v-test-chip-taped-out\/."},{"key":"e_1_3_2_45_2","unstructured":"TOP500 List. 2022. TOP500 List\u2014June 2022. Retrieved December 15 2022 from https:\/\/www.top500.org\/lists\/top500\/2022\/06\/."},{"key":"e_1_3_2_46_2","doi-asserted-by":"publisher","DOI":"10.1145\/1479992.1480022"}],"container-title":["ACM Transactions on Architecture and Code Optimization"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3575861","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3575861","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T16:46:12Z","timestamp":1750178772000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3575861"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,3]]},"references-count":45,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2023,6,30]]}},"alternative-id":["10.1145\/3575861"],"URL":"https:\/\/doi.org\/10.1145\/3575861","relation":{},"ISSN":["1544-3566","1544-3973"],"issn-type":[{"value":"1544-3566","type":"print"},{"value":"1544-3973","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,3]]},"assertion":[{"value":"2022-05-31","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-11-10","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-03-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}