{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:47:02Z","timestamp":1772725622826,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":43,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,11,15]],"date-time":"2023-11-15T00:00:00Z","timestamp":1700006400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,11,15]]},"DOI":"10.1145\/3576915.3623124","type":"proceedings-article","created":{"date-parts":[[2023,11,21]],"date-time":"2023-11-21T12:35:13Z","timestamp":1700570113000},"page":"975-989","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["FetchBench: Systematic Identification and Characterization of Proprietary Prefetchers"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-0134-7946","authenticated-orcid":false,"given":"Till","family":"Schl\u00fcter","sequence":"first","affiliation":[{"name":"CISPA Helmholtz Center for Information Security, Saarbr\u00fccken, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5578-7061","authenticated-orcid":false,"given":"Amit","family":"Choudhari","sequence":"additional","affiliation":[{"name":"CISPA Helmholtz Center for Information Security, Saarbr\u00fccken, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-1201-0299","authenticated-orcid":false,"given":"Lorenz","family":"Hetterich","sequence":"additional","affiliation":[{"name":"CISPA Helmholtz Center for Information Security, Saarbr\u00fccken, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-6891-965X","authenticated-orcid":false,"given":"Leon","family":"Trampert","sequence":"additional","affiliation":[{"name":"CISPA Helmholtz Center for Information Security, Saarbr\u00fccken, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9251-3679","authenticated-orcid":false,"given":"Hamed","family":"Nemati","sequence":"additional","affiliation":[{"name":"CISPA Helmholtz Center for Information Security, Saarbr\u00fccken, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-6856-1871","authenticated-orcid":false,"given":"Ahmad","family":"Ibrahim","sequence":"additional","affiliation":[{"name":"Unaffiliated, Saarbr\u00fccken, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6744-3410","authenticated-orcid":false,"given":"Michael","family":"Schwarz","sequence":"additional","affiliation":[{"name":"CISPA Helmholtz Center for Information Security, Saarbr\u00fccken, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2470-8444","authenticated-orcid":false,"given":"Christian","family":"Rossow","sequence":"additional","affiliation":[{"name":"CISPA Helmholtz Center for Information Security, Saarbr\u00fccken, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8424-2602","authenticated-orcid":false,"given":"Nils Ole","family":"Tippenhauer","sequence":"additional","affiliation":[{"name":"CISPA Helmholtz Center for Information Security, Saarbr\u00fccken, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,11,21]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"Arm Ltd. 2016. ARM\u00ae Cortex\u00ae-A72 MPCore Processor Technical Reference Manual."},{"key":"e_1_3_2_1_2_1","unstructured":"Arm Ltd. 2023. TrustZone for Cortex-A. https:\/\/developer.arm.com\/Processors\/TrustZone%20for%20Cortex-A"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378498"},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"publisher","DOI":"10.1145\/125826.125932"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_2_1_6_1","volume-title":"28th USENIX Security Symposium (USENIX Security 19)","author":"Canella Claudio","year":"2019","unstructured":"Claudio Canella, Jo Van Bulck, Michael Schwarz, Moritz Lipp, Benjamin von Berg, Philipp Ortner, Frank Piessens, Dmitry Evtyushkin, and Daniel Gruss. 2019. A Systematic Evaluation of Transient Execution Attacks and Defenses. In 28th USENIX Security Symposium (USENIX Security 19) (Santa Clara (US)). USENIX Association, 19."},{"key":"e_1_3_2_1_7_1","volume-title":"Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"2","author":"Chen Yun","unstructured":"Yun Chen, Lingfeng Pei, and Trevor E. Carlson. 2023. AfterImage: Leaking Control Flow Data and Tracking Load Operations via the Hardware Prefetcher. In Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2. ACM, Vancouver BC Canada, 16--32."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2019.8741033"},{"key":"e_1_3_2_1_9_1","volume-title":"2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). 170--179","author":"Didier Guillaume","unstructured":"Guillaume Didier, Cl\u00e9mentine Maurice, Antoine Geimer, and Walid J. Ghandour. 2022. Characterizing Prefetchers using CacheObserver. In 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). 170--179."},{"key":"e_1_3_2_1_10_1","unstructured":"Electronic Frontier Foundation. 1998. Frequently Asked Questions (FAQ) About the Electronic Frontier Foundation's \"DES Cracker\" Machine. https:\/\/w2.eff.org\/Privacy\/Crypto\/Crypto_misc\/DESCracker\/HTML\/19980716_eff_des_faq.html"},{"key":"e_1_3_2_1_11_1","volume-title":"Wenisch","author":"Falsafi Babak","year":"2014","unstructured":"Babak Falsafi and Thomas F. Wenisch. 2014. A Primer on Hardware Prefetching. Number 28 in Synthesis Lectures Computer Architecture. Morgan & Claypool."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/SP46215.2023.10179399"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-11515-8_19"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/2976749.2978356"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-40667-1_14"},{"key":"e_1_3_2_1_16_1","volume-title":"Adversarial Prefetch: New Cross-Core Cache Side Channel Attacks. In IEEE Symposium on Security and Privacy (S&P)","author":"Guo Yanan","year":"2023","unstructured":"Yanan Guo, Andrew Zigerelli, Youtao Zhang, and Jun Yang. 2023. Adversarial Prefetch: New Cross-Core Cache Side Channel Attacks. In IEEE Symposium on Security and Privacy (S&P) 2022. IEEE Computer Society."},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1145\/3548606.3560613"},{"key":"e_1_3_2_1_18_1","unstructured":"Intel Corp. 2022. Guidelines for Mitigating Timing Side Channels Against Cryptographic Implementations. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/software-security-guidance\/secure-coding\/mitigate-timing-side-channel-crypto-implementation.html"},{"key":"e_1_3_2_1_19_1","unstructured":"Intel Corp. 2023. Intel\u00ae 64 and IA-32 Architectures Optimization Reference Manual."},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/264107.264207"},{"key":"e_1_3_2_1_21_1","volume-title":"Spectre Attacks: Exploiting Speculative Execution. In 40th IEEE Symposium on Security and Privacy (S&P'19)","author":"Kocher Paul","year":"2019","unstructured":"Paul Kocher, Jann Horn, Anders Fogh, and Daniel Genkin, Daniel Gruss, Werner Haas, Mike Hamburg, Moritz Lipp, Stefan Mangard, Thomas Prescher, Michael Schwarz, and Yuval Yarom. 2019. Spectre Attacks: Exploiting Speculative Execution. In 40th IEEE Symposium on Security and Privacy (S&P'19)."},{"key":"e_1_3_2_1_22_1","volume-title":"30th USENIX Security Symposium (USENIX Security 21)","author":"Lee Yoochan","year":"2021","unstructured":"Yoochan Lee, Changwoo Min, and Byoungyoung Lee. 2021. ExpRace: Exploiting Kernel Races through Raising Interrupts. In 30th USENIX Security Symposium (USENIX Security 21). USENIX Association, 2363--2380."},{"key":"e_1_3_2_1_23_1","volume-title":"31st USENIX Security Symposium (USENIX Security 22)","author":"Lipp Moritz","year":"2022","unstructured":"Moritz Lipp, Daniel Gruss, and Michael Schwarz. 2022. AMD Prefetch Attacks through Power and Time. In 31st USENIX Security Symposium (USENIX Security 22). USENIX Association, Boston, MA, 643--660."},{"key":"e_1_3_2_1_24_1","volume-title":"27th USENIX Security Symposium (USENIX Security 18)","author":"Lipp Moritz","year":"2018","unstructured":"Moritz Lipp, Michael Schwarz, Daniel Gruss, Thomas Prescher, Werner Haas, Anders Fogh, Jann Horn, Stefan Mangard, Paul Kocher, Daniel Genkin, Yuval Yarom, and Mike Hamburg. 2018. Meltdown: Reading Kernel Memory from User Space. In 27th USENIX Security Symposium (USENIX Security 18)."},{"key":"e_1_3_2_1_25_1","volume-title":"10th International Symposium on High Performance Computer Architecture (HPCA '04)","author":"Kyle","unstructured":"Kyle J. Nesbit and James E. Smith. 2004. Data Cache Prefetching Using a Global History Buffer. In 10th International Symposium on High Performance Computer Architecture (HPCA '04). 96--96."},{"key":"e_1_3_2_1_26_1","volume-title":"Cache Missing for Fun and Profit. In In Proc. of BSDCan","author":"Percival Colin","year":"2005","unstructured":"Colin Percival. 2005. Cache Missing for Fun and Profit. In In Proc. of BSDCan 2005."},{"key":"e_1_3_2_1_27_1","unstructured":"Rockchip Electronics Co. Ltd. 2021. Rockchip RK3399-T Datasheet. Revision 1.0."},{"key":"e_1_3_2_1_28_1","volume-title":"Reverse Engineering the Stream Prefetcher for Profit. In IEEE European Symposium on Security and Privacy Workshops, EuroS&P Workshops 2020","author":"Rohan Aditya","year":"2020","unstructured":"Aditya Rohan, Biswabandan Panda, and Prakhar Agarwal. 2020. Reverse Engineering the Stream Prefetcher for Profit. In IEEE European Symposium on Security and Privacy Workshops, EuroS&P Workshops 2020, Genoa, Italy, September 7-11, 2020. 682--687."},{"key":"e_1_3_2_1_29_1","volume-title":"IEEE Symposium on Security and Privacy (S&P)","author":"Sanchez Vicarte Jose Rodrigo","year":"2022","unstructured":"Jose Rodrigo Sanchez Vicarte, Michael Flanders, Riccardo Paccagnella, Grant Garrett-Grossman, Adam Morrison, Christopher W. Fletcher, and David Kohlbrenner. 2022. Augury: Using Data Memory-Dependent Prefetchers to Leak Data at Rest. In IEEE Symposium on Security and Privacy (S&P) 2022. IEEE Computer Society."},{"key":"e_1_3_2_1_30_1","volume-title":"48th ACM\/IEEE Annual International Symposium on Computer Architecture, ISCA 2021","author":"Sanchez Vicarte Jose Rodrigo","year":"2021","unstructured":"Jose Rodrigo Sanchez Vicarte, Pradyumna Shome, Nandeeka Nayak, Caroline Trippel, Adam Morrison, David Kohlbrenner, and Christopher W. Fletcher. 2021. Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture Can Leak Private Data. In 48th ACM\/IEEE Annual International Symposium on Computer Architecture, ISCA 2021, Valencia, Spain, June 14-18, 2021. 347--360."},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/339647.339666"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"publisher","DOI":"10.1145\/3243734.3243736"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/C-M.1978.218016"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555766"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.38"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.5555\/2724966.2725064"},{"key":"e_1_3_2_1_37_1","unstructured":"Krishnaswamy Viswanathan. 2014. Disclosure of Hardware Prefetcher Control on Some Intel\u00ae Processors. Intel. https:\/\/web.archive.org\/web\/20201112034737\/https:\/\/software.intel.com\/content\/www\/us\/en\/develop\/articles\/disclosure-of-hw-prefetcher-control-on-some-intel-processors.html"},{"key":"e_1_3_2_1_38_1","volume-title":"Practical Off-Chip Meta-Data for Temporal Memory Streaming. In 2009 IEEE 15th International Symposium on High Performance Computer Architecture. 79--90","author":"Wenisch Thomas F.","year":"2009","unstructured":"Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, and Andreas Moshovos. 2009. Practical Off-Chip Meta-Data for Temporal Memory Streaming. In 2009 IEEE 15th International Symposium on High Performance Computer Architecture. 79--90."},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.50"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2023.102877"},{"key":"e_1_3_2_1_41_1","volume-title":"23rd USENIX Security Symposium (USENIX Security 14)","author":"Yarom Yuval","year":"2014","unstructured":"Yuval Yarom and Katrina Falkner. 2014. FLUSH RELOAD : A High Resolution, Low Noise, L3 Cache Side-Channel Attack. In 23rd USENIX Security Symposium (USENIX Security 14). 719--732."},{"key":"e_1_3_2_1_42_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830807"},{"key":"e_1_3_2_1_43_1","volume-title":"BunnyHop: Exploiting the Instruction Prefetcher. In 32nd USENIX Security Symposium (USENIX Security 23)","author":"Zhang Zhiyuan","year":"2023","unstructured":"Zhiyuan Zhang, Mingtian Tao, Sioli O'Connell, Chitchanok Chuengsatiansup, Daniel Genkin, and Yuval Yarom. 2023. BunnyHop: Exploiting the Instruction Prefetcher. In 32nd USENIX Security Symposium (USENIX Security 23)."}],"event":{"name":"CCS '23: ACM SIGSAC Conference on Computer and Communications Security","location":"Copenhagen Denmark","acronym":"CCS '23","sponsor":["SIGSAC ACM Special Interest Group on Security, Audit, and Control"]},"container-title":["Proceedings of the 2023 ACM SIGSAC Conference on Computer and Communications Security"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3576915.3623124","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3576915.3623124","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,21]],"date-time":"2025-08-21T01:56:27Z","timestamp":1755741387000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3576915.3623124"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,11,15]]},"references-count":43,"alternative-id":["10.1145\/3576915.3623124","10.1145\/3576915"],"URL":"https:\/\/doi.org\/10.1145\/3576915.3623124","relation":{},"subject":[],"published":{"date-parts":[[2023,11,15]]},"assertion":[{"value":"2023-11-21","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}