{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,8]],"date-time":"2026-01-08T03:46:22Z","timestamp":1767843982388,"version":"3.49.0"},"publisher-location":"New York, NY, USA","reference-count":169,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,6,17]],"date-time":"2023-06-17T00:00:00Z","timestamp":1686960000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100006785","name":"Google","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006785","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Huawei"},{"name":"Intel"},{"DOI":"10.13039\/100004318","name":"Microsoft","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004318","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100016682","name":"VMware","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100016682","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Google Security and Privacy Research Award"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,6,17]]},"DOI":"10.1145\/3579371.3589063","type":"proceedings-article","created":{"date-parts":[[2023,6,16]],"date-time":"2023-06-16T20:25:28Z","timestamp":1686947128000},"page":"1-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":50,"title":["RowPress: Amplifying Read Disturbance in Modern DRAM Chips"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0009-0849-8724","authenticated-orcid":false,"given":"Haocong","family":"Luo","sequence":"first","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5333-5726","authenticated-orcid":false,"given":"Ataberk","family":"Olgun","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9333-6077","authenticated-orcid":false,"given":"Abdullah Giray","family":"Ya\u011fl\u0131k\u00e7\u0131","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-9291-3626","authenticated-orcid":false,"given":"Yahya Can","family":"Tu\u011frul","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-3389-5064","authenticated-orcid":false,"given":"Steve","family":"Rhyner","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4475-6945","authenticated-orcid":false,"given":"Meryem Banu","family":"Cavlak","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2581-8637","authenticated-orcid":false,"given":"Jo\u00ebl","family":"Lindegger","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4029-0175","authenticated-orcid":false,"given":"Mohammad","family":"Sadrosadati","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0075-2312","authenticated-orcid":false,"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}]}],"member":"320","published-online":{"date-parts":[[2023,6,17]]},"reference":[{"key":"e_1_3_2_1_1_1","first-page":"3387286","year":"1968","unstructured":"Robert H. Dennard. Field-Effect Transistor Memory. U.S. Patent 3387286 , 1968 . Robert H. Dennard. Field-Effect Transistor Memory. U.S. Patent 3387286, 1968.","journal-title":"Robert H. Dennard. Field-Effect Transistor Memory. U.S. Patent"},{"key":"e_1_3_2_1_2_1","volume-title":"ISCA","author":"Kim Y.","year":"2014","unstructured":"Y. Kim , R. Daly , J. Kim , C. Fallin , J. H. Lee , D. Lee , C. Wilkerson , K. Lai , and O. Mutlu . Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors . In ISCA , 2014 . Y. Kim, R. Daly, J. Kim, C. Fallin, J. H. Lee, D. Lee, C. Wilkerson, K. Lai, and O. Mutlu. Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors. In ISCA, 2014."},{"key":"e_1_3_2_1_3_1","volume-title":"ISCA","author":"Kim Jeremie S.","year":"2020","unstructured":"Jeremie S. Kim , Minesh Patel , Abdullah Giray Ya\u011fl\u0131k\u00e7\u0131 , Hasan Hassan , Roknoddin Azizi , Lois Orosa , and Onur Mutlu . Revisiting RowHammer : An Experimental Analysis of Modern Devices and Mitigation Techniques . In ISCA , 2020 . Jeremie S. Kim, Minesh Patel, Abdullah Giray Ya\u011fl\u0131k\u00e7\u0131, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu. Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques. In ISCA, 2020."},{"key":"e_1_3_2_1_4_1","volume-title":"A Remote Software-Induced Fault Attack in JavaScript. arXiv:1507.06955 [cs.CR]","author":"Gruss Daniel","year":"2015","unstructured":"Daniel Gruss , Clementine Maurice , and Stefan Mangard . Rowhammer.js : A Remote Software-Induced Fault Attack in JavaScript. arXiv:1507.06955 [cs.CR] , 2015 . Daniel Gruss, Clementine Maurice, and Stefan Mangard. Rowhammer.js: A Remote Software-Induced Fault Attack in JavaScript. arXiv:1507.06955 [cs.CR], 2015."},{"key":"e_1_3_2_1_5_1","volume-title":"Electronics","author":"Fournaris Apostolos P","year":"2017","unstructured":"Apostolos P Fournaris , Lidia Pocero Fraile , and Odysseas Koufopavlou . Exploiting Hardware Vulnerabilities to Attack Embedded System Devices: A Survey of Potent Microarchitectural Attacks . Electronics , 2017 . Apostolos P Fournaris, Lidia Pocero Fraile, and Odysseas Koufopavlou. Exploiting Hardware Vulnerabilities to Attack Embedded System Devices: A Survey of Potent Microarchitectural Attacks. Electronics, 2017."},{"key":"e_1_3_2_1_6_1","volume-title":"EuroS&P","author":"Poddebniak Damian","year":"2018","unstructured":"Damian Poddebniak , Juraj Somorovsky , Sebastian Schinzel , Manfred Lochter , and Paul R\u00f6sler . Attacking Deterministic Signature Schemes using Fault Attacks . In EuroS&P , 2018 . Damian Poddebniak, Juraj Somorovsky, Sebastian Schinzel, Manfred Lochter, and Paul R\u00f6sler. Attacking Deterministic Signature Schemes using Fault Attacks. In EuroS&P, 2018."},{"key":"e_1_3_2_1_7_1","volume-title":"USENIX ATC","author":"Tatar Andrei","year":"2018","unstructured":"Andrei Tatar , Radhesh Krishnan Konoth , Elias Athanasopoulos , Cristiano Giuffrida , Herbert Bos , and Kaveh Razavi . Throwhammer : Rowhammer Attacks Over the Network and Defenses . In USENIX ATC , 2018 . Andrei Tatar, Radhesh Krishnan Konoth, Elias Athanasopoulos, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi. Throwhammer: Rowhammer Attacks Over the Network and Defenses. In USENIX ATC, 2018."},{"key":"e_1_3_2_1_8_1","volume-title":"DSD","author":"Carre Sebastien","year":"2018","unstructured":"Sebastien Carre , Matthieu Desjardins , Adrien Facon , and Sylvain Guilley . OpenSSL Bellcore's Protection Helps Fault Attack . In DSD , 2018 . Sebastien Carre, Matthieu Desjardins, Adrien Facon, and Sylvain Guilley. OpenSSL Bellcore's Protection Helps Fault Attack. In DSD, 2018."},{"key":"e_1_3_2_1_9_1","volume-title":"IVSW","author":"Barenghi Alessandro","year":"2018","unstructured":"Alessandro Barenghi , Luca Breveglieri , Niccol\u00f2 Izzo , and Gerardo Pelosi . Software-Only Reverse Engineering of Physical DRAM Mappings for Rowhammer Attacks . In IVSW , 2018 . Alessandro Barenghi, Luca Breveglieri, Niccol\u00f2 Izzo, and Gerardo Pelosi. Software-Only Reverse Engineering of Physical DRAM Mappings for Rowhammer Attacks. In IVSW, 2018."},{"key":"e_1_3_2_1_10_1","volume-title":"ASHES","author":"Zhang Zhenkai","year":"2018","unstructured":"Zhenkai Zhang , Zihao Zhan , Daniel Balasubramanian , Xenofon Koutsoukos , and Gabor Karsai . Triggering Rowhammer Hardware Faults on ARM: A Revisit . In ASHES , 2018 . Zhenkai Zhang, Zihao Zhan, Daniel Balasubramanian, Xenofon Koutsoukos, and Gabor Karsai. Triggering Rowhammer Hardware Faults on ARM: A Revisit. In ASHES, 2018."},{"key":"e_1_3_2_1_11_1","volume-title":"Fault Tolerant Architectures for Cryptography and Hardware Security","author":"Bhattacharya Sarani","year":"2018","unstructured":"Sarani Bhattacharya and Debdeep Mukhopadhyay . Advanced Fault Attacks in Software: Exploiting the Rowhammer Bug . Fault Tolerant Architectures for Cryptography and Hardware Security , 2018 . Sarani Bhattacharya and Debdeep Mukhopadhyay. Advanced Fault Attacks in Software: Exploiting the Rowhammer Bug. Fault Tolerant Architectures for Cryptography and Hardware Security, 2018."},{"key":"e_1_3_2_1_12_1","unstructured":"Mark Seaborn and Thomas Dullien. Exploiting the DRAM Rowhammer Bug to Gain Kernel Privileges. http:\/\/googleprojectzero.blogspot.com.tr\/2015\/03\/exploiting-dram-rowhammer-bug-to-gain.html 2015.  Mark Seaborn and Thomas Dullien. Exploiting the DRAM Rowhammer Bug to Gain Kernel Privileges. http:\/\/googleprojectzero.blogspot.com.tr\/2015\/03\/exploiting-dram-rowhammer-bug-to-gain.html 2015."},{"key":"e_1_3_2_1_13_1","unstructured":"SAFARI Research Group. RowHammer --- GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/rowhammer.  SAFARI Research Group. RowHammer --- GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/rowhammer."},{"key":"e_1_3_2_1_14_1","volume-title":"Black Hat","author":"Seaborn Mark","year":"2015","unstructured":"Mark Seaborn and Thomas Dullien . Exploiting the DRAM Rowhammer Bug to Gain Kernel Privileges . Black Hat , 2015 . Mark Seaborn and Thomas Dullien. Exploiting the DRAM Rowhammer Bug to Gain Kernel Privileges. Black Hat, 2015."},{"key":"e_1_3_2_1_15_1","volume-title":"CCS","author":"van der Veen Victor","year":"2016","unstructured":"Victor van der Veen , Yanick Fratantonio , Martina Lindorfer , Daniel Gruss , Clementine Maurice , Giovanni Vigna , Herbert Bos , Kaveh Razavi , and Cristiano Giuffrida . Drammer : Deterministic Rowhammer Attacks on Mobile Platforms . In CCS , 2016 . Victor van der Veen, Yanick Fratantonio, Martina Lindorfer, Daniel Gruss, Clementine Maurice, Giovanni Vigna, Herbert Bos, Kaveh Razavi, and Cristiano Giuffrida. Drammer: Deterministic Rowhammer Attacks on Mobile Platforms. In CCS, 2016."},{"key":"e_1_3_2_1_16_1","volume-title":"A Remote Software-Induced Fault Attack in Javascript. arXiv:1507.06955 [cs.CR]","author":"Gruss Daniel","year":"2016","unstructured":"Daniel Gruss , Cl\u00e9mentine Maurice , and Stefan Mangard . Rowhammer.js : A Remote Software-Induced Fault Attack in Javascript. arXiv:1507.06955 [cs.CR] , 2016 . Daniel Gruss, Cl\u00e9mentine Maurice, and Stefan Mangard. Rowhammer.js: A Remote Software-Induced Fault Attack in Javascript. arXiv:1507.06955 [cs.CR], 2016."},{"key":"e_1_3_2_1_17_1","volume-title":"USENIX Security","author":"Razavi Kaveh","year":"2016","unstructured":"Kaveh Razavi , Ben Gras , Erik Bosman , Bart Preneel , Cristiano Giuffrida , and Herbert Bos . Flip Feng Shui: Hammering a Needle in the Software Stack . In USENIX Security , 2016 . Kaveh Razavi, Ben Gras, Erik Bosman, Bart Preneel, Cristiano Giuffrida, and Herbert Bos. Flip Feng Shui: Hammering a Needle in the Software Stack. In USENIX Security, 2016."},{"key":"e_1_3_2_1_18_1","volume-title":"USENIX Security","author":"Pessl Peter","year":"2016","unstructured":"Peter Pessl , Daniel Gruss , Cl\u00e9mentine Maurice , Michael Schwarz , and Stefan Mangard . DRAMA : Exploiting DRAM Addressing for Cross-CPU Attacks . In USENIX Security , 2016 . Peter Pessl, Daniel Gruss, Cl\u00e9mentine Maurice, Michael Schwarz, and Stefan Mangard. DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks. In USENIX Security, 2016."},{"key":"e_1_3_2_1_19_1","volume-title":"One Cloud Flops: Cross-VM Row Hammer Attacks and Privilege Escalation. In USENIX Security","author":"Xiao Yuan","year":"2016","unstructured":"Yuan Xiao , Xiaokuan Zhang , Yinqian Zhang , and Radu Teodorescu . One Bit Flips , One Cloud Flops: Cross-VM Row Hammer Attacks and Privilege Escalation. In USENIX Security , 2016 . Yuan Xiao, Xiaokuan Zhang, Yinqian Zhang, and Radu Teodorescu. One Bit Flips, One Cloud Flops: Cross-VM Row Hammer Attacks and Privilege Escalation. In USENIX Security, 2016."},{"key":"e_1_3_2_1_20_1","volume-title":"S&P","author":"Bosman Erik","year":"2016","unstructured":"Erik Bosman , Kaveh Razavi , Herbert Bos , and Cristiano Giuffrida . Dedup Est Machina: Memory Deduplication as an Advanced Exploitation Vector . In S&P , 2016 . Erik Bosman, Kaveh Razavi, Herbert Bos, and Cristiano Giuffrida. Dedup Est Machina: Memory Deduplication as an Advanced Exploitation Vector. In S&P, 2016."},{"key":"e_1_3_2_1_21_1","volume-title":"CHES","author":"Bhattacharya Sarani","year":"2016","unstructured":"Sarani Bhattacharya and Debdeep Mukhopadhyay . Curious Case of Rowhammer: Flipping Secret Exponent Bits Using Timing Analysis . In CHES , 2016 . Sarani Bhattacharya and Debdeep Mukhopadhyay. Curious Case of Rowhammer: Flipping Secret Exponent Bits Using Timing Analysis. In CHES, 2016."},{"key":"e_1_3_2_1_22_1","volume-title":"DAC","author":"Burleson Wayne","year":"2016","unstructured":"Wayne Burleson , Onur Mutlu , and Mohit Tiwari . Invited : Who is the Major Threat to Tomorrow's Security? You, the Hardware Designer . In DAC , 2016 . Wayne Burleson, Onur Mutlu, and Mohit Tiwari. Invited: Who is the Major Threat to Tomorrow's Security? You, the Hardware Designer. In DAC, 2016."},{"key":"e_1_3_2_1_23_1","volume-title":"HOST","author":"Qiao Rui","year":"2016","unstructured":"Rui Qiao and Mark Seaborn . A New Approach for RowHammer Attacks . In HOST , 2016 . Rui Qiao and Mark Seaborn. A New Approach for RowHammer Attacks. In HOST, 2016."},{"key":"e_1_3_2_1_24_1","volume-title":"USENIX Security","author":"Brasser Ferdinand","year":"2017","unstructured":"Ferdinand Brasser , Lucas Davi , David Gens , Christopher Liebchen , and Ahmad-Reza Sadeghi . Can't Touch This : Software-Only Mitigation Against Rowhammer Attacks Targeting Kernel Memory . In USENIX Security , 2017 . Ferdinand Brasser, Lucas Davi, David Gens, Christopher Liebchen, and Ahmad-Reza Sadeghi. Can't Touch This: Software-Only Mitigation Against Rowhammer Attacks Targeting Kernel Memory. In USENIX Security, 2017."},{"key":"e_1_3_2_1_25_1","volume-title":"SOSP","author":"Jang Yeongjin","year":"2017","unstructured":"Yeongjin Jang , Jaehyuk Lee , Sangho Lee , and Taesoo Kim . SGX-Bomb : Locking Down the Processor via Rowhammer Attack . In SOSP , 2017 . Yeongjin Jang, Jaehyuk Lee, Sangho Lee, and Taesoo Kim. SGX-Bomb: Locking Down the Processor via Rowhammer Attack. In SOSP, 2017."},{"key":"e_1_3_2_1_26_1","volume-title":"HOST","author":"Aga Misiker Tadesse","year":"2017","unstructured":"Misiker Tadesse Aga , Zelalem Birhanu Aweke , and Todd Austin . When Good Protections Go Bad: Exploiting Anti-DoS Measures to Accelerate Rowhammer Attacks . In HOST , 2017 . Misiker Tadesse Aga, Zelalem Birhanu Aweke, and Todd Austin. When Good Protections Go Bad: Exploiting Anti-DoS Measures to Accelerate Rowhammer Attacks. In HOST, 2017."},{"key":"e_1_3_2_1_27_1","volume-title":"DATE","author":"Mutlu Onur","year":"2017","unstructured":"Onur Mutlu . The RowHammer Problem and Other Issues We May Face as Memory Becomes Denser . In DATE , 2017 . Onur Mutlu. The RowHammer Problem and Other Issues We May Face as Memory Becomes Denser. In DATE, 2017."},{"key":"e_1_3_2_1_28_1","volume-title":"RAID","author":"Tatar Andrei","year":"2018","unstructured":"Andrei Tatar , Cristiano Giuffrida , Herbert Bos , and Kaveh Razavi . Defeating Software Mitigations Against Rowhammer: A Surgical Precision Hammer . In RAID , 2018 . Andrei Tatar, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi. Defeating Software Mitigations Against Rowhammer: A Surgical Precision Hammer. In RAID, 2018."},{"key":"e_1_3_2_1_29_1","volume-title":"S&P","author":"Gruss Daniel","year":"2018","unstructured":"Daniel Gruss , Moritz Lipp , Michael Schwarz , Daniel Genkin , Jonas Juffinger , Sioli O'Connell , Wolfgang Schoechl , and Yuval Yarom . Another Flip in the Wall of Rowhammer Defenses . In S&P , 2018 . Daniel Gruss, Moritz Lipp, Michael Schwarz, Daniel Genkin, Jonas Juffinger, Sioli O'Connell, Wolfgang Schoechl, and Yuval Yarom. Another Flip in the Wall of Rowhammer Defenses. In S&P, 2018."},{"key":"e_1_3_2_1_30_1","volume-title":"Michael Schwarz, Daniel Gruss, Cl\u00e9mentine Maurice, Lukas Raab, and Lukas Lamster. Nethammer: Inducing Rowhammer Faults Through Network Requests. arXiv:1805.04956 [cs.CR]","author":"Lipp Moritz","year":"2018","unstructured":"Moritz Lipp , Misiker Tadesse Aga , Michael Schwarz, Daniel Gruss, Cl\u00e9mentine Maurice, Lukas Raab, and Lukas Lamster. Nethammer: Inducing Rowhammer Faults Through Network Requests. arXiv:1805.04956 [cs.CR] , 2018 . Moritz Lipp, Misiker Tadesse Aga, Michael Schwarz, Daniel Gruss, Cl\u00e9mentine Maurice, Lukas Raab, and Lukas Lamster. Nethammer: Inducing Rowhammer Faults Through Network Requests. arXiv:1805.04956 [cs.CR], 2018."},{"key":"e_1_3_2_1_31_1","volume-title":"DIMVA","author":"van der Veen Victor","year":"2018","unstructured":"Victor van der Veen , Martina Lindorfer , Yanick Fratantonio , Harikrishnan Padmanabha Pillai , Giovanni Vigna , Christopher Kruegel , Herbert Bos , and Kaveh Razavi . GuardION : Practical Mitigation of DMA-Based Rowhammer Attacks on ARM . In DIMVA , 2018 . Victor van der Veen, Martina Lindorfer, Yanick Fratantonio, Harikrishnan Padmanabha Pillai, Giovanni Vigna, Christopher Kruegel, Herbert Bos, and Kaveh Razavi. GuardION: Practical Mitigation of DMA-Based Rowhammer Attacks on ARM. In DIMVA, 2018."},{"key":"e_1_3_2_1_32_1","volume-title":"S&P","author":"Frigo Pietro","year":"2018","unstructured":"Pietro Frigo , Cristiano Giuffrida , Herbert Bos , and Kaveh Razavi . Grand Pwning Unit: Accelerating Microarchitectural Attacks with the GPU . In S&P , 2018 . Pietro Frigo, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi. Grand Pwning Unit: Accelerating Microarchitectural Attacks with the GPU. In S&P, 2018."},{"key":"e_1_3_2_1_33_1","volume-title":"S&P","author":"Cojocar Lucian","year":"2019","unstructured":"Lucian Cojocar , Kaveh Razavi , Cristiano Giuffrida , and Herbert Bos . Exploiting Correcting Codes: On the Effectiveness of ECC Memory Against Rowhammer Attacks . In S&P , 2019 . Lucian Cojocar, Kaveh Razavi, Cristiano Giuffrida, and Herbert Bos. Exploiting Correcting Codes: On the Effectiveness of ECC Memory Against Rowhammer Attacks. In S&P, 2019."},{"key":"e_1_3_2_1_34_1","volume-title":"ASIACCS","author":"Ji Sangwoo","year":"2019","unstructured":"Sangwoo Ji , Youngjoo Ko , Saeyoung Oh , and Jong Kim . Pinpoint Rowhammer : Suppressing Unwanted Bit Flips on Rowhammer Attacks . In ASIACCS , 2019 . Sangwoo Ji, Youngjoo Ko, Saeyoung Oh, and Jong Kim. Pinpoint Rowhammer: Suppressing Unwanted Bit Flips on Rowhammer Attacks. In ASIACCS, 2019."},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2915318"},{"key":"e_1_3_2_1_36_1","volume-title":"USENIX Security","author":"Hong Sanghyun","year":"2019","unstructured":"Sanghyun Hong , Pietro Frigo , Yi\u011fitcan Kaya , Cristiano Giuffrida , and Tudor Dumitra\u015f . Terminal Brain Damage: Exposing the Graceless Degradation in Deep Neural Networks Under Hardware Fault Attacks . In USENIX Security , 2019 . Sanghyun Hong, Pietro Frigo, Yi\u011fitcan Kaya, Cristiano Giuffrida, and Tudor Dumitra\u015f. Terminal Brain Damage: Exposing the Graceless Degradation in Deep Neural Networks Under Hardware Fault Attacks. In USENIX Security, 2019."},{"key":"e_1_3_2_1_37_1","volume-title":"S&P","author":"Kwong Andrew","year":"2020","unstructured":"Andrew Kwong , Daniel Genkin , Daniel Gruss , and Yuval Yarom . RAMBleed: Reading Bits in Memory Without Accessing Them . In S&P , 2020 . Andrew Kwong, Daniel Genkin, Daniel Gruss, and Yuval Yarom. RAMBleed: Reading Bits in Memory Without Accessing Them. In S&P, 2020."},{"key":"e_1_3_2_1_38_1","volume-title":"S&P","author":"Frigo Pietro","year":"2020","unstructured":"Pietro Frigo , Emanuele Vannacci , Hasan Hassan , Victor van der Veen , Onur Mutlu , Cristiano Giuffrida , Herbert Bos , and Kaveh Razavi . TRRespass: Exploiting the Many Sides of Target Row Refresh . In S&P , 2020 . Pietro Frigo, Emanuele Vannacci, Hasan Hassan, Victor van der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi. TRRespass: Exploiting the Many Sides of Target Row Refresh. In S&P, 2020."},{"key":"e_1_3_2_1_39_1","volume-title":"S&P","author":"Cojocar Lucian","year":"2020","unstructured":"Lucian Cojocar , Jeremie Kim , Minesh Patel , Lillian Tsai , Stefan Saroiu , Alec Wolman , and Onur Mutlu . Are We Susceptible to Rowhammer? An End-to-End Methodology for Cloud Providers . In S&P , 2020 . Lucian Cojocar, Jeremie Kim, Minesh Patel, Lillian Tsai, Stefan Saroiu, Alec Wolman, and Onur Mutlu. Are We Susceptible to Rowhammer? An End-to-End Methodology for Cloud Providers. In S&P, 2020."},{"key":"e_1_3_2_1_40_1","volume-title":"JackHammer: Efficient Rowhammer on Heterogeneous FPGA-CPU Platforms. arXiv:1912.11523 [cs.CR]","author":"Weissman Zane","year":"2020","unstructured":"Zane Weissman , Thore Tiemann , Daniel Moghimi , Evan Custodio , Thomas Eisenbarth , and Berk Sunar . JackHammer: Efficient Rowhammer on Heterogeneous FPGA-CPU Platforms. arXiv:1912.11523 [cs.CR] , 2020 . Zane Weissman, Thore Tiemann, Daniel Moghimi, Evan Custodio, Thomas Eisenbarth, and Berk Sunar. JackHammer: Efficient Rowhammer on Heterogeneous FPGA-CPU Platforms. arXiv:1912.11523 [cs.CR], 2020."},{"key":"e_1_3_2_1_41_1","volume-title":"MICRO","author":"Zhang Zhi","year":"2020","unstructured":"Zhi Zhang , Yueqiang Cheng , Dongxi Liu , Surya Nepal , Zhi Wang , and Yuval Yarom . PThammer : Cross-User-Kernel-Boundary Rowhammer through Implicit Accesses . In MICRO , 2020 . Zhi Zhang, Yueqiang Cheng, Dongxi Liu, Surya Nepal, Zhi Wang, and Yuval Yarom. PThammer: Cross-User-Kernel-Boundary Rowhammer through Implicit Accesses. In MICRO, 2020."},{"key":"e_1_3_2_1_42_1","volume-title":"USENIX Security","author":"Yao Fan","year":"2020","unstructured":"Fan Yao , Adnan Siraj Rakin , and Deliang Fan . DeepHammer : Depleting the Intelligence of Deep Neural Networks Through Targeted Chain of Bit Flips . In USENIX Security , 2020 . Fan Yao, Adnan Siraj Rakin, and Deliang Fan. DeepHammer: Depleting the Intelligence of Deep Neural Networks Through Targeted Chain of Bit Flips. In USENIX Security, 2020."},{"key":"e_1_3_2_1_43_1","volume-title":"USENIX Security","author":"de Ridder Finn","year":"2021","unstructured":"Finn de Ridder , Pietro Frigo , Emanuele Vannacci , Herbert Bos , Cristiano Giuffrida , and Kaveh Razavi . SMASH : Synchronized Many-Sided Rowhammer Attacks from JavaScript . In USENIX Security , 2021 . Finn de Ridder, Pietro Frigo, Emanuele Vannacci, Herbert Bos, Cristiano Giuffrida, and Kaveh Razavi. SMASH: Synchronized Many-Sided Rowhammer Attacks from JavaScript. In USENIX Security, 2021."},{"key":"e_1_3_2_1_44_1","volume-title":"MICRO","author":"Hassan Hasan","year":"2021","unstructured":"Hasan Hassan , Yahya Can Tugrul , Jeremie S. Kim , Victor van der Veen, Kaveh Razavi, and Onur Mutlu. Uncovering in-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications . In MICRO , 2021 . Hasan Hassan, Yahya Can Tugrul, Jeremie S. Kim, Victor van der Veen, Kaveh Razavi, and Onur Mutlu. Uncovering in-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications. In MICRO, 2021."},{"key":"e_1_3_2_1_45_1","volume-title":"Blacksmith: Scalable Rowhammering in the Frequency Domain. In SP","author":"Jattke Patrick","year":"2022","unstructured":"Patrick Jattke , Victor van der Veen, Pietro Frigo, Stijn Gunter, and Kaveh Razavi . Blacksmith: Scalable Rowhammering in the Frequency Domain. In SP , 2022 . Patrick Jattke, Victor van der Veen, Pietro Frigo, Stijn Gunter, and Kaveh Razavi. Blacksmith: Scalable Rowhammering in the Frequency Domain. In SP, 2022."},{"key":"e_1_3_2_1_46_1","volume-title":"Toward Realistic Backdoor Injection Attacks on DNNs using RowHammer. arXiv:2110.07683v2 [cs.LG]","author":"Tol M Caner","year":"2022","unstructured":"M Caner Tol , Saad Islam , Berk Sunar , and Ziming Zhang . Toward Realistic Backdoor Injection Attacks on DNNs using RowHammer. arXiv:2110.07683v2 [cs.LG] , 2022 . M Caner Tol, Saad Islam, Berk Sunar, and Ziming Zhang. Toward Realistic Backdoor Injection Attacks on DNNs using RowHammer. arXiv:2110.07683v2 [cs.LG], 2022."},{"key":"e_1_3_2_1_47_1","volume-title":"USENIX Security","author":"Kogler Andreas","year":"2022","unstructured":"Andreas Kogler , Jonas Juffinger , Salman Qazi , Yoongu Kim , Moritz Lipp , Nicolas Boichat , Eric Shiu , Mattias Nissler , and Daniel Gruss . Half-Double : Hammering From the Next Row Over . In USENIX Security , 2022 . Andreas Kogler, Jonas Juffinger, Salman Qazi, Yoongu Kim, Moritz Lipp, Nicolas Boichat, Eric Shiu, Mattias Nissler, and Daniel Gruss. Half-Double: Hammering From the Next Row Over. In USENIX Security, 2022."},{"key":"e_1_3_2_1_48_1","volume-title":"SpyHammer: Using RowHammer to Remotely Spy on Temperature. arXiv:2210.04084","author":"Orosa Lois","year":"2022","unstructured":"Lois Orosa , Ulrich R\u00fchrmair , A Giray Yaglikci , Haocong Luo , Ataberk Olgun , Patrick Jattke , Minesh Patel , Jeremie Kim , Kaveh Razavi , and Onur Mutlu . SpyHammer: Using RowHammer to Remotely Spy on Temperature. arXiv:2210.04084 , 2022 . Lois Orosa, Ulrich R\u00fchrmair, A Giray Yaglikci, Haocong Luo, Ataberk Olgun, Patrick Jattke, Minesh Patel, Jeremie Kim, Kaveh Razavi, and Onur Mutlu. SpyHammer: Using RowHammer to Remotely Spy on Temperature. arXiv:2210.04084, 2022."},{"key":"e_1_3_2_1_49_1","volume-title":"Implicit Hammer: Cross-Privilege-Boundary Rowhammer through Implicit Accesses","author":"Zhang Zhi","year":"2022","unstructured":"Zhi Zhang , Wei He , Yueqiang Cheng , Wenhao Wang , Yansong Gao , Dongxi Liu , Kang Li , Surya Nepal , Anmin Fu , and Yi Zou . Implicit Hammer: Cross-Privilege-Boundary Rowhammer through Implicit Accesses . IEEE Transactions on Dependable and Secure Computing , 2022 . Zhi Zhang, Wei He, Yueqiang Cheng, Wenhao Wang, Yansong Gao, Dongxi Liu, Kang Li, Surya Nepal, Anmin Fu, and Yi Zou. Implicit Hammer: Cross-Privilege-Boundary Rowhammer through Implicit Accesses. IEEE Transactions on Dependable and Secure Computing, 2022."},{"key":"e_1_3_2_1_50_1","volume-title":"IEEE Transactions on Computers","author":"Liu Liang","year":"2022","unstructured":"Liang Liu , Yanan Guo , Yueqiang Cheng , Youtao Zhang , and Jun Yang . Generating Robust DNN with Resistance to Bit-Flip based Adversarial Weight Attack . IEEE Transactions on Computers , 2022 . Liang Liu, Yanan Guo, Yueqiang Cheng, Youtao Zhang, and Jun Yang. Generating Robust DNN with Resistance to Bit-Flip based Adversarial Weight Attack. IEEE Transactions on Computers, 2022."},{"key":"e_1_3_2_1_51_1","volume-title":"CCS","author":"Cohen Yaakov","year":"2022","unstructured":"Yaakov Cohen , Kevin Sam Tharayil , Arie Haenel , Daniel Genkin , Angelos D Keromytis , Yossi Oren , and Yuval Yarom . HammerScope : Observing DRAM Power Consumption Using Rowhammer . In CCS , 2022 . Yaakov Cohen, Kevin Sam Tharayil, Arie Haenel, Daniel Genkin, Angelos D Keromytis, Yossi Oren, and Yuval Yarom. HammerScope: Observing DRAM Power Consumption Using Rowhammer. In CCS, 2022."},{"key":"e_1_3_2_1_52_1","volume-title":"TrojViT: Trojan Insertion in Vision Transformers. arXiv:2208.13049","author":"Zheng Mengxin","year":"2022","unstructured":"Mengxin Zheng , Qian Lou , and Lei Jiang . TrojViT: Trojan Insertion in Vision Transformers. arXiv:2208.13049 , 2022 . Mengxin Zheng, Qian Lou, and Lei Jiang. TrojViT: Trojan Insertion in Vision Transformers. arXiv:2208.13049, 2022."},{"key":"e_1_3_2_1_53_1","volume-title":"CCS","author":"Jr Michael Fahr","year":"2022","unstructured":"Michael Fahr Jr , Hunter Kippen , Andrew Kwong , Thinh Dang , Jacob Lichtinger , Dana Dachman-Soled , Daniel Genkin , Alexander Nelson , Ray Perlner , Arkady Yerukhimovich , When Frodo Flips: End-to-End Key Recovery on FrodoKEM via Rowhammer . CCS , 2022 . Michael Fahr Jr, Hunter Kippen, Andrew Kwong, Thinh Dang, Jacob Lichtinger, Dana Dachman-Soled, Daniel Genkin, Alexander Nelson, Ray Perlner, Arkady Yerukhimovich, et al. When Frodo Flips: End-to-End Key Recovery on FrodoKEM via Rowhammer. CCS, 2022."},{"key":"e_1_3_2_1_54_1","volume-title":"SpecHammer: Combining Spectre and Rowhammer for New Speculative Attacks. In SP","author":"Tobah Youssef","year":"2022","unstructured":"Youssef Tobah , Andrew Kwong , Ingab Kang , Daniel Genkin , and Kang G . Shin . SpecHammer: Combining Spectre and Rowhammer for New Speculative Attacks. In SP , 2022 . Youssef Tobah, Andrew Kwong, Ingab Kang, Daniel Genkin, and Kang G. Shin. SpecHammer: Combining Spectre and Rowhammer for New Speculative Attacks. In SP, 2022."},{"key":"e_1_3_2_1_55_1","volume-title":"Fan Yao, and Deliang Fan. DeepSteal: Advanced Model Extractions Leveraging Efficient Weight Stealing in Memories. In SP","author":"Rakin Adnan Siraj","year":"2022","unstructured":"Adnan Siraj Rakin , Md Hafizul Islam Chowdhuryy , Fan Yao, and Deliang Fan. DeepSteal: Advanced Model Extractions Leveraging Efficient Weight Stealing in Memories. In SP , 2022 . Adnan Siraj Rakin, Md Hafizul Islam Chowdhuryy, Fan Yao, and Deliang Fan. DeepSteal: Advanced Model Extractions Leveraging Efficient Weight Stealing in Memories. In SP, 2022."},{"key":"e_1_3_2_1_56_1","volume-title":"Apparatus and methods for refreshing memory. U.S. Patent 11062754B2","author":"Ito Yutaka","year":"2019","unstructured":"Yutaka Ito and Yuan He . Apparatus and methods for refreshing memory. U.S. Patent 11062754B2 , 2019 . Yutaka Ito and Yuan He. Apparatus and methods for refreshing memory. U.S. Patent 11062754B2, 2019."},{"key":"e_1_3_2_1_57_1","volume-title":"Word line cache mode. U.S. Patent 10366733B1","author":"Wolff Gregg D.","year":"2019","unstructured":"Gregg D. Wolff . Word line cache mode. U.S. Patent 10366733B1 , 2019 . Gregg D. Wolff. Word line cache mode. U.S. Patent 10366733B1, 2019."},{"key":"e_1_3_2_1_58_1","volume-title":"Dsac: Low-cost rowhammer mitigation using in-dram stochastic and approximate counting algorithm. arXiv:2302.03591","author":"Hong Seungki","year":"2023","unstructured":"Seungki Hong , Dongha Kim , Jaehyung Lee , Reum Oh , Changsik Yoo , Sangjoon Hwang , and Jooyoung Lee . Dsac: Low-cost rowhammer mitigation using in-dram stochastic and approximate counting algorithm. arXiv:2302.03591 , 2023 . Seungki Hong, Dongha Kim, Jaehyung Lee, Reum Oh, Changsik Yoo, Sangjoon Hwang, and Jooyoung Lee. Dsac: Low-cost rowhammer mitigation using in-dram stochastic and approximate counting algorithm. arXiv:2302.03591, 2023."},{"key":"e_1_3_2_1_59_1","volume-title":"JESD79-4C: DDR4 SDRAM Standard","author":"JEDEC.","year":"2020","unstructured":"JEDEC. JESD79-4C: DDR4 SDRAM Standard , 2020 . JEDEC. JESD79-4C: DDR4 SDRAM Standard, 2020."},{"key":"e_1_3_2_1_60_1","volume-title":"Lois Orosa, Haocong Luo, Minesh Patel, Oguz Ergin, and Onur Mutlu. DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips. arXiv:2211.05838","author":"Olgun Ataberk","year":"2022","unstructured":"Ataberk Olgun , Hasan Hassan , A. Giray Yaglikci , Yahya Can Tugrul , Lois Orosa, Haocong Luo, Minesh Patel, Oguz Ergin, and Onur Mutlu. DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips. arXiv:2211.05838 , 2022 . Ataberk Olgun, Hasan Hassan, A. Giray Yaglikci, Yahya Can Tugrul, Lois Orosa, Haocong Luo, Minesh Patel, Oguz Ergin, and Onur Mutlu. DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips. arXiv:2211.05838, 2022."},{"key":"e_1_3_2_1_61_1","volume-title":"JESD79-3: DDR3 SDRAM Standard","author":"JEDEC.","year":"2012","unstructured":"JEDEC. JESD79-3: DDR3 SDRAM Standard , 2012 . JEDEC. JESD79-3: DDR3 SDRAM Standard, 2012."},{"key":"e_1_3_2_1_62_1","volume-title":"EDL","author":"Yang Thomas","year":"2019","unstructured":"Thomas Yang and Xi-Wei Lin . Trap-Assisted DRAM Row Hammer Effect . EDL , 2019 . Thomas Yang and Xi-Wei Lin. Trap-Assisted DRAM Row Hammer Effect. EDL, 2019."},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2021.3060362"},{"key":"e_1_3_2_1_64_1","volume-title":"Microelectronics Reliability","author":"Park Kyungbae","year":"2016","unstructured":"Kyungbae Park , Chulseung Lim , Donghyuk Yun , and Sanghyeon Baeg . Experiments and Root Cause Analysis for Active-Precharge Hammering Fault in DDR3 SDRAM under 3xnm Technology . Microelectronics Reliability , 2016 . Kyungbae Park, Chulseung Lim, Donghyuk Yun, and Sanghyeon Baeg. Experiments and Root Cause Analysis for Active-Precharge Hammering Fault in DDR3 SDRAM under 3xnm Technology. Microelectronics Reliability, 2016."},{"key":"e_1_3_2_1_65_1","volume-title":"Microelectronics Reliability","author":"Park Kyungbae","year":"2016","unstructured":"Kyungbae Park , Donghyuk Yun , and Sanghyeon Baeg . Statistical Distributions of Row-Hammering Induced Failures in DDR3 Components . Microelectronics Reliability , 2016 . Kyungbae Park, Donghyuk Yun, and Sanghyeon Baeg. Statistical Distributions of Row-Hammering Induced Failures in DDR3 Components. Microelectronics Reliability, 2016."},{"key":"e_1_3_2_1_66_1","volume-title":"DSN","author":"Ya\u011fl\u0131k\u00e7\u0131 A Giray","year":"2022","unstructured":"A Giray Ya\u011fl\u0131k\u00e7\u0131 , Haocong Luo , Geraldo Francisco Oliveira , Ataberk Olgun , Minesh Patel , Jisung Park , Hasan Hassan , Jeremie S. Kim , Lois Orosa , and Onur Mutlu . Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices . In DSN , 2022 . A Giray Ya\u011fl\u0131k\u00e7\u0131, Haocong Luo, Geraldo Francisco Oliveira, Ataberk Olgun, Minesh Patel, Jisung Park, Hasan Hassan, Jeremie S. Kim, Lois Orosa, and Onur Mutlu. Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices. In DSN, 2022."},{"key":"e_1_3_2_1_67_1","volume-title":"ASP-DAC","author":"Mutlu Onur","year":"2023","unstructured":"Onur Mutlu , Ataberk Olgun , and A. Giray Ya\u011fl\u0131k\u00e7\u0131 . Fundamentally Understanding and Solving RowHammer . In ASP-DAC , 2023 . Onur Mutlu, Ataberk Olgun, and A. Giray Ya\u011fl\u0131k\u00e7\u0131. Fundamentally Understanding and Solving RowHammer. In ASP-DAC, 2023."},{"key":"e_1_3_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00014"},{"key":"e_1_3_2_1_69_1","unstructured":"SAFARI Research Group. RowPress Artifact --- GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/RowPress.  SAFARI Research Group. RowPress Artifact --- GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/RowPress."},{"key":"e_1_3_2_1_70_1","volume-title":"JESD209-4B: Low Power Double Data Rate 4 (LPDDR4) Standard","author":"JEDEC.","year":"2017","unstructured":"JEDEC. JESD209-4B: Low Power Double Data Rate 4 (LPDDR4) Standard , 2017 . JEDEC. JESD209-4B: Low Power Double Data Rate 4 (LPDDR4) Standard, 2017."},{"key":"e_1_3_2_1_71_1","volume-title":"JESD79-5: DDR5 SDRAM Standard","author":"JEDEC.","year":"2020","unstructured":"JEDEC. JESD79-5: DDR5 SDRAM Standard , 2020 . JEDEC. JESD79-5: DDR5 SDRAM Standard, 2020."},{"key":"e_1_3_2_1_72_1","volume-title":"ISCA","author":"Mutlu Onur","year":"2008","unstructured":"Onur Mutlu and Thomas Moscibroda . Parallelism-Aware Batch Scheduling: Enhancing Both Performance and Fairness of Shared DRAM Systems . In ISCA , 2008 . Onur Mutlu and Thomas Moscibroda. Parallelism-Aware Batch Scheduling: Enhancing Both Performance and Fairness of Shared DRAM Systems. In ISCA, 2008."},{"key":"e_1_3_2_1_73_1","volume-title":"Memory Access Scheduling. In ISCA","author":"Rixner Scott","year":"2000","unstructured":"Scott Rixner , William J. Dally , Ujval J. Kapasi , Peter Mattson , and John D . Owens . Memory Access Scheduling. In ISCA , 2000 . Scott Rixner, William J. Dally, Ujval J. Kapasi, Peter Mattson, and John D. Owens. Memory Access Scheduling. In ISCA, 2000."},{"key":"e_1_3_2_1_74_1","first-page":"5630096","author":"Zuravleff William K","year":"1997","unstructured":"William K Zuravleff and Timothy Robinson . Controller for a Synchronous DRAM That Maximizes Throughput by Allowing Memory Requests and Commands to Be Issued Out of Order. U.S. Patent 5630096 , 1997 . William K Zuravleff and Timothy Robinson. Controller for a Synchronous DRAM That Maximizes Throughput by Allowing Memory Requests and Commands to Be Issued Out of Order. U.S. Patent 5630096, 1997.","journal-title":"Be Issued Out of Order. U.S. Patent"},{"key":"e_1_3_2_1_75_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.40"},{"key":"e_1_3_2_1_76_1","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.853449"},{"key":"e_1_3_2_1_77_1","author":"May T.C.","year":"1979","unstructured":"T.C. May and M.H. Woods . Alpha-particle-induced soft errors in dynamic memories. In IEEE Transactions on Electron Devices , 1979 . T.C. May and M.H. Woods. Alpha-particle-induced soft errors in dynamic memories. In IEEE Transactions on Electron Devices, 1979.","journal-title":"Alpha-particle-induced soft errors in dynamic memories. In IEEE Transactions on Electron Devices"},{"key":"e_1_3_2_1_78_1","volume-title":"IEEE Transactions on Reliability","author":"Lantz L.","year":"1996","unstructured":"L. Lantz . Soft errors induced by alpha particles . In IEEE Transactions on Reliability , 1996 . L. Lantz. Soft errors induced by alpha particles. In IEEE Transactions on Reliability, 1996."},{"key":"e_1_3_2_1_79_1","volume-title":"The effect of cosmic rays on the soft error rate of a DRAM at ground level","author":"J.","year":"1994","unstructured":"T. J. O'Gorman . In The effect of cosmic rays on the soft error rate of a DRAM at ground level , 1994 . T.J. O'Gorman. In The effect of cosmic rays on the soft error rate of a DRAM at ground level, 1994."},{"key":"e_1_3_2_1_80_1","volume-title":"ISCA","author":"Liu Jamie","year":"2012","unstructured":"Jamie Liu , Ben Jaiyen , Richard Veras , and Onur Mutlu . RAIDR : Retention-Aware Intelligent DRAM Refresh . In ISCA , 2012 . Jamie Liu, Ben Jaiyen, Richard Veras, and Onur Mutlu. RAIDR: Retention-Aware Intelligent DRAM Refresh. In ISCA, 2012."},{"key":"e_1_3_2_1_81_1","volume-title":"ISCA","author":"Liu Jamie","year":"2013","unstructured":"Jamie Liu , Ben Jaiyen , Yoongu Kim , Chris Wilkerson , Onur Mutlu , J Liu , B Jaiyen , Y Kim , C Wilkerson , and O Mutlu . An Experimental Study of Data Retention Behavior in Modern DRAM Devices . In ISCA , 2013 . Jamie Liu, Ben Jaiyen, Yoongu Kim, Chris Wilkerson, Onur Mutlu, J Liu, B Jaiyen, Y Kim, C Wilkerson, and O Mutlu. An Experimental Study of Data Retention Behavior in Modern DRAM Devices. In ISCA, 2013."},{"key":"e_1_3_2_1_82_1","volume-title":"ISCA","author":"Patel Minesh","year":"2017","unstructured":"Minesh Patel , Jeremie S Kim , and Onur Mutlu . The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions . In ISCA , 2017 . Minesh Patel, Jeremie S Kim, and Onur Mutlu. The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions. In ISCA, 2017."},{"key":"e_1_3_2_1_83_1","doi-asserted-by":"publisher","DOI":"10.1145\/2591971.2592000"},{"key":"e_1_3_2_1_84_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2016.30"},{"key":"e_1_3_2_1_85_1","volume-title":"TNS","author":"Lim Chulseung","year":"2017","unstructured":"Chulseung Lim , Kyungbae Park , and Sanghyeon Baeg . Active Precharge Hammering to Monitor Displacement Damage Using High-Energy Protons in 3x-nm SDRAM . TNS , 2017 . Chulseung Lim, Kyungbae Park, and Sanghyeon Baeg. Active Precharge Hammering to Monitor Displacement Damage Using High-Energy Protons in 3x-nm SDRAM. TNS, 2017."},{"key":"e_1_3_2_1_86_1","volume-title":"IEDM","author":"Ryu Seong-Wan","year":"2017","unstructured":"Seong-Wan Ryu , Kyungkyu Min , Jungho Shin , Heimi Kwon , Donghoon Nam , Taekyung Oh , Tae-Su Jang , Minsoo Yoo , Yongtaik Kim , and Sungjoo Hong . Overcoming the Reliability Limitation in the Ultimately Scaled DRAM using Silicon Migration Technique by Hydrogen Annealing . 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Rowhammer for Spin Torque based Memory: Problem or not ? In INTERMAG , 2018 . S. Agarwal, H. Dixit, D. Datta, M. Tran, D. Houssameddine, D. Shum, and F. Benistant. Rowhammer for Spin Torque based Memory: Problem or not? In INTERMAG, 2018."},{"key":"e_1_3_2_1_91_1","volume-title":"IRPS","author":"Li Haitong","year":"2014","unstructured":"Haitong Li , Hong-Yu Chen , Zhe Chen , Bing Chen , Rui Liu , Gang Qiu , Peng Huang , Feifei Zhang , Zizhen Jiang , Bin Gao , Lifeng Liu , Xiaoyan Liu , Shimeng Yu , H.-S. Philip Wong , and Jinfeng Kang . Write Disturb Analyses on Half-Selected Cells of Cross-Point RRAM Arrays . In IRPS , 2014 . Haitong Li, Hong-Yu Chen, Zhe Chen, Bing Chen, Rui Liu, Gang Qiu, Peng Huang, Feifei Zhang, Zizhen Jiang, Bin Gao, Lifeng Liu, Xiaoyan Liu, Shimeng Yu, H.-S. Philip Wong, and Jinfeng Kang. Write Disturb Analyses on Half-Selected Cells of Cross-Point RRAM Arrays. In IRPS, 2014."},{"key":"e_1_3_2_1_92_1","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2018.2872347"},{"key":"e_1_3_2_1_93_1","volume-title":"On the Reliability of FeFET On-Chip Memory. TC","author":"Genssler Paul R.","year":"2022","unstructured":"Paul R. Genssler , Victor M. van Santen , J\u00f6rg Henkel , and Hussam Amrouch . On the Reliability of FeFET On-Chip Memory. TC , 2022 . Paul R. Genssler, Victor M. van Santen, J\u00f6rg Henkel, and Hussam Amrouch. On the Reliability of FeFET On-Chip Memory. TC, 2022."},{"key":"e_1_3_2_1_94_1","volume-title":"Xilinx Alveo U200 FPGA Board. https:\/\/www.xilinx.com\/products\/boards-and-kits\/alveo\/u200.html","year":"2021","unstructured":"Xilinx. Xilinx Alveo U200 FPGA Board. https:\/\/www.xilinx.com\/products\/boards-and-kits\/alveo\/u200.html , 2021 . Xilinx. Xilinx Alveo U200 FPGA Board. https:\/\/www.xilinx.com\/products\/boards-and-kits\/alveo\/u200.html, 2021."},{"key":"e_1_3_2_1_95_1","unstructured":"SAFARI Research Group. DRAM Bender --- GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/DRAM-Bender.  SAFARI Research Group. DRAM Bender --- GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/DRAM-Bender."},{"key":"e_1_3_2_1_96_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.62"},{"key":"e_1_3_2_1_97_1","unstructured":"SAFARI Research Group. SoftMC --- GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/softmc.  SAFARI Research Group. SoftMC --- GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/softmc."},{"key":"e_1_3_2_1_98_1","unstructured":"Maxwell. FT20X. https:\/\/www.maxwell-fa.com\/upload\/files\/base\/8\/m\/311.pdf.  Maxwell. FT20X. https:\/\/www.maxwell-fa.com\/upload\/files\/base\/8\/m\/311.pdf."},{"key":"e_1_3_2_1_99_1","volume-title":"Steve Rhyner, Meryem Banu Cavlak, Jo\u00ebl Lindegger, Mohammad Sadrosadati, and Onur Mutlu","author":"Luo Haocong","year":"2023","unstructured":"Haocong Luo , Ataberk Olgun , A. Giray Ya\u011fl\u0131k\u00e7\u0131 , Yahya Can Tu\u011frul , Steve Rhyner, Meryem Banu Cavlak, Jo\u00ebl Lindegger, Mohammad Sadrosadati, and Onur Mutlu . RowPress: Amplifying Read Disturbance in Modern DRAM Chips . arXiv, 2023 . Haocong Luo, Ataberk Olgun, A. Giray Ya\u011fl\u0131k\u00e7\u0131, Yahya Can Tu\u011frul, Steve Rhyner, Meryem Banu Cavlak, Jo\u00ebl Lindegger, Mohammad Sadrosadati, and Onur Mutlu. RowPress: Amplifying Read Disturbance in Modern DRAM Chips. arXiv, 2023."},{"key":"e_1_3_2_1_100_1","volume-title":"JSSC","author":"Smith Robert T.","year":"1981","unstructured":"Robert T. Smith , James D. Chlipala , John F. M. Bindels , Roy G. Nelson , Frederick H. Fischer , and Thomas F. Mantz . Laser Programmable Redundancy and Yield Improvement in a 64K DRAM . JSSC , 1981 . Robert T. Smith, James D. Chlipala, John F. M. Bindels, Roy G. Nelson, Frederick H. Fischer, and Thomas F. Mantz. Laser Programmable Redundancy and Yield Improvement in a 64K DRAM. JSSC, 1981."},{"key":"e_1_3_2_1_101_1","volume-title":"ISIS","author":"Horiguchi Masashi","year":"1997","unstructured":"Masashi Horiguchi . Redundancy Techniques for High-Density DRAMs . In ISIS , 1997 . Masashi Horiguchi. Redundancy Techniques for High-Density DRAMs. In ISIS, 1997."},{"key":"e_1_3_2_1_102_1","volume-title":"DRAM Circuit Design: A Tutorial","author":"Keeth B.","year":"2001","unstructured":"B. Keeth and R.J. Baker . DRAM Circuit Design: A Tutorial . Wiley , 2001 . B. Keeth and R.J. Baker. DRAM Circuit Design: A Tutorial. Wiley, 2001."},{"key":"e_1_3_2_1_103_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-04478-0"},{"key":"e_1_3_2_1_104_1","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830820"},{"key":"e_1_3_2_1_105_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123945"},{"key":"e_1_3_2_1_106_1","doi-asserted-by":"publisher","DOI":"10.1145\/3078505.3078533"},{"key":"e_1_3_2_1_107_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00034"},{"key":"e_1_3_2_1_108_1","volume-title":"DELTA","author":"van de Goor A.J.","year":"2002","unstructured":"A.J. van de Goor and I. Schanstra . Address and Data Scrambling: Causes and Impact on Memory Tests . In DELTA , 2002 . A.J. van de Goor and I. Schanstra. Address and Data Scrambling: Causes and Impact on Memory Tests. In DELTA, 2002."},{"key":"e_1_3_2_1_109_1","doi-asserted-by":"publisher","DOI":"10.1109\/IIRW.2014.7049516"},{"key":"e_1_3_2_1_110_1","volume-title":"linux 5.4.0-131.147 source package in Ubuntu. https:\/\/launchpad.net\/ubuntu\/+source\/linux\/5.4.0-131.147","year":"2022","unstructured":"Launchpad. linux 5.4.0-131.147 source package in Ubuntu. https:\/\/launchpad.net\/ubuntu\/+source\/linux\/5.4.0-131.147 , 2022 . Launchpad. linux 5.4.0-131.147 source package in Ubuntu. https:\/\/launchpad.net\/ubuntu\/+source\/linux\/5.4.0-131.147, 2022."},{"key":"e_1_3_2_1_111_1","unstructured":"Intel. Intel Core i5-10400 Processor. https:\/\/ark.intel.com\/content\/www\/us\/en\/ark\/products\/199271\/intel-core-i510400-processor-12m-cache-up-to-4-30-ghz.html.  Intel. Intel Core i5-10400 Processor. https:\/\/ark.intel.com\/content\/www\/us\/en\/ark\/products\/199271\/intel-core-i510400-processor-12m-cache-up-to-4-30-ghz.html."},{"key":"e_1_3_2_1_112_1","unstructured":"Samsung Electronics. 288pin Unbuffered DIMM based on 8Gb C-die. https:\/\/download.semiconductor.samsung.com\/resources\/data-sheet\/DDR4_8Gb_C_die_Unbuffered_DIMM_Rev1.4_Apr.18.pdf.  Samsung Electronics. 288pin Unbuffered DIMM based on 8Gb C-die. https:\/\/download.semiconductor.samsung.com\/resources\/data-sheet\/DDR4_8Gb_C_die_Unbuffered_DIMM_Rev1.4_Apr.18.pdf."},{"key":"e_1_3_2_1_113_1","volume-title":"Summary of Hugetlbpage Support. https:\/\/www.kernel.org\/doc\/Documentation\/vm\/hugetlbpage.txt","author":"Kernel Archives The Linux","year":"2022","unstructured":"The Linux Kernel Archives . Summary of Hugetlbpage Support. https:\/\/www.kernel.org\/doc\/Documentation\/vm\/hugetlbpage.txt , 2022 . The Linux Kernel Archives. Summary of Hugetlbpage Support. https:\/\/www.kernel.org\/doc\/Documentation\/vm\/hugetlbpage.txt, 2022."},{"key":"e_1_3_2_1_114_1","unstructured":"Intel. Intel 64 and IA-32 Architectures Software Developer's Manual - Combined Volumes: 1 2A 2B 2C 2D 3A 3B 3C 3D and 4. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/intel-sdm.html 2022.  Intel. Intel 64 and IA-32 Architectures Software Developer's Manual - Combined Volumes: 1 2A 2B 2C 2D 3A 3B 3C 3D and 4. https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/intel-sdm.html 2022."},{"key":"e_1_3_2_1_115_1","volume-title":"Adaptive page management. U.S. Patent 7076617B2","author":"Dodd James M.","year":"2005","unstructured":"James M. Dodd . Adaptive page management. U.S. Patent 7076617B2 , 2005 . James M. Dodd. Adaptive page management. U.S. Patent 7076617B2, 2005."},{"key":"e_1_3_2_1_116_1","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2011.31"},{"key":"e_1_3_2_1_117_1","volume-title":"Method and computer system for speculatively closing","author":"Rokicki Tomas G.","year":"2002","unstructured":"Tomas G. Rokicki . Method and computer system for speculatively closing pages in memory. U.S. Patent 6389514B1, 2002 . Tomas G. Rokicki. Method and computer system for speculatively closing pages in memory. U.S. Patent 6389514B1, 2002."},{"key":"e_1_3_2_1_118_1","volume-title":"ISCAS","author":"Park S.-I.","year":"2003","unstructured":"S.-I. Park and I.-C. Park . History-based memory mode prediction for improving memory performance . In ISCAS , 2003 . S.-I. Park and I.-C. Park. History-based memory mode prediction for improving memory performance. In ISCAS, 2003."},{"key":"e_1_3_2_1_119_1","volume-title":"Method for dynamically adjusting a memory page closing policy","author":"Kahn O.","year":"2004","unstructured":"O. Kahn and J. Wilcox . Method for dynamically adjusting a memory page closing policy . 2004 . O. Kahn and J. Wilcox. Method for dynamically adjusting a memory page closing policy. 2004."},{"key":"e_1_3_2_1_120_1","volume-title":"Dynamic idle counter threshold value for use in memory paging policy","author":"Sander B.","year":"2005","unstructured":"B. Sander , P. Madrid , and G. Samus . Dynamic idle counter threshold value for use in memory paging policy . 2005 . B. Sander, P. Madrid, and G. Samus. Dynamic idle counter threshold value for use in memory paging policy. 2005."},{"key":"e_1_3_2_1_121_1","volume-title":"SAMOS","author":"Xu Y.","year":"2009","unstructured":"Y. Xu , A. Agarwal , and B. Davis . Prediction in dynamic sdram controller policies . In SAMOS , 2009 . Y. Xu, A. Agarwal, and B. Davis. Prediction in dynamic sdram controller policies. In SAMOS, 2009."},{"key":"e_1_3_2_1_122_1","volume-title":"The Bell System Technical Journal","author":"Hamming Richard W","year":"1950","unstructured":"Richard W Hamming . Error Detecting and Error Correcting Codes . The Bell System Technical Journal , 1950 . Richard W Hamming. Error Detecting and Error Correcting Codes. The Bell System Technical Journal, 1950."},{"key":"e_1_3_2_1_123_1","volume-title":"IBM Microelectronics Division","author":"Dell Timothy J","year":"1997","unstructured":"Timothy J Dell . A White Paper on the Benefits of Chipkill-Correct ECC for PC Server Main Memory . IBM Microelectronics Division , 1997 . Timothy J Dell. A White Paper on the Benefits of Chipkill-Correct ECC for PC Server Main Memory. IBM Microelectronics Division, 1997."},{"key":"e_1_3_2_1_124_1","volume-title":"Chipkill Correct Memory Architecture","author":"Locklear David","year":"2000","unstructured":"David Locklear . Chipkill Correct Memory Architecture . Dell Enterprise Systems Group , Technology Brief , 2000 . David Locklear. Chipkill Correct Memory Architecture. Dell Enterprise Systems Group, Technology Brief, 2000."},{"key":"e_1_3_2_1_125_1","unstructured":"IBM Chipkill Memory. Advanced ECC Memory for the IBM Netfinity 7000 M10. Enhancing IBM Nethnity Server Reliability.  IBM Chipkill Memory. Advanced ECC Memory for the IBM Netfinity 7000 M10. Enhancing IBM Nethnity Server Reliability."},{"key":"e_1_3_2_1_126_1","volume-title":"SC","author":"Fiala David","year":"2012","unstructured":"David Fiala , Frank Mueller , Christian Engelmann , Rolf Riesen , Kurt Ferreira , and Ron Brightwell . Detection and Correction of Silent Data Corruption for Large-Scale High-Performance Computing . In SC , 2012 . David Fiala, Frank Mueller, Christian Engelmann, Rolf Riesen, Kurt Ferreira, and Ron Brightwell. Detection and Correction of Silent Data Corruption for Large-Scale High-Performance Computing. In SC, 2012."},{"key":"e_1_3_2_1_127_1","volume-title":"ISCA","author":"Papadimitriou George","year":"2021","unstructured":"George Papadimitriou and Dimitris Gizopoulos . Demystifying the system vulnerability stack: Transient fault effects across the layers . In ISCA , 2021 . George Papadimitriou and Dimitris Gizopoulos. Demystifying the system vulnerability stack: Transient fault effects across the layers. In ISCA, 2021."},{"key":"e_1_3_2_1_128_1","volume-title":"Siva Kumar Sastry Hari, and Stephen W. Keckler. Characterizing and Mitigating Soft Errors in GPU DRAM","author":"Sullivan Michael B.","year":"2022","unstructured":"Michael B. Sullivan , Nirmal R. Saxena , Mike O'Connor , Donghyuk Lee , Paul Racunas , Saurabh Hukerikar , Timothy Tsai , Siva Kumar Sastry Hari, and Stephen W. Keckler. Characterizing and Mitigating Soft Errors in GPU DRAM . IEEE Micro , 2022 . Michael B. Sullivan, Nirmal R. Saxena, Mike O'Connor, Donghyuk Lee, Paul Racunas, Saurabh Hukerikar, Timothy Tsai, Siva Kumar Sastry Hari, and Stephen W. Keckler. Characterizing and Mitigating Soft Errors in GPU DRAM. IEEE Micro, 2022."},{"key":"e_1_3_2_1_129_1","volume-title":"DSN","author":"Tang Dong","year":"2006","unstructured":"Dong Tang , P. Carruthers , Z. Totari , and M.W. Shapiro . Assessment of the Effect of Memory Page Retirement on System RAS Against Hardware Faults . In DSN , 2006 . Dong Tang, P. Carruthers, Z. Totari, and M.W. Shapiro. Assessment of the Effect of Memory Page Retirement on System RAS Against Hardware Faults. In DSN, 2006."},{"key":"e_1_3_2_1_130_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.57"},{"key":"e_1_3_2_1_131_1","volume-title":"ISCA","author":"Seongil O.","year":"2014","unstructured":"O. Seongil , Young Hoon Son , Nam Sung Kim , and Jung Ho Ahn . Row-buffer decoupling : A case for low-latency DRAM microarchitecture . In ISCA , 2014 . O. Seongil, Young Hoon Son, Nam Sung Kim, and Jung Ho Ahn. Row-buffer decoupling: A case for low-latency DRAM microarchitecture. In ISCA, 2014."},{"key":"e_1_3_2_1_132_1","volume-title":"DAC","author":"Subramanian Lavanya","year":"2018","unstructured":"Lavanya Subramanian , Kaushik Vaidyanathan , Anant Nori , Sreenivas Subramoney , Tanay Karnik , and Hong Wang . Closed yet Open DRAM: Achieving Low Latency and High Performance in DRAM Memory Systems . In DAC , 2018 . Lavanya Subramanian, Kaushik Vaidyanathan, Anant Nori, Sreenivas Subramoney, Tanay Karnik, and Hong Wang. Closed yet Open DRAM: Achieving Low Latency and High Performance in DRAM Memory Systems. In DAC, 2018."},{"key":"e_1_3_2_1_133_1","volume-title":"Performance Evaluation Corp. SPEC CPU 2017","author":"Standard","year":"2017","unstructured":"Standard Performance Evaluation Corp. SPEC CPU 2017 . http:\/\/www.spec.org\/cpu 2017 \/. Standard Performance Evaluation Corp. SPEC CPU 2017. http:\/\/www.spec.org\/cpu2017\/."},{"key":"e_1_3_2_1_134_1","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379244"},{"key":"e_1_3_2_1_135_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.44"},{"key":"e_1_3_2_1_136_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2414456"},{"key":"e_1_3_2_1_137_1","unstructured":"SAFARI Research Group. Ramulator --- GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/ramulator.  SAFARI Research Group. Ramulator --- GitHub Repository. https:\/\/github.com\/CMU-SAFARI\/ramulator."},{"key":"e_1_3_2_1_138_1","unstructured":"Transaction Processing Performance Council. TPC-H. https:\/\/www.tpc.org\/tpch.  Transaction Processing Performance Council. TPC-H. https:\/\/www.tpc.org\/tpch."},{"key":"e_1_3_2_1_139_1","doi-asserted-by":"publisher","DOI":"10.1145\/1807128.1807152"},{"key":"e_1_3_2_1_140_1","volume-title":"HPCA","author":"Ya\u011fl\u0131k\u00e7\u0131 A Giray","year":"2021","unstructured":"A Giray Ya\u011fl\u0131k\u00e7\u0131 , Minesh Patel , Jeremie S. Kim , Roknoddin Azizibarzoki , Ataberk Olgun , Lois Orosa , Hasan Hassan , Jisung Park , Konstantinos Kanellopoullos , Taha Shahroodi , Saugata Ghose , and Onur Mutlu . BlockHammer : Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows . In HPCA , 2021 . A Giray Ya\u011fl\u0131k\u00e7\u0131, Minesh Patel, Jeremie S. Kim, Roknoddin Azizibarzoki, Ataberk Olgun, Lois Orosa, Hasan Hassan, Jisung Park, Konstantinos Kanellopoullos, Taha Shahroodi, Saugata Ghose, and Onur Mutlu. BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows. In HPCA, 2021."},{"key":"e_1_3_2_1_141_1","volume-title":"HPEC","author":"Aichinger Barbara","year":"2015","unstructured":"Barbara Aichinger . DDR Memory Errors Caused by Row Hammer . In HPEC , 2015 . Barbara Aichinger. DDR Memory Errors Caused by Row Hammer. In HPEC, 2015."},{"key":"e_1_3_2_1_142_1","volume-title":"About the Security Content of Mac EFI Security Update 2015-001. https:\/\/support.apple.com\/en-us\/HT204934","author":"Apple Inc.","year":"2015","unstructured":"Apple Inc. About the Security Content of Mac EFI Security Update 2015-001. https:\/\/support.apple.com\/en-us\/HT204934 , 2015 . Apple Inc. About the Security Content of Mac EFI Security Update 2015-001. https:\/\/support.apple.com\/en-us\/HT204934, 2015."},{"key":"e_1_3_2_1_143_1","doi-asserted-by":"publisher","DOI":"10.1145\/2872362.2872390"},{"key":"e_1_3_2_1_144_1","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2014.2332177"},{"key":"e_1_3_2_1_145_1","volume-title":"DAC","author":"Son Mungyu","year":"2017","unstructured":"Mungyu Son , Hyunsun Park , Junwhan Ahn , and Sungjoo Yoo . Making DRAM Stronger Against Row Hammering . In DAC , 2017 . Mungyu Son, Hyunsun Park, Junwhan Ahn, and Sungjoo Yoo. Making DRAM Stronger Against Row Hammering. In DAC, 2017."},{"key":"e_1_3_2_1_146_1","volume-title":"ISCA","author":"Lee Eojin","year":"2019","unstructured":"Eojin Lee , Ingab Kang , Sukhan Lee , G Edward Suh , and Jung Ho Ahn . TWiCe : Preventing Row-Hammering by Exploiting Time Window Counters . In ISCA , 2019 . Eojin Lee, Ingab Kang, Sukhan Lee, G Edward Suh, and Jung Ho Ahn. TWiCe: Preventing Row-Hammering by Exploiting Time Window Counters. In ISCA, 2019."},{"key":"e_1_3_2_1_147_1","volume-title":"DAC","author":"You Jung Min","year":"2019","unstructured":"Jung Min You and Joon-Sung Yang . MRLoc : Mitigating Row-Hammering Based on Memory Locality . In DAC , 2019 . Jung Min You and Joon-Sung Yang. MRLoc: Mitigating Row-Hammering Based on Memory Locality. In DAC, 2019."},{"key":"e_1_3_2_1_148_1","volume-title":"ISCA","author":"Seyedzadeh S. M.","year":"2018","unstructured":"S. M. Seyedzadeh , A. K. Jones , and R. Melhem . Mitigating Wordline Crosstalk Using Adaptive Trees of Counters . In ISCA , 2018 . S. M. Seyedzadeh, A. K. Jones, and R. Melhem. Mitigating Wordline Crosstalk Using Adaptive Trees of Counters. In ISCA, 2018."},{"key":"e_1_3_2_1_149_1","volume-title":"OSDI","author":"Konoth Radhesh Krishnan","year":"2018","unstructured":"Radhesh Krishnan Konoth , Marco Oliverio , Andrei Tatar , Dennis Andriesse , Herbert Bos , Cristiano Giuffrida , and Kaveh Razavi . ZebRAM : Comprehensive and Compatible Software Protection Against Rowhammer Attacks . In OSDI , 2018 . Radhesh Krishnan Konoth, Marco Oliverio, Andrei Tatar, Dennis Andriesse, Herbert Bos, Cristiano Giuffrida, and Kaveh Razavi. ZebRAM: Comprehensive and Compatible Software Protection Against Rowhammer Attacks. In OSDI, 2018."},{"key":"e_1_3_2_1_150_1","volume-title":"Time Window Optimized for DRAM Row-Hammer Prevention","author":"Kang Ingab","year":"2020","unstructured":"Ingab Kang , Eojin Lee , and Jung Ho Ahn . CAT-TWO: Counter-Based Adaptive Tree , Time Window Optimized for DRAM Row-Hammer Prevention . IEEE Access , 2020 . Ingab Kang, Eojin Lee, and Jung Ho Ahn. CAT-TWO: Counter-Based Adaptive Tree, Time Window Optimized for DRAM Row-Hammer Prevention. IEEE Access, 2020."},{"key":"e_1_3_2_1_151_1","first-page":"9117544","author":"Bains Kuljit","year":"2015","unstructured":"Kuljit Bains , John Halbert , Christopher Mozak , Theodore Schoenborn , and Zvika Greenfield. Row Hammer Refresh Command. U.S. Patent 9117544 , 2015 . Kuljit Bains, John Halbert, Christopher Mozak, Theodore Schoenborn, and Zvika Greenfield. Row Hammer Refresh Command. U.S. Patent 9117544, 2015.","journal-title":"Zvika Greenfield. Row Hammer Refresh Command. U.S. Patent"},{"key":"e_1_3_2_1_152_1","first-page":"9299400","year":"2016","unstructured":"Kuljit S Bains and John B Halbert. Distributed Row Hammer Tracking. U.S. Patent 9299400 , 2016 . Kuljit S Bains and John B Halbert. Distributed Row Hammer Tracking. U.S. Patent 9299400, 2016.","journal-title":"Kuljit S Bains and John B Halbert. Distributed Row Hammer Tracking. U.S. Patent"},{"key":"e_1_3_2_1_153_1","volume-title":"Row Hammer Monitoring Based on Stored Row Hammer Threshold Value. U.S. Patent 9384821","author":"Bains Kuljit S","year":"2016","unstructured":"Kuljit S Bains and John B Halbert . Row Hammer Monitoring Based on Stored Row Hammer Threshold Value. U.S. Patent 9384821 , 2016 . Kuljit S Bains and John B Halbert. Row Hammer Monitoring Based on Stored Row Hammer Threshold Value. U.S. Patent 9384821, 2016."},{"key":"e_1_3_2_1_154_1","volume-title":"NORCAS","author":"Gomez H.","year":"2016","unstructured":"H. Gomez , A. Amaya , and E. Roa . DRAM Row-Hammer Attack Reduction Using Dummy Cells . In NORCAS , 2016 . H. Gomez, A. Amaya, and E. Roa. DRAM Row-Hammer Attack Reduction Using Dummy Cells. In NORCAS, 2016."},{"key":"e_1_3_2_1_155_1","volume-title":"ISCA","author":"Hassan H.","year":"2019","unstructured":"H. Hassan , M. Patel , J. S. Kim , A. G. Ya\u011fl\u0131k\u00e7\u0131 , N. Vijaykumar , N. Mansouri Ghiasi , S. Ghose , and O. Mutlu . CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability . In ISCA , 2019 . H. Hassan, M. Patel, J. S. Kim, A. G. Ya\u011fl\u0131k\u00e7\u0131, N. Vijaykumar, N. Mansouri Ghiasi, S. Ghose, and O. Mutlu. CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability. In ISCA, 2019."},{"key":"e_1_3_2_1_156_1","first-page":"10885966","author":"Devaux Fabrice","year":"2021","unstructured":"Fabrice Devaux and Renaud Ayrignac . Method and Circuit for Protecting a DRAM Memory Device from the Row Hammer Effect. U.S. Patent 10885966 , 2021 . Fabrice Devaux and Renaud Ayrignac. Method and Circuit for Protecting a DRAM Memory Device from the Row Hammer Effect. U.S. Patent 10885966, 2021.","journal-title":"Row Hammer Effect. U.S. Patent"},{"key":"e_1_3_2_1_157_1","volume-title":"Yu Jing Chang, Tieh Chiang Wu, Hsiu Pin Chen, and Chao Sung Lai. Suppression of RowHammer Effect by Doping Profile Modification in Saddle-Fin Array Devices for Sub-30-nm DRAM Technology","author":"Yang Chia","year":"2016","unstructured":"Chia Yang , Chen Kang Wei , Yu Jing Chang, Tieh Chiang Wu, Hsiu Pin Chen, and Chao Sung Lai. Suppression of RowHammer Effect by Doping Profile Modification in Saddle-Fin Array Devices for Sub-30-nm DRAM Technology . IEEE Transactions on Device and Materials Reliability , 2016 . Chia Yang, Chen Kang Wei, Yu Jing Chang, Tieh Chiang Wu, Hsiu Pin Chen, and Chao Sung Lai. Suppression of RowHammer Effect by Doping Profile Modification in Saddle-Fin Array Devices for Sub-30-nm DRAM Technology. IEEE Transactions on Device and Materials Reliability, 2016."},{"key":"e_1_3_2_1_158_1","volume-title":"Tieh-Chiang Wu, and Chao-Sung Lai. Scanning Spreading Resistance Microscopy for Doping Profile in Saddle-Fin Devices","author":"Yang Chia-Ming","year":"2017","unstructured":"Chia-Ming Yang , Chen-Kang Wei , Hsiu-Pin Chen , Jian-Shing Luo , Yu Jing Chang , Tieh-Chiang Wu, and Chao-Sung Lai. Scanning Spreading Resistance Microscopy for Doping Profile in Saddle-Fin Devices . IEEE Transactions on Nanotechnology , 2017 . Chia-Ming Yang, Chen-Kang Wei, Hsiu-Pin Chen, Jian-Shing Luo, Yu Jing Chang, Tieh-Chiang Wu, and Chao-Sung Lai. Scanning Spreading Resistance Microscopy for Doping Profile in Saddle-Fin Devices. IEEE Transactions on Nanotechnology, 2017."},{"key":"e_1_3_2_1_159_1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2019.2931347"},{"key":"e_1_3_2_1_160_1","volume-title":"Security Analysis of the Silver Bullet Technique for RowHammer Prevention. arXiv:2106.07084 [cs.CR]","author":"Ya\u011fl\u0131k\u00e7\u0131 A. Giray","year":"2021","unstructured":"A. Giray Ya\u011fl\u0131k\u00e7\u0131 , Jeremie S. Kim , Fabrice Devaux , and Onur Mutlu . Security Analysis of the Silver Bullet Technique for RowHammer Prevention. arXiv:2106.07084 [cs.CR] , 2021 . A. Giray Ya\u011fl\u0131k\u00e7\u0131, Jeremie S. Kim, Fabrice Devaux, and Onur Mutlu. Security Analysis of the Silver Bullet Technique for RowHammer Prevention. arXiv:2106.07084 [cs.CR], 2021."},{"key":"e_1_3_2_1_161_1","volume-title":"DRAMSec","author":"Qureshi Moinuddin","year":"2021","unstructured":"Moinuddin Qureshi . Rethinking ECC in the Era of Row-Hammer . DRAMSec , 2021 . Moinuddin Qureshi. Rethinking ECC in the Era of Row-Hammer. DRAMSec, 2021."},{"key":"e_1_3_2_1_162_1","first-page":"9251885","year":"2016","unstructured":"Zvika Greenfield and Tomer Levy. Throttling Support for Row-Hammer Counters. U.S. Patent 9251885 , 2016 . Zvika Greenfield and Tomer Levy. Throttling Support for Row-Hammer Counters. U.S. Patent 9251885, 2016.","journal-title":"Zvika Greenfield and Tomer Levy. Throttling Support for Row-Hammer Counters. U.S. Patent"},{"key":"e_1_3_2_1_163_1","volume-title":"ASPLOS","author":"Saileshwar Gururaj","year":"2022","unstructured":"Gururaj Saileshwar , Bolin Wang , Moinuddin Qureshi , and Prashant J Nair . Randomized Row-Swap : Mitigating Row Hammer by Breaking Spatial Correlation Between Aggressor and Victim Rows . In ASPLOS , 2022 . Gururaj Saileshwar, Bolin Wang, Moinuddin Qureshi, and Prashant J Nair. Randomized Row-Swap: Mitigating Row Hammer by Breaking Spatial Correlation Between Aggressor and Victim Rows. In ASPLOS, 2022."},{"key":"e_1_3_2_1_164_1","volume-title":"ISCA","author":"Qureshi Moinuddin","year":"2022","unstructured":"Moinuddin Qureshi , Aditya Rohan , Gururaj Saileshwar , and Prashant J Nair . Hydra : Enabling Low-Overhead Mitigation of Row-Hammer at Ultra-Low Thresholds via Hybrid Tracking . In ISCA , 2022 . Moinuddin Qureshi, Aditya Rohan, Gururaj Saileshwar, and Prashant J Nair. Hydra: Enabling Low-Overhead Mitigation of Row-Hammer at Ultra-Low Thresholds via Hybrid Tracking. In ISCA, 2022."},{"key":"e_1_3_2_1_165_1","volume-title":"HPCA","author":"Wi Minbok","year":"2023","unstructured":"Minbok Wi , Jaehyun Park , Seoyoung Ko , Michael Jaemin Kim , Nam Sung Kim , Eojin Lee , and Jung Ho Ahn . SHADOW : Preventing Row Hammer in DRAM with Intra-Subarray Row Shuffling . In HPCA , 2023 . Minbok Wi, Jaehyun Park, Seoyoung Ko, Michael Jaemin Kim, Nam Sung Kim, Eojin Lee, and Jung Ho Ahn. SHADOW: Preventing Row Hammer in DRAM with Intra-Subarray Row Shuffling. In HPCA, 2023."},{"key":"e_1_3_2_1_166_1","volume-title":"Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems. In HPCA","author":"Woo Jeonghyun","year":"2023","unstructured":"Jeonghyun Woo , Gururaj Saileshwar , and Prashant J . Nair . Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems. In HPCA , 2023 . Jeonghyun Woo, Gururaj Saileshwar, and Prashant J. Nair. Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems. In HPCA, 2023."},{"key":"e_1_3_2_1_167_1","volume-title":"S&P","author":"Marazzi Michele","year":"2022","unstructured":"Michele Marazzi , Patrick Jattke , Flavien Solt , and Kaveh Razavi . ProTRR: Principled yet Optimal In-DRAM Target Row Refresh . In S&P , 2022 . Michele Marazzi, Patrick Jattke, Flavien Solt, and Kaveh Razavi. ProTRR: Principled yet Optimal In-DRAM Target Row Refresh. In S&P, 2022."},{"key":"e_1_3_2_1_168_1","volume-title":"S&P","author":"Marazzi Michele","year":"2023","unstructured":"Michele Marazzi , Flavien Solt , Patrick Jattke , Kubo Takashi , and Kaveh Razavi . REGA: Scalable Rowhammer Mitigation with Refresh-Generating Activations . In S&P , 2023 . Michele Marazzi, Flavien Solt, Patrick Jattke, Kubo Takashi, and Kaveh Razavi. REGA: Scalable Rowhammer Mitigation with Refresh-Generating Activations. In S&P, 2023."},{"key":"e_1_3_2_1_169_1","doi-asserted-by":"publisher","DOI":"10.5281\/zenodo.7750890"}],"event":{"name":"ISCA '23: 50th Annual International Symposium on Computer Architecture","location":"Orlando FL USA","acronym":"ISCA '23","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE"]},"container-title":["Proceedings of the 50th Annual International Symposium on Computer Architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3579371.3589063","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T16:46:39Z","timestamp":1750178799000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3579371.3589063"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,6,17]]},"references-count":169,"alternative-id":["10.1145\/3579371.3589063","10.1145\/3579371"],"URL":"https:\/\/doi.org\/10.1145\/3579371.3589063","relation":{},"subject":[],"published":{"date-parts":[[2023,6,17]]},"assertion":[{"value":"2023-06-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}