{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,29]],"date-time":"2026-04-29T18:10:14Z","timestamp":1777486214150,"version":"3.51.4"},"publisher-location":"New York, NY, USA","reference-count":162,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,6,17]],"date-time":"2023-06-17T00:00:00Z","timestamp":1686960000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"Google"},{"DOI":"10.13039\/100006785","name":"Huawei","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100006785","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Intel"},{"name":"Microsoft"},{"DOI":"10.13039\/100004318","name":"VMware","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004318","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100016682","name":"The Semiconductor Research Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100016682","id-type":"DOI","asserted-by":"publisher"}]},{"name":"The Swiss National Science Foundation","award":["200021_213084"],"award-info":[{"award-number":["200021_213084"]}]},{"name":"ETH Future Computing Laboratory"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,6,17]]},"DOI":"10.1145\/3579371.3589071","type":"proceedings-article","created":{"date-parts":[[2023,6,16]],"date-time":"2023-06-16T20:25:28Z","timestamp":1686947128000},"page":"1-16","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":20,"title":["Venice: Improving Solid-State Drive Parallelism at Low Cost via Conflict-Free Accesses"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4709-2323","authenticated-orcid":false,"given":"Rakesh","family":"Nadig","sequence":"first","affiliation":[{"name":"D-ITET\/SAFARI Research Group, ETH Z\u00fcrich, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4029-0175","authenticated-orcid":false,"given":"Mohammad","family":"Sadrosadati","sequence":"additional","affiliation":[{"name":"D-ITET\/SAFARI Research Group, ETH Z\u00fcrich, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7393-4504","authenticated-orcid":false,"given":"Haiyu","family":"Mao","sequence":"additional","affiliation":[{"name":"D-ITET\/SAFARI Research Group, ETH Zurich, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0833-0042","authenticated-orcid":false,"given":"Nika Mansouri","family":"Ghiasi","sequence":"additional","affiliation":[{"name":"D-ITET\/SAFARI Research Group, ETH Zurich, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3859-1259","authenticated-orcid":false,"given":"Arash","family":"Tavakkol","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1826-9003","authenticated-orcid":false,"given":"Jisung","family":"Park","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"},{"name":"POSTECH, Pohang, Gyeongsangbuk-do, Republic of Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4079-8603","authenticated-orcid":false,"given":"Hamid","family":"Sarbazi-Azad","sequence":"additional","affiliation":[{"name":"Sharif University of Technology, Tehran, Iran"},{"name":"IPM, Tehran, Iran"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6514-1571","authenticated-orcid":false,"given":"Juan G\u00f3mez","family":"Luna","sequence":"additional","affiliation":[{"name":"D-ITET\/SAFARI Research Group, ETH Zurich, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0075-2312","authenticated-orcid":false,"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[{"name":"ETH Zurich, Zurich, Switzerland"}]}],"member":"320","published-online":{"date-parts":[[2023,6,17]]},"reference":[{"key":"e_1_3_2_1_1_1","volume-title":"Concurrency, Device Architecture","author":"Dirik C.","year":"2009","unstructured":"C. Dirik and B. Jacob , \" The Performance of PC Solid-State Disks (SSDs) as a Function of Bandwidth , Concurrency, Device Architecture , and System Organization ,\" in ISCA, 2009 . C. Dirik and B. Jacob, \"The Performance of PC Solid-State Disks (SSDs) as a Function of Bandwidth, Concurrency, Device Architecture, and System Organization,\" in ISCA, 2009."},{"key":"e_1_3_2_1_2_1","volume-title":"Opportunities and Challenges,\" in SIGMOD","author":"Do J.","year":"2013","unstructured":"J. Do , Y.-S. Kee , J. M. Patel , C. Park , K. Park , and D. J. DeWitt , \" Query Processing on Smart SS Ds : Opportunities and Challenges,\" in SIGMOD , 2013 . J. Do, Y.-S. Kee, J. M. Patel, C. Park, K. Park, and D. J. DeWitt, \"Query Processing on Smart SSDs: Opportunities and Challenges,\" in SIGMOD, 2013."},{"key":"e_1_3_2_1_3_1","volume-title":"Hystor: Making the Best Use of Solid State Drives in High Performance Storage Systems,\" in ICS","author":"Chen F.","year":"2011","unstructured":"F. Chen , D. A. Koufaty , and X. Zhang , \" Hystor: Making the Best Use of Solid State Drives in High Performance Storage Systems,\" in ICS , 2011 . F. Chen, D. A. Koufaty, and X. Zhang, \"Hystor: Making the Best Use of Solid State Drives in High Performance Storage Systems,\" in ICS, 2011."},{"key":"e_1_3_2_1_4_1","volume-title":"ObliviStore: High Performance Oblivious Cloud Storage,\" in SP","author":"Stefanov E.","year":"2013","unstructured":"E. Stefanov and E. Shi , \" ObliviStore: High Performance Oblivious Cloud Storage,\" in SP , 2013 . E. Stefanov and E. Shi, \"ObliviStore: High Performance Oblivious Cloud Storage,\" in SP, 2013."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-9431-5"},{"key":"e_1_3_2_1_6_1","volume-title":"Design Tradeoffs for SSD Performance,\" in USENIX ATC","author":"Agrawal N.","year":"2008","unstructured":"N. Agrawal , V. Prabhakaran , T. Wobber , J. D. Davis , M. Manasse , and R. Panigrahy , \" Design Tradeoffs for SSD Performance,\" in USENIX ATC , 2008 . N. Agrawal, V. Prabhakaran, T. Wobber, J. D. Davis, M. Manasse, and R. Panigrahy, \"Design Tradeoffs for SSD Performance,\" in USENIX ATC, 2008."},{"key":"e_1_3_2_1_7_1","volume-title":"Design for Scalability in Enterprise SSDs,\" in PACT","author":"Tavakkol A.","year":"2014","unstructured":"A. Tavakkol , M. Arjomand , and H. Sarbazi-Azad , \" Design for Scalability in Enterprise SSDs,\" in PACT , 2014 . A. Tavakkol, M. Arjomand, and H. Sarbazi-Azad, \"Design for Scalability in Enterprise SSDs,\" in PACT, 2014."},{"key":"e_1_3_2_1_8_1","volume-title":"SSD Architecture and PCI Express Interface,\" in Inside Solid State Drives (SSDs)","author":"Eshghi K.","year":"2018","unstructured":"K. Eshghi and R. Micheloni , \" SSD Architecture and PCI Express Interface,\" in Inside Solid State Drives (SSDs) . Springer , 2018 . K. Eshghi and R. Micheloni, \"SSD Architecture and PCI Express Interface,\" in Inside Solid State Drives (SSDs). Springer, 2018."},{"key":"e_1_3_2_1_9_1","volume-title":"Exploring and Exploiting the Multilevel Parallelism Inside SSDs for Improved Performance and Endurance,\" TC","author":"Hu Y.","year":"2012","unstructured":"Y. Hu , H. Jiang , D. Feng , L. Tian , H. Luo , and C. Ren , \" Exploring and Exploiting the Multilevel Parallelism Inside SSDs for Improved Performance and Endurance,\" TC , 2012 . Y. Hu, H. Jiang, D. Feng, L. Tian, H. Luo, and C. Ren, \"Exploring and Exploiting the Multilevel Parallelism Inside SSDs for Improved Performance and Endurance,\" TC, 2012."},{"key":"e_1_3_2_1_10_1","volume-title":"Design Tradeoffs of SSDs: From Energy Consumption's Perspective,\" TOS","author":"Cho S.","year":"2015","unstructured":"S. Cho , C. Park , Y. Won , S. Kang , J. Cha , S. Yoon , and J. Choi , \" Design Tradeoffs of SSDs: From Energy Consumption's Perspective,\" TOS , 2015 . S. Cho, C. Park, Y. Won, S. Kang, J. Cha, S. Yoon, and J. Choi, \"Design Tradeoffs of SSDs: From Energy Consumption's Perspective,\" TOS, 2015."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"crossref","unstructured":"C. Gao L. Shi M. Zhao C. J. Xue K. Wu and E. H.-M. Sha \"Exploiting Parallelism in I\/O Scheduling for Access Conflict Minimization in Flash-based Solid State Drives \" in MSST 2014.  C. Gao L. Shi M. Zhao C. J. Xue K. Wu and E. H.-M. Sha \"Exploiting Parallelism in I\/O Scheduling for Access Conflict Minimization in Flash-based Solid State Drives \" in MSST 2014.","DOI":"10.1109\/MSST.2014.6855544"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","unstructured":"C. Gao L. Shi C. Ji Y. Di K. Wu C. J. Xue and E. H.-M. Sha \"Exploiting Parallelism for Access Conflict Minimization in Flash-Based Solid State Drives \" TCAD 2017.  C. Gao L. Shi C. Ji Y. Di K. Wu C. J. Xue and E. H.-M. Sha \"Exploiting Parallelism for Access Conflict Minimization in Flash-Based Solid State Drives \" TCAD 2017.","DOI":"10.1109\/TCAD.2017.2693281"},{"key":"e_1_3_2_1_13_1","volume-title":"AutoSSD: an Autonomic SSD Architecture,\" in USENIX ATC","author":"Kim B. S.","year":"2018","unstructured":"B. S. Kim , H. S. Yang , and S. L. Min , \" AutoSSD: an Autonomic SSD Architecture,\" in USENIX ATC , 2018 . B. S. Kim, H. S. Yang, and S. L. Min, \"AutoSSD: an Autonomic SSD Architecture,\" in USENIX ATC, 2018."},{"key":"e_1_3_2_1_14_1","volume-title":"Performance Evaluation of Dynamic Page Allocation Strategies in SSDs,\" TOMPECS","author":"Tavakkol A.","year":"2016","unstructured":"A. Tavakkol , P. Mehrvarzy , M. Arjomand , and H. Sarbazi-Azad , \" Performance Evaluation of Dynamic Page Allocation Strategies in SSDs,\" TOMPECS , 2016 . A. Tavakkol, P. Mehrvarzy, M. Arjomand, and H. Sarbazi-Azad, \"Performance Evaluation of Dynamic Page Allocation Strategies in SSDs,\" TOMPECS, 2016."},{"key":"e_1_3_2_1_15_1","volume-title":"Networked SSD: Flash Memory Interconnection Network for High-Bandwidth SSD,\" in MICRO","author":"Kim J.","year":"2022","unstructured":"J. Kim , S. Kang , Y. Park , and J. Kim , \" Networked SSD: Flash Memory Interconnection Network for High-Bandwidth SSD,\" in MICRO , 2022 . J. Kim, S. Kang, Y. Park, and J. Kim, \"Networked SSD: Flash Memory Interconnection Network for High-Bandwidth SSD,\" in MICRO, 2022."},{"key":"e_1_3_2_1_16_1","volume-title":"FASTer FTL for Enterprise-Class Flash Memory SSDs,\" in SNAPI","author":"Lim S.-P.","year":"2010","unstructured":"S.-P. Lim , S.-W. Lee , and B. Moon , \" FASTer FTL for Enterprise-Class Flash Memory SSDs,\" in SNAPI , 2010 . S.-P. Lim, S.-W. Lee, and B. Moon, \"FASTer FTL for Enterprise-Class Flash Memory SSDs,\" in SNAPI, 2010."},{"key":"e_1_3_2_1_17_1","volume-title":"Practical Erase Suspension for Modern Low-latency SSDs,\" in USENIX ATC","author":"Kim S.","year":"2019","unstructured":"S. Kim , J. Bae , H. Jang , W. Jin , J. Gong , S. Lee , T. J. Ham , and J. W. Lee , \" Practical Erase Suspension for Modern Low-latency SSDs,\" in USENIX ATC , 2019 . S. Kim, J. Bae, H. Jang, W. Jin, J. Gong, S. Lee, T. J. Ham, and J. W. Lee, \"Practical Erase Suspension for Modern Low-latency SSDs,\" in USENIX ATC, 2019."},{"key":"e_1_3_2_1_18_1","volume-title":"Active Disk Meets Flash: A Case for Intelligent SSDs,\" in ICS","author":"Cho S.","year":"2013","unstructured":"S. Cho , C. Park , H. Oh , S. Kim , Y. Yi , and G. R. Ganger , \" Active Disk Meets Flash: A Case for Intelligent SSDs,\" in ICS , 2013 . S. Cho, C. Park, H. Oh, S. Kim, Y. Yi, and G. R. Ganger, \"Active Disk Meets Flash: A Case for Intelligent SSDs,\" in ICS, 2013."},{"key":"e_1_3_2_1_19_1","volume-title":"Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery,\" in Inside Solid State Drives","author":"Cai Y.","year":"2018","unstructured":"Y. Cai , S. Ghose , E. F. Haratsch , Y. Luo , and O. Mutlu , \" Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery,\" in Inside Solid State Drives , 2018 . Y. Cai, S. Ghose, E. F. Haratsch, Y. Luo, and O. Mutlu, \"Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery,\" in Inside Solid State Drives, 2018."},{"key":"e_1_3_2_1_20_1","volume-title":"Data Retention in MLC NAND Flash Memory: Characterization, Optimization, and Recovery,\" in HPCA","author":"Cai Y.","year":"2015","unstructured":"Y. Cai , Y. Luo , E. F. Haratsch , K. Mai , and O. Mutlu , \" Data Retention in MLC NAND Flash Memory: Characterization, Optimization, and Recovery,\" in HPCA , 2015 . Y. Cai, Y. Luo, E. F. Haratsch, K. Mai, and O. Mutlu, \"Data Retention in MLC NAND Flash Memory: Characterization, Optimization, and Recovery,\" in HPCA, 2015."},{"key":"e_1_3_2_1_21_1","volume-title":"Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis, and Modeling,\" in DATE","author":"Cai Y.","year":"2013","unstructured":"Y. Cai , E. F. Haratsch , O. Mutlu , and K. Mai , \" Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis, and Modeling,\" in DATE , 2013 . Y. Cai, E. F. Haratsch, O. Mutlu, and K. Mai, \"Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis, and Modeling,\" in DATE, 2013."},{"key":"e_1_3_2_1_22_1","volume-title":"Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives,\" Proc","author":"Cai Y.","year":"2017","unstructured":"Y. Cai , S. Ghose , E. F. Haratsch , Y. Luo , and O. Mutlu , \" Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives,\" Proc . IEEE , 2017 . Y. Cai, S. Ghose, E. F. Haratsch, Y. Luo, and O. Mutlu, \"Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives,\" Proc. IEEE, 2017."},{"key":"e_1_3_2_1_23_1","volume-title":"FLIN: Enabling Fairness and Enhancing Performance in Modern NVMe Solid State Drives,\" in ISCA","author":"Tavakkol A.","year":"2018","unstructured":"A. Tavakkol , M. Sadrosadati , S. Ghose , J. Kim , Y. Luo , Y. Wang , N. M. Ghiasi , L. Orosa , J. G\u00f3mez-Luna , and O. Mutlu , \" FLIN: Enabling Fairness and Enhancing Performance in Modern NVMe Solid State Drives,\" in ISCA , 2018 . A. Tavakkol, M. Sadrosadati, S. Ghose, J. Kim, Y. Luo, Y. Wang, N. M. Ghiasi, L. Orosa, J. G\u00f3mez-Luna, and O. Mutlu, \"FLIN: Enabling Fairness and Enhancing Performance in Modern NVMe Solid State Drives,\" in ISCA, 2018."},{"key":"e_1_3_2_1_24_1","volume-title":"Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash Memory,\" in MICRO","author":"Park J.","year":"2022","unstructured":"J. Park , R. Azizi , G. F. Oliveira , M. Sadrosadati , R. Nadig , D. Novo , J. G\u00f3mez-Luna , M. Kim , and O. Mutlu , \" Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash Memory,\" in MICRO , 2022 . J. Park, R. Azizi, G. F. Oliveira, M. Sadrosadati, R. Nadig, D. Novo, J. G\u00f3mez-Luna, M. Kim, and O. Mutlu, \"Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash Memory,\" in MICRO, 2022."},{"key":"e_1_3_2_1_25_1","volume-title":"A Modern Primer on Processing in Memory,\" in Emerging Computing: From Devices to Systems - Looking Beyond Moore and Von Neumann","author":"Mutlu O.","year":"2021","unstructured":"O. Mutlu , S. Ghose , J. G\u00f3mez-Luna , and R. Ausavarungnirun , \" A Modern Primer on Processing in Memory,\" in Emerging Computing: From Devices to Systems - Looking Beyond Moore and Von Neumann . Springer , 2021 . O. Mutlu, S. Ghose, J. G\u00f3mez-Luna, and R. Ausavarungnirun, \"A Modern Primer on Processing in Memory,\" in Emerging Computing: From Devices to Systems - Looking Beyond Moore and Von Neumann. Springer, 2021."},{"key":"e_1_3_2_1_26_1","volume-title":"Evanesco: Architectural Support for Efficient Data Sanitization in Modern Flash-Based Storage Systems,\" in ASPLOS","author":"Kim M.","year":"2020","unstructured":"M. Kim , J. Park , G. Cho , Y. Kim , L. Orosa , O. Mutlu , and J. Kim , \" Evanesco: Architectural Support for Efficient Data Sanitization in Modern Flash-Based Storage Systems,\" in ASPLOS , 2020 . M. Kim, J. Park, G. Cho, Y. Kim, L. Orosa, O. Mutlu, and J. Kim, \"Evanesco: Architectural Support for Efficient Data Sanitization in Modern Flash-Based Storage Systems,\" in ASPLOS, 2020."},{"key":"e_1_3_2_1_27_1","volume-title":"Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques, \" in HPCA","author":"Cai Y.","year":"2017","unstructured":"Y. Cai , S. Ghose , Y. Luo , K. Mai , O. Mutlu , and E. F. Haratsch , \" Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques, \" in HPCA , 2017 . Y. Cai, S. Ghose, Y. Luo, K. Mai, O. Mutlu, and E. F. Haratsch, \"Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques, \" in HPCA, 2017."},{"key":"e_1_3_2_1_28_1","volume-title":"Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis,\" in DATE","author":"Cai Y.","year":"2012","unstructured":"Y. Cai , E. F. Haratsch , O. Mutlu , and K. Mai , \" Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis,\" in DATE , 2012 . Y. Cai, E. F. Haratsch, O. Mutlu, and K. Mai, \"Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis,\" in DATE, 2012."},{"key":"e_1_3_2_1_29_1","volume-title":"After Hard Drives---What Comes Next?\" TMAG","author":"Kryder M. H.","year":"2009","unstructured":"M. H. Kryder and C. S. Kim , \" After Hard Drives---What Comes Next?\" TMAG , 2009 . M. H. Kryder and C. S. Kim, \"After Hard Drives---What Comes Next?\" TMAG, 2009."},{"key":"e_1_3_2_1_30_1","volume-title":"Reliability of Solid-State Drives Based on NAND Flash Memory,\" Proc","author":"Mielke N. R.","year":"2017","unstructured":"N. R. Mielke , R. E. Frickey , I. Kalastirsky , M. Quan , D. Ustinov , and V. J. Vasudevan , \" Reliability of Solid-State Drives Based on NAND Flash Memory,\" Proc . IEEE , 2017 . N. R. Mielke, R. E. Frickey, I. Kalastirsky, M. Quan, D. Ustinov, and V. J. Vasudevan, \"Reliability of Solid-State Drives Based on NAND Flash Memory,\" Proc. IEEE, 2017."},{"key":"e_1_3_2_1_31_1","unstructured":"Samsung \"Ultra-Low Latency with Samsung Z-NAND SSD \" https:\/\/semiconductor.samsung.com\/resources\/brochure\/Ultra-Low%20Latency%20with%20Samsung%20Z-NAND%20SSD.pdf.  Samsung \"Ultra-Low Latency with Samsung Z-NAND SSD \" https:\/\/semiconductor.samsung.com\/resources\/brochure\/Ultra-Low%20Latency%20with%20Samsung%20Z-NAND%20SSD.pdf."},{"key":"e_1_3_2_1_32_1","unstructured":"NVM Express Workgroup \"NVM Express Specification Revision 1.2 \" 2014.  NVM Express Workgroup \"NVM Express Specification Revision 1.2 \" 2014."},{"key":"e_1_3_2_1_33_1","unstructured":"Micron \"3D XPoint Technology https:\/\/www.micron.com\/products\/advanced-solutions\/3d-xpoint-technology.\"  Micron \"3D XPoint Technology https:\/\/www.micron.com\/products\/advanced-solutions\/3d-xpoint-technology.\""},{"key":"e_1_3_2_1_34_1","volume-title":"Kawabe et al., \"13.1 A 1.33Tb 4-bit\/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology,\" in ISSCC","author":"Shibata N.","year":"2019","unstructured":"N. Shibata , K. Kanda , T. Shimizu , J. Nakai , O. Nagao , N. Kobayashi , M. Miakashi , Y. Nagadomi , T. Nakano , T. Kawabe et al., \"13.1 A 1.33Tb 4-bit\/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology,\" in ISSCC , 2019 . N. Shibata, K. Kanda, T. Shimizu, J. Nakai, O. Nagao, N. Kobayashi, M. Miakashi, Y. Nagadomi, T. Nakano, T. Kawabe et al., \"13.1 A 1.33Tb 4-bit\/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology,\" in ISSCC, 2019."},{"key":"e_1_3_2_1_35_1","volume-title":"The Bleak Future of NAND Flash Memory,\" in FAST","author":"Grupp L. M.","year":"2012","unstructured":"L. M. Grupp , J. D. Davis , and S. Swanson , \" The Bleak Future of NAND Flash Memory,\" in FAST , 2012 . L. M. Grupp, J. D. Davis, and S. Swanson, \"The Bleak Future of NAND Flash Memory,\" in FAST, 2012."},{"key":"e_1_3_2_1_36_1","volume-title":"High-Capacity Solid State Disk Drives","author":"Nishtala S.","year":"2015","unstructured":"S. Nishtala and T. L. Lyon , \" High-Capacity Solid State Disk Drives ,\" 2015 , US Patent App . 14\/598,662. S. Nishtala and T. L. Lyon, \"High-Capacity Solid State Disk Drives,\" 2015, US Patent App. 14\/598,662."},{"key":"e_1_3_2_1_37_1","volume-title":"Performance, And Reliability,\"","author":"Hsu C.-D. A.","year":"2015","unstructured":"C.-D. A. Hsu , S. Arya , Y.-C. Chen , L. Zhang , and D. Xing , \" NAND Interface Capacity Extender Device For Extending Solid State Drives Capacity , Performance, And Reliability,\" 2015 , US Patent App . 14\/445,047. C.-D. A. Hsu, S. Arya, Y.-C. Chen, L. Zhang, and D. Xing, \"NAND Interface Capacity Extender Device For Extending Solid State Drives Capacity, Performance, And Reliability,\" 2015, US Patent App. 14\/445,047."},{"key":"e_1_3_2_1_38_1","volume-title":"Network-on-SSD: A Scalable and High-Performance Communication Design Paradigm for SSDs,\" IEEE CAL","author":"Tavakkol A.","year":"2012","unstructured":"A. Tavakkol , M. Arjomand , and H. Sarbazi-Azad , \" Network-on-SSD: A Scalable and High-Performance Communication Design Paradigm for SSDs,\" IEEE CAL , 2012 . A. Tavakkol, M. Arjomand, and H. Sarbazi-Azad, \"Network-on-SSD: A Scalable and High-Performance Communication Design Paradigm for SSDs,\" IEEE CAL, 2012."},{"key":"e_1_3_2_1_39_1","volume-title":"An Evaluation of Different Page Allocation Strategies on High-Speed SSDs.\" in HotStorage","author":"Jung M.","year":"2012","unstructured":"M. Jung and M. T. Kandemir , \" An Evaluation of Different Page Allocation Strategies on High-Speed SSDs.\" in HotStorage , 2012 . M. Jung and M. T. Kandemir, \"An Evaluation of Different Page Allocation Strategies on High-Speed SSDs.\" in HotStorage, 2012."},{"key":"e_1_3_2_1_40_1","volume-title":"Physically Addressed Queueing (PAQ): Improving Parallelism in Solid State Disks,\" in ISCA","author":"Jung M.","year":"2012","unstructured":"M. Jung , E. H. Wilson III, and M. Kandemir , \" Physically Addressed Queueing (PAQ): Improving Parallelism in Solid State Disks,\" in ISCA , 2012 . M. Jung, E. H. Wilson III, and M. Kandemir, \"Physically Addressed Queueing (PAQ): Improving Parallelism in Solid State Disks,\" in ISCA, 2012."},{"key":"e_1_3_2_1_41_1","volume-title":"Performance Impact and Interplay of SSD Parallelism through Advanced Commands, Allocation Strategy and Data Granularity,\" in ICS","author":"Hu Y.","year":"2011","unstructured":"Y. Hu , H. Jiang , D. Feng , L. Tian , H. Luo , and S. Zhang , \" Performance Impact and Interplay of SSD Parallelism through Advanced Commands, Allocation Strategy and Data Granularity,\" in ICS , 2011 . Y. Hu, H. Jiang, D. Feng, L. Tian, H. Luo, and S. Zhang, \"Performance Impact and Interplay of SSD Parallelism through Advanced Commands, Allocation Strategy and Data Granularity,\" in ICS, 2011."},{"key":"e_1_3_2_1_42_1","volume-title":"Exploiting Internal Parallelism of Flash-based SSDs,\" IEEE CAL","author":"Park S.-y.","year":"2010","unstructured":"S.-y. Park , E. Seo , J.-Y. Shin , S. Maeng , and J. Lee , \" Exploiting Internal Parallelism of Flash-based SSDs,\" IEEE CAL , 2010 . S.-y. Park, E. Seo, J.-Y. Shin, S. Maeng, and J. Lee, \"Exploiting Internal Parallelism of Flash-based SSDs,\" IEEE CAL, 2010."},{"key":"e_1_3_2_1_43_1","volume-title":"Improving the SSD Performance by Exploiting Request Characteristics and Internal Parallelism,\" TCAD","author":"Mao B.","year":"2017","unstructured":"B. Mao , S. Wu , and L. Duan , \" Improving the SSD Performance by Exploiting Request Characteristics and Internal Parallelism,\" TCAD , 2017 . B. Mao, S. Wu, and L. Duan, \"Improving the SSD Performance by Exploiting Request Characteristics and Internal Parallelism,\" TCAD, 2017."},{"key":"e_1_3_2_1_44_1","volume-title":"Improving Write Performance by Enhancing Internal Parallelism of Solid State Drives,\" in IPCCC","author":"Ruan X.","year":"2012","unstructured":"X. Ruan , Z. Zong , M. I. Alghamdi , Y. Tian , X. Jiang , and X. Qin , \" Improving Write Performance by Enhancing Internal Parallelism of Solid State Drives,\" in IPCCC , 2012 . X. Ruan, Z. Zong, M. I. Alghamdi, Y. Tian, X. Jiang, and X. Qin, \"Improving Write Performance by Enhancing Internal Parallelism of Solid State Drives,\" in IPCCC, 2012."},{"key":"e_1_3_2_1_45_1","volume-title":"Parallel all the Time: Plane Level Parallelism Exploration for High Performance SSDs,\" in MSST","author":"Gao C.","year":"2019","unstructured":"C. Gao , L. Shi , C. J. Xue , C. Ji , J. Yang , and Y. Zhang , \" Parallel all the Time: Plane Level Parallelism Exploration for High Performance SSDs,\" in MSST , 2019 . C. Gao, L. Shi, C. J. Xue, C. Ji, J. Yang, and Y. Zhang, \"Parallel all the Time: Plane Level Parallelism Exploration for High Performance SSDs,\" in MSST, 2019."},{"key":"e_1_3_2_1_46_1","volume-title":"Parallelizing Garbage Collection with I\/O to Improve Flash Resource Utilization,\" in HPDC","author":"Choi W.","year":"2018","unstructured":"W. Choi , M. Jung , M. Kandemir , and C. Das , \" Parallelizing Garbage Collection with I\/O to Improve Flash Resource Utilization,\" in HPDC , 2018 . W. Choi, M. Jung, M. Kandemir, and C. Das, \"Parallelizing Garbage Collection with I\/O to Improve Flash Resource Utilization,\" in HPDC, 2018."},{"key":"e_1_3_2_1_47_1","volume-title":"SFS: Random Write Considered Harmful in Solid State Drives,\" in FAST","author":"Min C.","year":"2012","unstructured":"C. Min , K. Kim , H. Cho , S.-W. Lee , and Y. I. Eom , \" SFS: Random Write Considered Harmful in Solid State Drives,\" in FAST , 2012 . C. Min, K. Kim, H. Cho, S.-W. Lee, and Y. I. Eom, \"SFS: Random Write Considered Harmful in Solid State Drives,\" in FAST, 2012."},{"key":"e_1_3_2_1_48_1","volume-title":"WAL-SSD: Address Remapping-Based Write-Ahead-Logging Solid-State Disks,\" TC","author":"Han K.","year":"2019","unstructured":"K. Han , H. Kim , and D. Shin , \" WAL-SSD: Address Remapping-Based Write-Ahead-Logging Solid-State Disks,\" TC , 2019 . K. Han, H. Kim, and D. Shin, \"WAL-SSD: Address Remapping-Based Write-Ahead-Logging Solid-State Disks,\" TC, 2019."},{"key":"e_1_3_2_1_49_1","volume-title":"An Efficient Page-level FTL to Optimize Address Translation in Flash Memory,\" in EuroSys","author":"Zhou Y.","year":"2015","unstructured":"Y. Zhou , F. Wu , P. Huang , X. He , C. Xie , and J. Zhou , \" An Efficient Page-level FTL to Optimize Address Translation in Flash Memory,\" in EuroSys , 2015 . Y. Zhou, F. Wu, P. Huang, X. He, C. Xie, and J. Zhou, \"An Efficient Page-level FTL to Optimize Address Translation in Flash Memory,\" in EuroSys, 2015."},{"key":"e_1_3_2_1_50_1","volume-title":"Improving Performance by Bridging the Semantic Gap between Multi-queue SSD and I\/O Virtualization Framework,\" in MSST","author":"Kim T. Y.","year":"2015","unstructured":"T. Y. Kim , D. H. Kang , D. Lee , and Y. I. Eom , \" Improving Performance by Bridging the Semantic Gap between Multi-queue SSD and I\/O Virtualization Framework,\" in MSST , 2015 . T. Y. Kim, D. H. Kang, D. Lee, and Y. I. Eom, \"Improving Performance by Bridging the Semantic Gap between Multi-queue SSD and I\/O Virtualization Framework,\" in MSST, 2015."},{"key":"e_1_3_2_1_51_1","unstructured":"Samsung \"Samsung 980 NVMe M.2 SSD https:\/\/www.anandtech.com\/show\/16504\/the-samsung-ssd-980-500gb-1tb-review.\"  Samsung \"Samsung 980 NVMe M.2 SSD https:\/\/www.anandtech.com\/show\/16504\/the-samsung-ssd-980-500gb-1tb-review.\""},{"key":"e_1_3_2_1_52_1","unstructured":"SK Hynix \"SK Hynix Gold P31 SSD https:\/\/ssd.skhynix.com\/gold_p31\/.\"  SK Hynix \"SK Hynix Gold P31 SSD https:\/\/ssd.skhynix.com\/gold_p31\/.\""},{"key":"e_1_3_2_1_53_1","unstructured":"Microchip \"Microchip 16-Channel PCIe Gen 5 Enterprise NVMe SSD Controller https:\/\/www.microchip.com\/en-us\/about\/news-releases\/products\/highest-performance-16-channel-pcie-gen-5-enterprise-nvme-ssd-controller.\"  Microchip \"Microchip 16-Channel PCIe Gen 5 Enterprise NVMe SSD Controller https:\/\/www.microchip.com\/en-us\/about\/news-releases\/products\/highest-performance-16-channel-pcie-gen-5-enterprise-nvme-ssd-controller.\""},{"key":"e_1_3_2_1_54_1","volume-title":"MQSim-E: An Enterprise SSD Simulator,\" IEEE CAL","author":"Lee D.","year":"2022","unstructured":"D. Lee , D. Hong , W. Choi , and J. Kim , \" MQSim-E: An Enterprise SSD Simulator,\" IEEE CAL , 2022 . D. Lee, D. Hong, W. Choi, and J. Kim, \"MQSim-E: An Enterprise SSD Simulator,\" IEEE CAL, 2022."},{"key":"e_1_3_2_1_55_1","unstructured":"Samsung \"PM9A3 SSD Whitepaper \" https:\/\/semiconductor.samsung.com\/resources\/white-paper\/PM9A3_SSD_Whitepaper.pdf.  Samsung \"PM9A3 SSD Whitepaper \" https:\/\/semiconductor.samsung.com\/resources\/white-paper\/PM9A3_SSD_Whitepaper.pdf."},{"key":"e_1_3_2_1_56_1","unstructured":"Wikipedia \"Venice https:\/\/en.wikipedia.org\/wiki\/Venice.\"  Wikipedia \"Venice https:\/\/en.wikipedia.org\/wiki\/Venice.\""},{"key":"e_1_3_2_1_57_1","volume-title":"MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices,\" in FAST","author":"Tavakkol A.","year":"2018","unstructured":"A. Tavakkol , J. G\u00f3mez-Luna , M. Sadrosadati , S. Ghose , and O. Mutlu , \" MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices,\" in FAST , 2018 . A. Tavakkol, J. G\u00f3mez-Luna, M. Sadrosadati, S. Ghose, and O. Mutlu, \"MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices,\" in FAST, 2018."},{"key":"e_1_3_2_1_58_1","unstructured":"CMU-SAFARI \"MQSim \" https:\/\/github.com\/CMU-SAFARI\/MQSim.git.  CMU-SAFARI \"MQSim \" https:\/\/github.com\/CMU-SAFARI\/MQSim.git."},{"key":"e_1_3_2_1_59_1","unstructured":"PCI-SIG \"PCI Express Specification 6.0 \" 2022 https:\/\/pcisig.com\/pci-express-6.0-specification.  PCI-SIG \"PCI Express Specification 6.0 \" 2022 https:\/\/pcisig.com\/pci-express-6.0-specification."},{"key":"e_1_3_2_1_60_1","volume-title":"Lee et al., \"A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes,\" JSSC","author":"Cho T.","year":"2001","unstructured":"T. Cho , Y.-T. Lee , E.-C. Kim , J.-W. Lee , S. Choi , S. Lee , D.-H. Kim , W.-G. Han , Y.-H. Lim , J.- D. Lee et al., \"A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes,\" JSSC , 2001 . T. Cho, Y.-T. Lee, E.-C. Kim, J.-W. Lee, S. Choi, S. Lee, D.-H. Kim, W.-G. Han, Y.-H. Lim, J.-D. Lee et al., \"A Dual-Mode NAND Flash Memory: 1-Gb Multilevel and High-Performance 512-Mb Single-Level Modes,\" JSSC, 2001."},{"key":"e_1_3_2_1_61_1","volume-title":"Lim et al., \"A 3.3V 4Gb Four-Level NAND Flash Memory with 90nm CMOS Technology,\" in ISSCC","author":"Lee S.","year":"2004","unstructured":"S. Lee , Y.-T. Lee , W.-K. Han , D.-H. Kim , M.-S. Kim , S.-H. Moon , H. C. Cho , J.-W. Lee , D.-S. Byeon , Y.- H. Lim et al., \"A 3.3V 4Gb Four-Level NAND Flash Memory with 90nm CMOS Technology,\" in ISSCC , 2004 . S. Lee, Y.-T. Lee, W.-K. Han, D.-H. Kim, M.-S. Kim, S.-H. Moon, H. C. Cho, J.-W. Lee, D.-S. Byeon, Y.-H. Lim et al., \"A 3.3V 4Gb Four-Level NAND Flash Memory with 90nm CMOS Technology,\" in ISSCC, 2004."},{"key":"e_1_3_2_1_62_1","volume-title":"Musha et al., \"A 512Gb 3b\/Cell 3D Flash Memory on a 96-Word-Line-Layer Technology,\" in ISSCC","author":"Maejima H.","year":"2018","unstructured":"H. Maejima , K. Kanda , S. Fujimura , T. Takagiwa , S. Ozawa , J. Sato , Y. Shindo , M. Sato , N. Kanagawa , J. Musha et al., \"A 512Gb 3b\/Cell 3D Flash Memory on a 96-Word-Line-Layer Technology,\" in ISSCC , 2018 . H. Maejima, K. Kanda, S. Fujimura, T. Takagiwa, S. Ozawa, J. Sato, Y. Shindo, M. Sato, N. Kanagawa, J. Musha et al., \"A 512Gb 3b\/Cell 3D Flash Memory on a 96-Word-Line-Layer Technology,\" in ISSCC, 2018."},{"key":"e_1_3_2_1_63_1","volume-title":"Kim et al., \"A 1-Tb, 4b\/Cell, 176-Stacked-WL 3D-NAND Flash Memory with Improved Read Latency and a 14.8 Gb\/mm2 Density,\" in ISSCC","author":"Cho W.","year":"2022","unstructured":"W. Cho , J. Jung , J. Kim , J. Ham , S. Lee , Y. Noh , D. Kim , W. Lee , K. Cho , K. Kim et al., \"A 1-Tb, 4b\/Cell, 176-Stacked-WL 3D-NAND Flash Memory with Improved Read Latency and a 14.8 Gb\/mm2 Density,\" in ISSCC , 2022 . W. Cho, J. Jung, J. Kim, J. Ham, S. Lee, Y. Noh, D. Kim, W. Lee, K. Cho, K. Kim et al., \"A 1-Tb, 4b\/Cell, 176-Stacked-WL 3D-NAND Flash Memory with Improved Read Latency and a 14.8 Gb\/mm2 Density,\" in ISSCC, 2022."},{"key":"e_1_3_2_1_64_1","volume-title":"How I Learned to Stop Worrying and Love Flash Endurance,\" HotStorage","author":"Mohan V.","year":"2010","unstructured":"V. Mohan , T. Siddiqua , S. Gurumurthi , and M. R. Stan , \" How I Learned to Stop Worrying and Love Flash Endurance,\" HotStorage , 2010 . V. Mohan, T. Siddiqua, S. Gurumurthi, and M. R. Stan, \"How I Learned to Stop Worrying and Love Flash Endurance,\" HotStorage, 2010."},{"key":"e_1_3_2_1_65_1","volume-title":"Write Endurance in Flash Drives: Measurements and Analysis,\" in FAST","author":"Boboila S.","year":"2010","unstructured":"S. Boboila and P. Desnoyers , \" Write Endurance in Flash Drives: Measurements and Analysis,\" in FAST , 2010 . S. Boboila and P. Desnoyers, \"Write Endurance in Flash Drives: Measurements and Analysis,\" in FAST, 2010."},{"key":"e_1_3_2_1_66_1","volume-title":"Wear Unleveling: Improving NAND Flash Lifetime by Balancing Page Endurance,\" in FAST","author":"Jimenez X.","year":"2014","unstructured":"X. Jimenez , D. Novo , and P. Ienne , \" Wear Unleveling: Improving NAND Flash Lifetime by Balancing Page Endurance,\" in FAST , 2014 . X. Jimenez, D. Novo, and P. Ienne, \"Wear Unleveling: Improving NAND Flash Lifetime by Balancing Page Endurance,\" in FAST, 2014."},{"key":"e_1_3_2_1_67_1","volume-title":"Improving MLC flash performance and endurance with Extended P\/E Cycles,\" in MSST","author":"Margaglia F.","year":"2015","unstructured":"F. Margaglia and A. Brinkmann , \" Improving MLC flash performance and endurance with Extended P\/E Cycles,\" in MSST , 2015 . F. Margaglia and A. Brinkmann, \"Improving MLC flash performance and endurance with Extended P\/E Cycles,\" in MSST, 2015."},{"key":"e_1_3_2_1_68_1","volume-title":"DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings,\" in ASPLOS","author":"Gupta A.","year":"2009","unstructured":"A. Gupta , Y. Kim , and B. Urgaonkar , \" DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings,\" in ASPLOS , 2009 . A. Gupta, Y. Kim, and B. Urgaonkar, \"DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings,\" in ASPLOS, 2009."},{"key":"e_1_3_2_1_69_1","doi-asserted-by":"crossref","unstructured":"J.-Y. Shin Z.-L. Xia N.-Y. Xu R. Gao X.-F. Cai S. Maeng and F.-H. Hsu \"FTL Design Exploration in Reconfigurable High-Performance SSD for Server Applications \" in ICS 2009.  J.-Y. Shin Z.-L. Xia N.-Y. Xu R. Gao X.-F. Cai S. Maeng and F.-H. Hsu \"FTL Design Exploration in Reconfigurable High-Performance SSD for Server Applications \" in ICS 2009.","DOI":"10.1145\/1542275.1542324"},{"key":"e_1_3_2_1_70_1","volume-title":"Design of a Host Interface Logic for GC-Free SSDs,\" TCAD","author":"Jung M.","year":"2019","unstructured":"M. Jung , W. Choi , M. Kwon , S. Srikantaiah , J. Yoo , and M. T. Kandemir , \" Design of a Host Interface Logic for GC-Free SSDs,\" TCAD , 2019 . M. Jung, W. Choi, M. Kwon, S. Srikantaiah, J. Yoo, and M. T. Kandemir, \"Design of a Host Interface Logic for GC-Free SSDs,\" TCAD, 2019."},{"key":"e_1_3_2_1_71_1","doi-asserted-by":"publisher","DOI":"10.5555\/2665671.2665715"},{"key":"e_1_3_2_1_72_1","unstructured":"Serial ATA International Organization \"AHCI specification for Serial ATA \" https:\/\/www.intel.com\/content\/www\/us\/en\/io\/serial-ata\/ahci.html.  Serial ATA International Organization \"AHCI specification for Serial ATA \" https:\/\/www.intel.com\/content\/www\/us\/en\/io\/serial-ata\/ahci.html."},{"key":"e_1_3_2_1_73_1","unstructured":"Serial ATA International Organization \"Serial ATA Revision 3.1 \" 2011 https:\/\/sata-io.org\/system\/files\/specifications\/SerialATA_Revision_3_1_Gold.pdf.  Serial ATA International Organization \"Serial ATA Revision 3.1 \" 2011 https:\/\/sata-io.org\/system\/files\/specifications\/SerialATA_Revision_3_1_Gold.pdf."},{"key":"e_1_3_2_1_74_1","volume-title":"Data Sheet","author":"Intel Corporation","year":"2017","unstructured":"Intel Corporation , \" Intel 3D NAND SSD DC P4500 Series , Data Sheet ,\" 2017 . Intel Corporation, \"Intel 3D NAND SSD DC P4500 Series, Data Sheet,\" 2017."},{"key":"e_1_3_2_1_75_1","volume-title":"Data Sheet","author":"Toshiba Corporation","year":"2016","unstructured":"Toshiba Corporation , \"PX04 PMB Series , Data Sheet ,\" 2016 . Toshiba Corporation, \"PX04PMB Series, Data Sheet,\" 2016."},{"key":"e_1_3_2_1_76_1","volume-title":"Data Sheet","author":"Western Digital Corporation","year":"2017","unstructured":"Western Digital Corporation , \" HGST Ultrastar SN200 Series , Data Sheet ,\" 2017 . Western Digital Corporation, \"HGST Ultrastar SN200 Series, Data Sheet,\" 2017."},{"key":"e_1_3_2_1_77_1","volume-title":"Data Sheet","author":"Western Digital Corp.","year":"2017","unstructured":"Western Digital Corp. , \" SanDisk Skyhawk & Skyhawk Ultra NVMe PCIe SSD , Data Sheet ,\" 2017 . Western Digital Corp., \"SanDisk Skyhawk & Skyhawk Ultra NVMe PCIe SSD, Data Sheet,\" 2017."},{"key":"e_1_3_2_1_78_1","volume-title":"Data Sheet","author":"Series OCZ","year":"2016","unstructured":"OCZ , \"RD400\/400A Series , Data Sheet ,\" 2016 . OCZ, \"RD400\/400A Series, Data Sheet,\" 2016."},{"key":"e_1_3_2_1_79_1","unstructured":"Samsung \"Samsung NVMe SSD 980 PRO \" https:\/\/download.semiconductor.samsung.com\/resources\/brochure\/SSD_980_PRO_980_PRO_with_Heatsink_Brochure.pdf.  Samsung \"Samsung NVMe SSD 980 PRO \" https:\/\/download.semiconductor.samsung.com\/resources\/brochure\/SSD_980_PRO_980_PRO_with_Heatsink_Brochure.pdf."},{"key":"e_1_3_2_1_80_1","unstructured":"Samsung \"Samsung NVMe SSD 990 PRO \" https:\/\/download.semiconductor.samsung.com\/resources\/brochure\/990_PRO_Series_Brouchure_Web_Version_1.0.pdf.  Samsung \"Samsung NVMe SSD 990 PRO \" https:\/\/download.semiconductor.samsung.com\/resources\/brochure\/990_PRO_Series_Brouchure_Web_Version_1.0.pdf."},{"key":"e_1_3_2_1_81_1","volume-title":"Past and Future,\" in SMARTCOMP","author":"Yang M.-C.","year":"2014","unstructured":"M.-C. Yang , Y.-M. Chang , C.-W. Tsao , P.-C. Huang , Y.-H. Chang , and T.-W. Kuo , \" Garbage Collection and Wear Leveling for Flash Memory : Past and Future,\" in SMARTCOMP , 2014 . M.-C. Yang, Y.-M. Chang, C.-W. Tsao, P.-C. Huang, Y.-H. Chang, and T.-W. Kuo, \"Garbage Collection and Wear Leveling for Flash Memory: Past and Future,\" in SMARTCOMP, 2014."},{"key":"e_1_3_2_1_82_1","volume-title":"Exploring the Potentials of Parallel Garbage Collection in SSDs for Enterprise Storage Systems,\" in SC","author":"Shahidi N.","year":"2016","unstructured":"N. Shahidi , M. T. Kandemir , M. Arjomand , C. R. Das , M. Jung , and A. Sivasubramaniam , \" Exploring the Potentials of Parallel Garbage Collection in SSDs for Enterprise Storage Systems,\" in SC , 2016 . N. Shahidi, M. T. Kandemir, M. Arjomand, C. R. Das, M. Jung, and A. Sivasubramaniam, \"Exploring the Potentials of Parallel Garbage Collection in SSDs for Enterprise Storage Systems,\" in SC, 2016."},{"key":"e_1_3_2_1_83_1","volume-title":"Preemptible I\/O Scheduling of Garbage Collection for Solid State Drives,\" TCAD","author":"Lee J.","year":"2013","unstructured":"J. Lee , Y. Kim , G. M. Shipman , S. Oral , and J. Kim , \" Preemptible I\/O Scheduling of Garbage Collection for Solid State Drives,\" TCAD , 2013 . J. Lee, Y. Kim, G. M. Shipman, S. Oral, and J. Kim, \"Preemptible I\/O Scheduling of Garbage Collection for Solid State Drives,\" TCAD, 2013."},{"key":"e_1_3_2_1_84_1","volume-title":"Taking Garbage Collection Overheads Off the Critical Path in SSDs,\" in Middleware","author":"Jung M.","year":"2012","unstructured":"M. Jung , R. Prabhakar , and M. T. Kandemir , \" Taking Garbage Collection Overheads Off the Critical Path in SSDs,\" in Middleware , 2012 . M. Jung, R. Prabhakar, and M. T. Kandemir, \"Taking Garbage Collection Overheads Off the Critical Path in SSDs,\" in Middleware, 2012."},{"key":"e_1_3_2_1_85_1","volume-title":"GCaR: Garbage Collection aware Cache Management with Improved Performance for Flash-based SSDs,\" in ICS","author":"Wu S.","year":"2016","unstructured":"S. Wu , Y. Lin , B. Mao , and H. Jiang , \" GCaR: Garbage Collection aware Cache Management with Improved Performance for Flash-based SSDs,\" in ICS , 2016 . S. Wu, Y. Lin, B. Mao, and H. Jiang, \"GCaR: Garbage Collection aware Cache Management with Improved Performance for Flash-based SSDs,\" in ICS, 2016."},{"key":"e_1_3_2_1_86_1","volume-title":"Rejuvenator: A Static Wear Leveling Algorithm for NAND Flash Memory with Minimized Overhead,\" in MSST","author":"Murugan M.","year":"2011","unstructured":"M. Murugan and D. H. Du , \" Rejuvenator: A Static Wear Leveling Algorithm for NAND Flash Memory with Minimized Overhead,\" in MSST , 2011 . M. Murugan and D. H. Du, \"Rejuvenator: A Static Wear Leveling Algorithm for NAND Flash Memory with Minimized Overhead,\" in MSST, 2011."},{"key":"e_1_3_2_1_87_1","volume-title":"Exploring SSD Endurance Model based on Write Amplification and Temperature,\" in IGSC","author":"Sun H.","year":"2016","unstructured":"H. Sun , G. Chen , X. Liang , and W. Liu , \" Exploring SSD Endurance Model based on Write Amplification and Temperature,\" in IGSC , 2016 . H. Sun, G. Chen, X. Liang, and W. Liu, \"Exploring SSD Endurance Model based on Write Amplification and Temperature,\" in IGSC, 2016."},{"key":"e_1_3_2_1_88_1","volume-title":"Cost-effectively Improving Life Endurance of MLC NAND Flash SSDs via Hierarchical Data Redundancy and Heterogeneous Flash Memory,\" in NAS","author":"Tan S.","year":"2015","unstructured":"S. Tan , R. Yu , S. Wan , and Q. Cao , \" Cost-effectively Improving Life Endurance of MLC NAND Flash SSDs via Hierarchical Data Redundancy and Heterogeneous Flash Memory,\" in NAS , 2015 . S. Tan, R. Yu, S. Wan, and Q. Cao, \"Cost-effectively Improving Life Endurance of MLC NAND Flash SSDs via Hierarchical Data Redundancy and Heterogeneous Flash Memory,\" in NAS, 2015."},{"key":"e_1_3_2_1_89_1","volume-title":"Decoupled SSD: Reducing Data Movement on NAND-Based Flash SSD,\" IEEE CAL","author":"Kim J.","year":"2021","unstructured":"J. Kim , M. Jung , and J. Kim , \" Decoupled SSD: Reducing Data Movement on NAND-Based Flash SSD,\" IEEE CAL , 2021 . J. Kim, M. Jung, and J. Kim, \"Decoupled SSD: Reducing Data Movement on NAND-Based Flash SSD,\" IEEE CAL, 2021."},{"key":"e_1_3_2_1_90_1","volume-title":"Reducing SSD Read Latency via NAND Flash Program and Erase Suspension,\" in FAST","author":"Wu G.","year":"2012","unstructured":"G. Wu and X. He , \" Reducing SSD Read Latency via NAND Flash Program and Erase Suspension,\" in FAST , 2012 . G. Wu and X. He, \"Reducing SSD Read Latency via NAND Flash Program and Erase Suspension,\" in FAST, 2012."},{"key":"e_1_3_2_1_91_1","unstructured":"ONFI Workgroup \"Open NAND Flash Interface Specification Revision 5.1 \" 2022 https:\/\/media-www.micron.com\/-\/media\/client\/onfi\/specs\/onfi_5_1_final_1 -d- 0.pdf.  ONFI Workgroup \"Open NAND Flash Interface Specification Revision 5.1 \" 2022 https:\/\/media-www.micron.com\/-\/media\/client\/onfi\/specs\/onfi_5_1_final_1 -d- 0.pdf."},{"key":"e_1_3_2_1_92_1","volume-title":"LDPC-in-SSD: Making Advanced Error Correction Codes Work Effectively in Solid State Drives,\" in FAST","author":"Zhao K.","year":"2013","unstructured":"K. Zhao , W. Zhao , H. Sun , X. Zhang , N. Zheng , and T. Zhang , \" LDPC-in-SSD: Making Advanced Error Correction Codes Work Effectively in Solid State Drives,\" in FAST , 2013 . K. Zhao, W. Zhao, H. Sun, X. Zhang, N. Zheng, and T. Zhang, \"LDPC-in-SSD: Making Advanced Error Correction Codes Work Effectively in Solid State Drives,\" in FAST, 2013."},{"key":"e_1_3_2_1_93_1","volume-title":"Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs),\" JSSC","author":"Tanakamaru S.","year":"2013","unstructured":"S. Tanakamaru , Y. Yanagihara , and K. Takeuchi , \" Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs),\" JSSC , 2013 . S. Tanakamaru, Y. Yanagihara, and K. Takeuchi, \"Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs),\" JSSC, 2013."},{"key":"e_1_3_2_1_94_1","volume-title":"Reducing Solid-State Drive Read Latency by Optimizing Read-Retry,\" in ASPLOS","author":"Park J.","year":"2021","unstructured":"J. Park , M. Kim , M. Chun , L. Orosa , J. Kim , and O. Mutlu , \" Reducing Solid-State Drive Read Latency by Optimizing Read-Retry,\" in ASPLOS , 2021 . J. Park, M. Kim, M. Chun, L. Orosa, J. Kim, and O. Mutlu, \"Reducing Solid-State Drive Read Latency by Optimizing Read-Retry,\" in ASPLOS, 2021."},{"key":"e_1_3_2_1_95_1","volume-title":"Exploiting Process Similarity of 3D Flash Memory for High Performance SSDs,\" in MICRO","author":"Shim Y.","year":"2019","unstructured":"Y. Shim , M. Kim , M. Chun , J. Park , Y. Kim , and J. Kim , \" Exploiting Process Similarity of 3D Flash Memory for High Performance SSDs,\" in MICRO , 2019 . Y. Shim, M. Kim, M. Chun, J. Park, Y. Kim, and J. Kim, \"Exploiting Process Similarity of 3D Flash Memory for High Performance SSDs,\" in MICRO, 2019."},{"key":"e_1_3_2_1_96_1","volume-title":"Improving 3-D NAND SSD Read Performance by Parallelizing Read-Retry,\" TCAD","author":"Cui J.","year":"2022","unstructured":"J. Cui , Z. Zeng , J. Huang , W. Yuan , and L. T. Yang , \" Improving 3-D NAND SSD Read Performance by Parallelizing Read-Retry,\" TCAD , 2022 . J. Cui, Z. Zeng, J. Huang, W. Yuan, and L. T. Yang, \"Improving 3-D NAND SSD Read Performance by Parallelizing Read-Retry,\" TCAD, 2022."},{"key":"e_1_3_2_1_97_1","volume-title":"LaLDPC: Latency-aware LDPC for Read Performance Improvement of Solid State Drives,\" in MSST","author":"Du Y.","year":"2017","unstructured":"Y. Du , D. Zou , Q. Li , L. Shi , H. Jin , and C. J. Xue , \" LaLDPC: Latency-aware LDPC for Read Performance Improvement of Solid State Drives,\" in MSST , 2017 . Y. Du, D. Zou, Q. Li, L. Shi, H. Jin, and C. J. Xue, \"LaLDPC: Latency-aware LDPC for Read Performance Improvement of Solid State Drives,\" in MSST, 2017."},{"key":"e_1_3_2_1_98_1","volume-title":"SOML Read: Rethinking the Read Operation Granularity of 3D NAND SSDs,\" in ASPLOS","author":"Liu C.-Y.","year":"2019","unstructured":"C.-Y. Liu , J. B. Kotra , M. Jung , M. T. Kandemir , and C. R. Das , \" SOML Read: Rethinking the Read Operation Granularity of 3D NAND SSDs,\" in ASPLOS , 2019 . C.-Y. Liu, J. B. Kotra, M. Jung, M. T. Kandemir, and C. R. Das, \"SOML Read: Rethinking the Read Operation Granularity of 3D NAND SSDs,\" in ASPLOS, 2019."},{"key":"e_1_3_2_1_99_1","volume-title":"Yu et al., \"A Flash Memory Controller for 15\u03bcs Ultra-Low-Latency SSD Using High-Speed 3D NAND Flash with 3\u03bcs Read Time,\" in ISSCC","author":"Cheong W.","year":"2018","unstructured":"W. Cheong , C. Yoon , S. Woo , K. Han , D. Kim , C. Lee , Y. Choi , S. Kim , D. Kang , G. Yu et al., \"A Flash Memory Controller for 15\u03bcs Ultra-Low-Latency SSD Using High-Speed 3D NAND Flash with 3\u03bcs Read Time,\" in ISSCC , 2018 . W. Cheong, C. Yoon, S. Woo, K. Han, D. Kim, C. Lee, Y. Choi, S. Kim, D. Kang, G. Yu et al., \"A Flash Memory Controller for 15\u03bcs Ultra-Low-Latency SSD Using High-Speed 3D NAND Flash with 3\u03bcs Read Time,\" in ISSCC, 2018."},{"key":"e_1_3_2_1_100_1","volume-title":"july 28","author":"Newsroom I.","year":"2015","unstructured":"I. Newsroom , \" Intel and micron produce breakthrough memory technology , july 28 , 2015 .\" I. Newsroom, \"Intel and micron produce breakthrough memory technology, july 28, 2015.\""},{"key":"e_1_3_2_1_101_1","unstructured":"Intel \"Intel Optane SSD DC P4801X Series https:\/\/ark.intel.com\/content\/www\/us\/en\/ark\/products\/149365\/intel-optane-ssd-dc-p4801x-series-100gb-2-5in-pcie-x4-3d-xpoint.html.\"  Intel \"Intel Optane SSD DC P4801X Series https:\/\/ark.intel.com\/content\/www\/us\/en\/ark\/products\/149365\/intel-optane-ssd-dc-p4801x-series-100gb-2-5in-pcie-x4-3d-xpoint.html.\""},{"key":"e_1_3_2_1_102_1","doi-asserted-by":"publisher","DOI":"10.5555\/2821589"},{"key":"e_1_3_2_1_103_1","volume-title":"Venice: Improving Solid-State Drive Parallelism at Low Cost via Conflict-Free Accesses,\" in arXiv","author":"Nadig R.","year":"2023","unstructured":"R. Nadig , M. Sadrosadati , H. Mao , N. Mansouri Ghiasi , A. Tavakkol , J. Park , H. Sarbazi-Azad , J. G\u00f3mez-Luna , and O. Mutlu , \" Venice: Improving Solid-State Drive Parallelism at Low Cost via Conflict-Free Accesses,\" in arXiv , 2023 . R. Nadig, M. Sadrosadati, H. Mao, N. Mansouri Ghiasi, A. Tavakkol, J. Park, H. Sarbazi-Azad, J. G\u00f3mez-Luna, and O. Mutlu, \"Venice: Improving Solid-State Drive Parallelism at Low Cost via Conflict-Free Accesses,\" in arXiv, 2023."},{"key":"e_1_3_2_1_104_1","volume-title":"Morgan Kaufmann","author":"Duato J.","year":"2003","unstructured":"J. Duato , S. Yalamanchili , and L. M. Ni , Interconnection Networks: An Engineering Approach . Morgan Kaufmann , 2003 . J. Duato, S. Yalamanchili, and L. M. Ni, Interconnection Networks: An Engineering Approach. Morgan Kaufmann, 2003."},{"key":"e_1_3_2_1_105_1","volume-title":"A Case for Bufferless Routing in On-Chip Networks,\" in ISCA","author":"Moscibroda T.","year":"2009","unstructured":"T. Moscibroda and O. Mutlu , \" A Case for Bufferless Routing in On-Chip Networks,\" in ISCA , 2009 . T. Moscibroda and O. Mutlu, \"A Case for Bufferless Routing in On-Chip Networks,\" in ISCA, 2009."},{"key":"e_1_3_2_1_106_1","doi-asserted-by":"crossref","unstructured":"L. Gravano G. D. Pifarre P. E. Berman and J. L. C. Sanz \"Adaptive Deadlock- and Livelock-Free Routing With all Minimal Paths in Torus Networks \" IEEE TPDS 1994.  L. Gravano G. D. Pifarre P. E. Berman and J. L. C. Sanz \"Adaptive Deadlock- and Livelock-Free Routing With all Minimal Paths in Torus Networks \" IEEE TPDS 1994.","DOI":"10.1109\/71.334898"},{"key":"e_1_3_2_1_107_1","volume-title":"CHIPPER: A Low-complexity Bufferless Deflection Router,\" in HPCA","author":"Fallin C.","year":"2011","unstructured":"C. Fallin , C. Craik , and O. Mutlu , \" CHIPPER: A Low-complexity Bufferless Deflection Router,\" in HPCA , 2011 . C. Fallin, C. Craik, and O. Mutlu, \"CHIPPER: A Low-complexity Bufferless Deflection Router,\" in HPCA, 2011."},{"key":"e_1_3_2_1_109_1","volume-title":"The Turn Model for Adaptive Routing,\" in ISCA","author":"Glass C. J.","year":"1992","unstructured":"C. J. Glass and L. M. Ni , \" The Turn Model for Adaptive Routing,\" in ISCA , 1992 . C. J. Glass and L. M. Ni, \"The Turn Model for Adaptive Routing,\" in ISCA, 1992."},{"key":"e_1_3_2_1_110_1","volume-title":"An Abacus Turn Model for Time\/Space-Efficient Reconfigurable Routing,\" in ISCA","author":"Fu B.","year":"2011","unstructured":"B. Fu , Y. Han , J. Ma , H. Li , and X. Li , \" An Abacus Turn Model for Time\/Space-Efficient Reconfigurable Routing,\" in ISCA , 2011 . B. Fu, Y. Han, J. Ma, H. Li, and X. Li, \"An Abacus Turn Model for Time\/Space-Efficient Reconfigurable Routing,\" in ISCA, 2011."},{"key":"e_1_3_2_1_111_1","volume-title":"Application-aware deadlock-free oblivious routing based on extended turn-model,\" in ICCAD","author":"Shafiee A.","year":"2011","unstructured":"A. Shafiee , M. Zolghadr , M. Arjomand , and H. Sarbazi-Azad , \" Application-aware deadlock-free oblivious routing based on extended turn-model,\" in ICCAD , 2011 . A. Shafiee, M. Zolghadr, M. Arjomand, and H. Sarbazi-Azad, \"Application-aware deadlock-free oblivious routing based on extended turn-model,\" in ICCAD, 2011."},{"key":"e_1_3_2_1_112_1","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080253"},{"key":"e_1_3_2_1_113_1","doi-asserted-by":"crossref","unstructured":"J. Duato \"A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks \" TPDS 1995.  J. Duato \"A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks \" TPDS 1995.","DOI":"10.1109\/ICPP.1994.36"},{"key":"e_1_3_2_1_114_1","volume-title":"Design and Evaluation of Hierarchical Rings with Deflection Routing,\" in SBAC-PAD","author":"Ausavarungnirun R.","year":"2014","unstructured":"R. Ausavarungnirun , C. Fallin , X. Yu , K. K.-W. Chang , G. Nazario , R. Das , G. H. Loh , and O. Mutlu , \" Design and Evaluation of Hierarchical Rings with Deflection Routing,\" in SBAC-PAD , 2014 . R. Ausavarungnirun, C. Fallin, X. Yu, K. K.-W. Chang, G. Nazario, R. Das, G. H. Loh, and O. Mutlu, \"Design and Evaluation of Hierarchical Rings with Deflection Routing,\" in SBAC-PAD, 2014."},{"key":"e_1_3_2_1_115_1","volume-title":"Understanding the Interconnection Network of SpiNNaker,\" in ICS","author":"Navaridas J.","year":"2009","unstructured":"J. Navaridas , M. Luj\u00e1n , J. Miguel-Alonso , L. A. Plana , and S. Furber , \" Understanding the Interconnection Network of SpiNNaker,\" in ICS , 2009 . J. Navaridas, M. Luj\u00e1n, J. Miguel-Alonso, L. A. Plana, and S. Furber, \"Understanding the Interconnection Network of SpiNNaker,\" in ICS, 2009."},{"key":"e_1_3_2_1_116_1","volume-title":"Adaptive Deadlock-and Livelock-Free Routing with All Minimal Paths in Torus Networks,\" in SPAA","author":"Berman P. E.","year":"1992","unstructured":"P. E. Berman , L. Gravano , G. D. Pifarre , and J. L. Sanz , \" Adaptive Deadlock-and Livelock-Free Routing with All Minimal Paths in Torus Networks,\" in SPAA , 1992 . P. E. Berman, L. Gravano, G. D. Pifarre, and J. L. Sanz, \"Adaptive Deadlock-and Livelock-Free Routing with All Minimal Paths in Torus Networks,\" in SPAA, 1992."},{"key":"e_1_3_2_1_117_1","volume-title":"An Adaptive Deadlock and Livelock Free Routing Algorithm,\" in EMPDP","author":"Coli M.","year":"1995","unstructured":"M. Coli and P. Palazzari , \" An Adaptive Deadlock and Livelock Free Routing Algorithm,\" in EMPDP , 1995 . M. Coli and P. Palazzari, \"An Adaptive Deadlock and Livelock Free Routing Algorithm,\" in EMPDP, 1995."},{"key":"e_1_3_2_1_118_1","doi-asserted-by":"crossref","unstructured":"L.-T. Wang and E. J. McCluskey \"Linear Feedback Shift Register Design Using Cyclic Codes \" TC 1988.  L.-T. Wang and E. J. McCluskey \"Linear Feedback Shift Register Design Using Cyclic Codes \" TC 1988.","DOI":"10.1109\/12.5994"},{"key":"e_1_3_2_1_119_1","unstructured":"Samsung \"Samsung Z-SSD SZ985 https:\/\/image.semiconductor.samsung.com\/content\/samsung\/p6\/semiconductor\/newsroom\/tech-blog\/samsung-z-ssd-sz985\/Brochure_Samsung_S-ZZD_SZ985_1804.pdf.\"  Samsung \"Samsung Z-SSD SZ985 https:\/\/image.semiconductor.samsung.com\/content\/samsung\/p6\/semiconductor\/newsroom\/tech-blog\/samsung-z-ssd-sz985\/Brochure_Samsung_S-ZZD_SZ985_1804.pdf.\""},{"key":"e_1_3_2_1_120_1","unstructured":"UMC \"55 \/ 65 \/ 90nm https:\/\/www.umc.com\/en\/Product\/technologies\/Detail\/55_65_90nm.\"  UMC \"55 \/ 65 \/ 90nm https:\/\/www.umc.com\/en\/Product\/technologies\/Detail\/55_65_90nm.\""},{"key":"e_1_3_2_1_121_1","volume-title":"ORION3. 0: A Comprehensive NoC Router Estimation Tool,\" ESL","author":"Kahng A. B.","year":"2015","unstructured":"A. B. Kahng , B. Lin , and S. Nath , \" ORION3. 0: A Comprehensive NoC Router Estimation Tool,\" ESL , 2015 . A. B. Kahng, B. Lin, and S. Nath, \"ORION3. 0: A Comprehensive NoC Router Estimation Tool,\" ESL, 2015."},{"key":"e_1_3_2_1_122_1","volume-title":"Write Off-Loading: Practical Power Management for Enterprise Storage,\" TOS","author":"Narayanan D.","year":"2008","unstructured":"D. Narayanan , A. Donnelly , and A. Rowstron , \" Write Off-Loading: Practical Power Management for Enterprise Storage,\" TOS , 2008 . D. Narayanan, A. Donnelly, and A. Rowstron, \"Write Off-Loading: Practical Power Management for Enterprise Storage,\" TOS, 2008."},{"key":"e_1_3_2_1_123_1","volume-title":"Benchmarking Cloud Serving Systems with YCSB,\" in SoCC","author":"Cooper B. F.","year":"2010","unstructured":"B. F. Cooper , A. Silberstein , E. Tam , R. Ramakrishnan , and R. Sears , \" Benchmarking Cloud Serving Systems with YCSB,\" in SoCC , 2010 . B. F. Cooper, A. Silberstein, E. Tam, R. Ramakrishnan, and R. Sears, \"Benchmarking Cloud Serving Systems with YCSB,\" in SoCC, 2010."},{"key":"e_1_3_2_1_124_1","volume-title":"Slacker: Fast Distribution with Lazy Docker Containers,\" in FAST","author":"Harter T.","year":"2016","unstructured":"T. Harter , B. Salmon , R. Liu , A. C. Arpaci-Dusseau , and R. H. Arpaci-Dusseau , \" Slacker: Fast Distribution with Lazy Docker Containers,\" in FAST , 2016 . T. Harter, B. Salmon, R. Liu, A. C. Arpaci-Dusseau, and R. H. Arpaci-Dusseau, \"Slacker: Fast Distribution with Lazy Docker Containers,\" in FAST, 2016."},{"key":"e_1_3_2_1_125_1","volume-title":"Understanding Storage Traffic Characteristics on Enterprise Virtual Desktop Infrastructure,\" in SYSTOR","author":"Lee C.","year":"2017","unstructured":"C. Lee , T. Kumano , T. Matsuki , H. Endo , N. Fukumoto , and M. Sugawara , \" Understanding Storage Traffic Characteristics on Enterprise Virtual Desktop Infrastructure,\" in SYSTOR , 2017 . C. Lee, T. Kumano, T. Matsuki, H. Endo, N. Fukumoto, and M. Sugawara, \"Understanding Storage Traffic Characteristics on Enterprise Virtual Desktop Infrastructure,\" in SYSTOR, 2017."},{"key":"e_1_3_2_1_126_1","volume-title":"SSD-Based Workload Characteristics and their Performance Implications,\" TOS","author":"Yadgar G.","year":"2021","unstructured":"G. Yadgar , M. Gabel , S. Jaffer , and B. Schroeder , \" SSD-Based Workload Characteristics and their Performance Implications,\" TOS , 2021 . G. Yadgar, M. Gabel, S. Jaffer, and B. Schroeder, \"SSD-Based Workload Characteristics and their Performance Implications,\" TOS, 2021."},{"key":"e_1_3_2_1_127_1","volume-title":"Kang et al., \"13.4 A 512Gb 3-bit\/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB\/s Write Throughput and 1.2 Gb\/s Interface,\" in ISSCC","author":"Kang D.","year":"2019","unstructured":"D. Kang , M. Kim , S. C. Jeon , W. Jung , J. Park , G. Choo , D.-k. Shim , A. Kavala , S.-B. Kim , K.- M. Kang et al., \"13.4 A 512Gb 3-bit\/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB\/s Write Throughput and 1.2 Gb\/s Interface,\" in ISSCC , 2019 . D. Kang, M. Kim, S. C. Jeon, W. Jung, J. Park, G. Choo, D.-k. Shim, A. Kavala, S.-B. Kim, K.-M. Kang et al., \"13.4 A 512Gb 3-bit\/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB\/s Write Throughput and 1.2 Gb\/s Interface,\" in ISSCC, 2019."},{"key":"e_1_3_2_1_128_1","volume-title":"HyperLink NAND Flash Architecture for Mass Storage Applications,\" in NVSMW","author":"Schuetz R.","year":"2007","unstructured":"R. Schuetz , H. Oh , J.-K. Kim , H.-B. Pyeon , S. A. Przybylski , and P. Gillingham , \" HyperLink NAND Flash Architecture for Mass Storage Applications,\" in NVSMW , 2007 . R. Schuetz, H. Oh, J.-K. Kim, H.-B. Pyeon, S. A. Przybylski, and P. Gillingham, \"HyperLink NAND Flash Architecture for Mass Storage Applications,\" in NVSMW, 2007."},{"key":"e_1_3_2_1_129_1","volume-title":"800 MB\/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology,\" IEEE Access","author":"Gillingham P.","year":"2013","unstructured":"P. Gillingham , D. Chinn , E. Choi , J.-K. Kim , D. Macdonald , H. Oh , H.-B. Pyeon , and R. Schuetz , \" 800 MB\/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology,\" IEEE Access , 2013 . P. Gillingham, D. Chinn, E. Choi, J.-K. Kim, D. Macdonald, H. Oh, H.-B. Pyeon, and R. Schuetz, \"800 MB\/s DDR NAND Flash Memory Multi-Chip Package With Source-Synchronous Interface for Point-to-Point Ring Topology,\" IEEE Access, 2013."},{"key":"e_1_3_2_1_130_1","volume-title":"A 256Gb NAND Flash Memory Stack with 300MB\/s HLNAND Interface Chip for Point-to-Point Ring Topology,\" in IMW","author":"Gillingham P.","year":"2011","unstructured":"P. Gillingham , J.-K. Kim , R. Schuetz , H.-B. Pyeon , H. Oh , D. Macdonald , E. Choi , and D. Chinn , \" A 256Gb NAND Flash Memory Stack with 300MB\/s HLNAND Interface Chip for Point-to-Point Ring Topology,\" in IMW , 2011 . P. Gillingham, J.-K. Kim, R. Schuetz, H.-B. Pyeon, H. Oh, D. Macdonald, E. Choi, and D. Chinn, \"A 256Gb NAND Flash Memory Stack with 300MB\/s HLNAND Interface Chip for Point-to-Point Ring Topology,\" in IMW, 2011."},{"key":"e_1_3_2_1_131_1","volume-title":"A Novel I\/O Scheduler for SSD with Improved Performance and Lifetime,\" in MSST","author":"Wang H.","year":"2013","unstructured":"H. Wang , P. Huang , S. He , K. Zhou , C. Li , and X. He , \" A Novel I\/O Scheduler for SSD with Improved Performance and Lifetime,\" in MSST , 2013 . H. Wang, P. Huang, S. He, K. Zhou, C. Li, and X. He, \"A Novel I\/O Scheduler for SSD with Improved Performance and Lifetime,\" in MSST, 2013."},{"key":"e_1_3_2_1_132_1","volume-title":"Essential Roles of Exploiting Internal Parallelism of Flash Memory based Solid State Drives in High-Speed Data Processing,\" in HPCA","author":"Chen F.","year":"2011","unstructured":"F. Chen , R. Lee , and X. Zhang , \" Essential Roles of Exploiting Internal Parallelism of Flash Memory based Solid State Drives in High-Speed Data Processing,\" in HPCA , 2011 . F. Chen, R. Lee, and X. Zhang, \"Essential Roles of Exploiting Internal Parallelism of Flash Memory based Solid State Drives in High-Speed Data Processing,\" in HPCA, 2011."},{"key":"e_1_3_2_1_133_1","volume-title":"Exploiting Internal Parallelism for Address Translation in Solid-State Drives,\" TOS","author":"Xie W.","year":"2018","unstructured":"W. Xie , Y. Chen , and P. C. Roth , \" Exploiting Internal Parallelism for Address Translation in Solid-State Drives,\" TOS , 2018 . W. Xie, Y. Chen, and P. C. Roth, \"Exploiting Internal Parallelism for Address Translation in Solid-State Drives,\" TOS, 2018."},{"key":"e_1_3_2_1_134_1","volume-title":"SPA-SSD: Exploit Heterogeneity and Parallelism of 3D SLC-TLC Hybrid SSD to Improve Write Performance, \" in ICCD","author":"Zhang W.","year":"2019","unstructured":"W. Zhang , Q. Cao , H. Jiang , J. Yao , Y. Dong , and P. Yang , \" SPA-SSD: Exploit Heterogeneity and Parallelism of 3D SLC-TLC Hybrid SSD to Improve Write Performance, \" in ICCD , 2019 . W. Zhang, Q. Cao, H. Jiang, J. Yao, Y. Dong, and P. Yang, \"SPA-SSD: Exploit Heterogeneity and Parallelism of 3D SLC-TLC Hybrid SSD to Improve Write Performance, \" in ICCD, 2019."},{"key":"e_1_3_2_1_135_1","volume-title":"Fast Bulk Bitwise AND and OR in DRAM,\" IEEE CAL","author":"Seshadri V.","year":"2015","unstructured":"V. Seshadri , K. Hsieh , A. Boroumand , D. Lee , M. A. Kozuch , O. Mutlu , P. B. Gibbons , and T. C. Mowry , \" Fast Bulk Bitwise AND and OR in DRAM,\" IEEE CAL , 2015 . V. Seshadri, K. Hsieh, A. Boroumand, D. Lee, M. A. Kozuch, O. Mutlu, P. B. Gibbons, and T. C. Mowry, \"Fast Bulk Bitwise AND and OR in DRAM,\" IEEE CAL, 2015."},{"key":"e_1_3_2_1_136_1","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"e_1_3_2_1_137_1","volume-title":"SIMDRAM: A Framework for Bit-Serial SIMD Processing Using DRAM,\" in ASPLOS","author":"Hajinazar N.","year":"2021","unstructured":"N. Hajinazar , G. F. Oliveira , S. Gregorio , J. D. Ferreira , N. M. Ghiasi , M. Patel , M. Alser , S. Ghose , J. G\u00f3mez-Luna , and O. Mutlu , \" SIMDRAM: A Framework for Bit-Serial SIMD Processing Using DRAM,\" in ASPLOS , 2021 . N. Hajinazar, G. F. Oliveira, S. Gregorio, J. D. Ferreira, N. M. Ghiasi, M. Patel, M. Alser, S. Ghose, J. G\u00f3mez-Luna, and O. Mutlu, \"SIMDRAM: A Framework for Bit-Serial SIMD Processing Using DRAM,\" in ASPLOS, 2021."},{"key":"e_1_3_2_1_138_1","volume-title":"Willow: A User-Programmable SSD,\" in USENIX OSDI","author":"Seshadri S.","year":"2014","unstructured":"S. Seshadri , M. Gahagan , S. Bhaskaran , T. Bunker , A. De , Y. Jin , Y. Liu , and S. Swanson , \" Willow: A User-Programmable SSD,\" in USENIX OSDI , 2014 . S. Seshadri, M. Gahagan, S. Bhaskaran, T. Bunker, A. De, Y. Jin, Y. Liu, and S. Swanson, \"Willow: A User-Programmable SSD,\" in USENIX OSDI, 2014."},{"key":"e_1_3_2_1_139_1","volume-title":"ParaBit: Processing Parallel Bitwise Operations in NAND Flash Memory Based SSDs,\" in MICRO","author":"Gao C.","year":"2021","unstructured":"C. Gao , X. Xin , Y. Lu , Y. Zhang , J. Yang , and J. Shu , \" ParaBit: Processing Parallel Bitwise Operations in NAND Flash Memory Based SSDs,\" in MICRO , 2021 . C. Gao, X. Xin, Y. Lu, Y. Zhang, J. Yang, and J. Shu, \"ParaBit: Processing Parallel Bitwise Operations in NAND Flash Memory Based SSDs,\" in MICRO, 2021."},{"key":"e_1_3_2_1_140_1","volume-title":"Compute Caches,\" in HPCA","author":"Aga S.","year":"2017","unstructured":"S. Aga , S. Jeloka , A. Subramaniyan , S. Narayanasamy , D. Blaauw , and R. Das , \" Compute Caches,\" in HPCA , 2017 . S. Aga, S. Jeloka, A. Subramaniyan, S. Narayanasamy, D. Blaauw, and R. Das, \"Compute Caches,\" in HPCA, 2017."},{"key":"e_1_3_2_1_141_1","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"e_1_3_2_1_142_1","volume-title":"GenStore: A High-Performance In-Storage Processing System for Genome Sequence Analysis,\" in ASPLOS","author":"Ghiasi N. Mansouri","year":"2022","unstructured":"N. Mansouri Ghiasi , J. Park , H. Mustafa , J. Kim , A. Olgun , A. Gollwitzer , D. Senol Cali , C. Firtina , H. Mao , N. Almadhoun Alserr , R. Ausavarungnirun , N. Vijaykumar , M. Alser , and O. Mutlu , \" GenStore: A High-Performance In-Storage Processing System for Genome Sequence Analysis,\" in ASPLOS , 2022 . N. Mansouri Ghiasi, J. Park, H. Mustafa, J. Kim, A. Olgun, A. Gollwitzer, D. Senol Cali, C. Firtina, H. Mao, N. Almadhoun Alserr, R. Ausavarungnirun, N. Vijaykumar, M. Alser, and O. Mutlu, \"GenStore: A High-Performance In-Storage Processing System for Genome Sequence Analysis,\" in ASPLOS, 2022."},{"key":"e_1_3_2_1_143_1","volume-title":"Cho et al., \"Biscuit: A Framework for Near-Data Processing of Big Data Workloads,\" in ISCA","author":"Gu B.","year":"2016","unstructured":"B. Gu , A. S. Yoon , D.-H. Bae , I. Jo , J. Lee , J. Yoon , J.-U. Kang , M. Kwon , C. Yoon , S. Cho et al., \"Biscuit: A Framework for Near-Data Processing of Big Data Workloads,\" in ISCA , 2016 . B. Gu, A. S. Yoon, D.-H. Bae, I. Jo, J. Lee, J. Yoon, J.-U. Kang, M. Kwon, C. Yoon, S. Cho et al., \"Biscuit: A Framework for Near-Data Processing of Big Data Workloads,\" in ISCA, 2016."},{"key":"e_1_3_2_1_144_1","volume-title":"In-Storage Acceleration for Intelligent Queries,\" in MICRO","author":"Mailthody V. S.","year":"2019","unstructured":"V. S. Mailthody , Z. Qureshi , W. Liang , Z. Feng , S. G. De Gonzalo , Y. Li , H. Franke , J. Xiong , J. Huang , and W.-m. Hwu , \"Deepstore : In-Storage Acceleration for Intelligent Queries,\" in MICRO , 2019 . V. S. Mailthody, Z. Qureshi, W. Liang, Z. Feng, S. G. De Gonzalo, Y. Li, H. Franke, J. Xiong, J. Huang, and W.-m. Hwu, \"Deepstore: In-Storage Acceleration for Intelligent Queries,\" in MICRO, 2019."},{"key":"e_1_3_2_1_145_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2019.01.009"},{"key":"e_1_3_2_1_146_1","volume-title":"REGISTOR: A Platform for Unstructured Data Processing inside SSD Storage,\" TOS","author":"Pei S.","year":"2019","unstructured":"S. Pei , J. Yang , and Q. Yang , \" REGISTOR: A Platform for Unstructured Data Processing inside SSD Storage,\" TOS , 2019 . S. Pei, J. Yang, and Q. Yang, \"REGISTOR: A Platform for Unstructured Data Processing inside SSD Storage,\" TOS, 2019."},{"key":"e_1_3_2_1_147_1","volume-title":"RACER: Bit-Pipelined Processing Using Resistive Memory,\" in MICRO","author":"Truong M. S.","year":"2021","unstructured":"M. S. Truong , E. Chen , D. Su , L. Shen , A. Glass , L. R. Carley , J. A. Bain , and S. Ghose , \" RACER: Bit-Pipelined Processing Using Resistive Memory,\" in MICRO , 2021 . M. S. Truong, E. Chen, D. Su, L. Shen, A. Glass, L. R. Carley, J. A. Bain, and S. Ghose, \"RACER: Bit-Pipelined Processing Using Resistive Memory,\" in MICRO, 2021."},{"key":"e_1_3_2_1_148_1","volume-title":"Active Disks: Programming Model, Algorithms and Evaluation,\" ASPLOS","author":"Acharya A.","year":"1998","unstructured":"A. Acharya , M. Uysal , and J. Saltz , \" Active Disks: Programming Model, Algorithms and Evaluation,\" ASPLOS , 1998 . A. Acharya, M. Uysal, and J. Saltz, \"Active Disks: Programming Model, Algorithms and Evaluation,\" ASPLOS, 1998."},{"key":"e_1_3_2_1_149_1","volume-title":"Summarizer: Trading Communication with Computing Near Storage,\" in MICRO","author":"Koo G.","year":"2017","unstructured":"G. Koo , K. K. Matam , T. I, H. K. G. Narra , J. Li , H.-W. Tseng , S. Swanson , and M. Annavaram , \" Summarizer: Trading Communication with Computing Near Storage,\" in MICRO , 2017 . G. Koo, K. K. Matam, T. I, H. K. G. Narra, J. Li, H.-W. Tseng, S. Swanson, and M. Annavaram, \"Summarizer: Trading Communication with Computing Near Storage,\" in MICRO, 2017."},{"key":"e_1_3_2_1_150_1","volume-title":"IceClave: A Trusted Execution Environment for In-Storage Computing,\" in MICRO","author":"Kang L.","year":"2021","unstructured":"L. Kang , Y. Xue , W. Jia , X. Wang , J. Kim , C. Youn , M. J. Kang , H. J. Lim , B. Jacob , and J. Huang , \" IceClave: A Trusted Execution Environment for In-Storage Computing,\" in MICRO , 2021 . L. Kang, Y. Xue, W. Jia, X. Wang, J. Kim, C. Youn, M. J. Kang, H. J. Lim, B. Jacob, and J. Huang, \"IceClave: A Trusted Execution Environment for In-Storage Computing,\" in MICRO, 2021."},{"key":"e_1_3_2_1_151_1","volume-title":"Using Accelerated Flash Storage for External Graph Analytics,\" in ISCA","author":"Jun S.-W.","year":"2018","unstructured":"S.-W. Jun , A. Wright , S. Zhang , S. Xu , and Arvind, \"GraFBoost : Using Accelerated Flash Storage for External Graph Analytics,\" in ISCA , 2018 . S.-W. Jun, A. Wright, S. Zhang, S. Xu, and Arvind, \"GraFBoost: Using Accelerated Flash Storage for External Graph Analytics,\" in ISCA, 2018."},{"key":"e_1_3_2_1_152_1","volume-title":"Processing-in-Memory: A Workload-Driven Perspective,\" IBM JRD","author":"Ghose S.","year":"2019","unstructured":"S. Ghose , A. Boroumand , J. S. Kim , J. G\u00f3mez-Luna , and O. Mutlu , \" Processing-in-Memory: A Workload-Driven Perspective,\" IBM JRD , 2019 . S. Ghose, A. Boroumand, J. S. Kim, J. G\u00f3mez-Luna, and O. Mutlu, \"Processing-in-Memory: A Workload-Driven Perspective,\" IBM JRD, 2019."},{"key":"e_1_3_2_1_153_1","volume-title":"Active Disks for Large-Scale Data Processing,\" Computer","author":"Riedel E.","year":"2001","unstructured":"E. Riedel , C. Faloutsos , G. A. Gibson , and D. Nagle , \" Active Disks for Large-Scale Data Processing,\" Computer , 2001 . E. Riedel, C. Faloutsos, G. A. Gibson, and D. Nagle, \"Active Disks for Large-Scale Data Processing,\" Computer, 2001."},{"key":"e_1_3_2_1_154_1","volume-title":"Active Storage for Large-Scale Data Mining and Multimedia Applications,\" VLDB","author":"Riedel E.","year":"1998","unstructured":"E. Riedel , G. Gibson , and C. Faloutsos , \" Active Storage for Large-Scale Data Mining and Multimedia Applications,\" VLDB , 1998 . E. Riedel, G. Gibson, and C. Faloutsos, \"Active Storage for Large-Scale Data Mining and Multimedia Applications,\" VLDB, 1998."},{"key":"e_1_3_2_1_155_1","volume-title":"Enabling Cost-effective Data Processing with Smart SSD,\" in MSST","author":"Kang Y.","year":"2013","unstructured":"Y. Kang , Y.-s. Kee , E. L. Miller , and C. Park , \" Enabling Cost-effective Data Processing with Smart SSD,\" in MSST , 2013 . Y. Kang, Y.-s. Kee, E. L. Miller, and C. Park, \"Enabling Cost-effective Data Processing with Smart SSD,\" in MSST, 2013."},{"key":"e_1_3_2_1_156_1","volume-title":"A Case for Intelligent Disks (IDISKs),\" SIGMOD Record","author":"Keeton K.","year":"1998","unstructured":"K. Keeton , D. A. Patterson , and J. M. Hellerstein , \" A Case for Intelligent Disks (IDISKs),\" SIGMOD Record , 1998 . K. Keeton, D. A. Patterson, and J. M. Hellerstein, \"A Case for Intelligent Disks (IDISKs),\" SIGMOD Record, 1998."},{"key":"e_1_3_2_1_157_1","volume-title":"In-storage Processing of Database Scans and Joins,\" Information Sciences","author":"Kim S.","year":"2016","unstructured":"S. Kim , H. Oh , C. Park , S. Cho , S.-W. Lee , and B. Moon , \" In-storage Processing of Database Scans and Joins,\" Information Sciences , 2016 . S. Kim, H. Oh, C. Park, S. Cho, S.-W. Lee, and B. Moon, \"In-storage Processing of Database Scans and Joins,\" Information Sciences, 2016."},{"key":"e_1_3_2_1_158_1","volume-title":"Catalina: In-storage Processing Acceleration for Scalable Big Data Analytics,\" in EMPDP","author":"Torabzadehkashi M.","year":"2019","unstructured":"M. Torabzadehkashi , S. Rezaei , A. Heydarigorji , H. Bobarshad , V. Alves , and N. Bagherzadeh , \" Catalina: In-storage Processing Acceleration for Scalable Big Data Analytics,\" in EMPDP , 2019 . M. Torabzadehkashi, S. Rezaei, A. Heydarigorji, H. Bobarshad, V. Alves, and N. Bagherzadeh, \"Catalina: In-storage Processing Acceleration for Scalable Big Data Analytics,\" in EMPDP, 2019."},{"key":"e_1_3_2_1_159_1","volume-title":"SmartSSD: FPGA Accelerated Near-Storage Data Analytics on SSD,\" IEEE CAL","author":"Lee J. H.","year":"2020","unstructured":"J. H. Lee , H. Zhang , V. Lagrange , P. Krishnamoorthy , X. Zhao , and Y. S. Ki , \" SmartSSD: FPGA Accelerated Near-Storage Data Analytics on SSD,\" IEEE CAL , 2020 . J. H. Lee, H. Zhang, V. Lagrange, P. Krishnamoorthy, X. Zhao, and Y. S. Ki, \"SmartSSD: FPGA Accelerated Near-Storage Data Analytics on SSD,\" IEEE CAL, 2020."},{"key":"e_1_3_2_1_160_1","volume-title":"CIDR: A Cost-effective In-line Data Reduction System for Terabit-per-second Scale SSD Arrays,\" in HPCA","author":"Ajdari M.","year":"2019","unstructured":"M. Ajdari , P. Park , J. Kim , D. Kwon , and J. Kim , \" CIDR: A Cost-effective In-line Data Reduction System for Terabit-per-second Scale SSD Arrays,\" in HPCA , 2019 . M. Ajdari, P. Park, J. Kim, D. Kwon, and J. Kim, \"CIDR: A Cost-effective In-line Data Reduction System for Terabit-per-second Scale SSD Arrays,\" in HPCA, 2019."},{"key":"e_1_3_2_1_161_1","volume-title":"Alleviating Garbage Collection Interference Through Spatial Separation in All Flash Arrays,\" in USENIX ATC","author":"Kim J.","year":"2019","unstructured":"J. Kim , K. Lim , Y. Jung , S. Lee , C. Min , and S. H. Noh , \" Alleviating Garbage Collection Interference Through Spatial Separation in All Flash Arrays,\" in USENIX ATC , 2019 . J. Kim, K. Lim, Y. Jung, S. Lee, C. Min, and S. H. Noh, \"Alleviating Garbage Collection Interference Through Spatial Separation in All Flash Arrays,\" in USENIX ATC, 2019."},{"key":"e_1_3_2_1_162_1","doi-asserted-by":"crossref","unstructured":"W.-C. Tsai S.-M. Wu and L.-P. Chang \"Learning-Assisted Write Latency Optimization for Mobile Storage \" in RTCSA 2019.  W.-C. Tsai S.-M. Wu and L.-P. Chang \"Learning-Assisted Write Latency Optimization for Mobile Storage \" in RTCSA 2019.","DOI":"10.1109\/RTCSA.2019.8864577"},{"key":"e_1_3_2_1_163_1","volume-title":"Internal Parallelism of Flash Memory-Based Solid-State Drives,\" TOS","author":"Chen F.","year":"2016","unstructured":"F. Chen , B. Hou , and R. Lee , \" Internal Parallelism of Flash Memory-Based Solid-State Drives,\" TOS , 2016 . F. Chen, B. Hou, and R. Lee, \"Internal Parallelism of Flash Memory-Based Solid-State Drives,\" TOS, 2016."}],"event":{"name":"ISCA '23: 50th Annual International Symposium on Computer Architecture","location":"Orlando FL USA","acronym":"ISCA '23","sponsor":["SIGARCH ACM Special Interest Group on Computer Architecture","IEEE"]},"container-title":["Proceedings of the 50th Annual International Symposium on Computer Architecture"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3579371.3589071","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T16:46:39Z","timestamp":1750178799000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3579371.3589071"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,6,17]]},"references-count":162,"alternative-id":["10.1145\/3579371.3589071","10.1145\/3579371"],"URL":"https:\/\/doi.org\/10.1145\/3579371.3589071","relation":{},"subject":[],"published":{"date-parts":[[2023,6,17]]},"assertion":[{"value":"2023-06-17","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}