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Akhil Arunkumar, Evgeny Bolotin, Benjamin Cho, Ugljesa Milic, Eiman Ebrahimi, Oreste Villa, Aamer Jaleel, Carole-Jean Wu, and David Nellans. 2017. MCM-GPU: Multi-Chip-Module GPUs for Continued Performance Scalability. In Proceedings of the International Symposium on Computer Architecture (ISCA). IEEE, 320--332."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"e_1_3_2_1_4_1","volume-title":"Proceedings of the International Symposium on High Performance Computer Architecture (HPCA). IEEE, 596--609","author":"Baruah Trinayan","year":"2020","unstructured":"Trinayan Baruah , Yifan Sun , Ali Tolga Din\u00e7er , Saiful A Mojumder , Jos\u00e9 L Abell\u00e1n , Yash Ukidave , Ajay Joshi , Norman Rubin , John Kim , and David Kaeli . 2020 . Griffin: Hardware-Software Support for Efficient Page Migration in Multi-GPU Systems . In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA). IEEE, 596--609 . Trinayan Baruah, Yifan Sun, Ali Tolga Din\u00e7er, Saiful A Mojumder, Jos\u00e9 L Abell\u00e1n, Yash Ukidave, Ajay Joshi, Norman Rubin, John Kim, and David Kaeli. 2020. Griffin: Hardware-Software Support for Efficient Page Migration in Multi-GPU Systems. In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA). IEEE, 596--609."},{"key":"e_1_3_2_1_5_1","volume-title":"Proceedings of the International Symposium on Microarchitecture (MICRO). IEEE, 443--454","author":"Beckmann Bradford M","year":"2006","unstructured":"Bradford M Beckmann , Michael R Marty , and David A Wood . 2006 . ASR: Adaptive Selective Replication for CMP Caches . In Proceedings of the International Symposium on Microarchitecture (MICRO). IEEE, 443--454 . Bradford M Beckmann, Michael R Marty, and David A Wood. 2006. ASR: Adaptive Selective Replication for CMP Caches. In Proceedings of the International Symposium on Microarchitecture (MICRO). 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[Online ; accessed 2022 -04-16]. John Cavazos Scott Grauer-Gray. 2015. PolyBench\/GPU 1.0. https:\/\/web.cse.ohiostate.edu\/~pouchet.2\/software\/polybench\/. [Online; accessed 2022-04-16]."},{"key":"e_1_3_2_1_13_1","volume-title":"Computer Architecture: A Quantitative Approach","author":"Hennessy John L","year":"2017","unstructured":"John L Hennessy and David A Patterson . 2017 . Computer Architecture: A Quantitative Approach . Morgan Kaufmann Publishers . John L Hennessy and David A Patterson. 2017. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers."},{"key":"e_1_3_2_1_14_1","volume-title":"Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT). 161--173","author":"Ibrahim Mohamed Assem","year":"2020","unstructured":"Mohamed Assem Ibrahim , Onur Kayiran , Yasuko Eckert , Gabriel H Loh , and Adwait Jog . 2020 . Analyzing and Leveraging Shared L1 Caches in GPUs . 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[Online ; accessed 2022-04-16]. Micron. 2021. Technical Note: GDDR6 Design Guide. https:\/\/media-www.micron.com\/-\/media\/client\/global\/documents\/products\/technical-note\/dram\/tn-ed-04_gddr6_design_guide.pdf. [Online; accessed 2022-04-16]."},{"key":"e_1_3_2_1_25_1","volume-title":"Proceedings of the International Symposium on Microarchitecture (MICRO). IEEE, 123--135","author":"Milic Ugljesa","year":"2017","unstructured":"Ugljesa Milic , Oreste Villa , Evgeny Bolotin , Akhil Arunkumar , Eiman Ebrahimi , Aamer Jaleel , Alex Ramirez , and David Nellans . 2017 . Beyond the Socket: NUMA-Aware GPUs . In Proceedings of the International Symposium on Microarchitecture (MICRO). IEEE, 123--135 . Ugljesa Milic, Oreste Villa, Evgeny Bolotin, Akhil Arunkumar, Eiman Ebrahimi, Aamer Jaleel, Alex Ramirez, and David Nellans. 2017. Beyond the Socket: NUMA-Aware GPUs. In Proceedings of the International Symposium on Microarchitecture (MICRO). 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[Online; accessed 2022-04-16]."},{"key":"e_1_3_2_1_29_1","volume-title":"NVIDIA Tesla P100: The Most Advanced Datacenter Accelerator Ever Built. https:\/\/images.nvidia.com\/content\/pdf\/tesla\/whitepaper\/pascal-architecture-whitepaper.pdf. [Online","year":"2022","unstructured":"Nvidia. 2016. NVIDIA Tesla P100: The Most Advanced Datacenter Accelerator Ever Built. https:\/\/images.nvidia.com\/content\/pdf\/tesla\/whitepaper\/pascal-architecture-whitepaper.pdf. [Online ; accessed 2022 -04-16]. Nvidia. 2016. NVIDIA Tesla P100: The Most Advanced Datacenter Accelerator Ever Built. https:\/\/images.nvidia.com\/content\/pdf\/tesla\/whitepaper\/pascal-architecture-whitepaper.pdf. [Online; accessed 2022-04-16]."},{"key":"e_1_3_2_1_30_1","volume-title":"NVIDIA DGX-2: Break Through the Barriers to AI Speed and Scale. https:\/\/www.nvidia.com\/en-us\/data-center\/dgx-2\/. [Online","year":"2022","unstructured":"Nvidia. 2018. NVIDIA DGX-2: Break Through the Barriers to AI Speed and Scale. https:\/\/www.nvidia.com\/en-us\/data-center\/dgx-2\/. [Online ; accessed 2022 -04-16]. Nvidia. 2018. NVIDIA DGX-2: Break Through the Barriers to AI Speed and Scale. https:\/\/www.nvidia.com\/en-us\/data-center\/dgx-2\/. [Online; accessed 2022-04-16]."},{"key":"e_1_3_2_1_31_1","volume-title":"NVIDIA A100 Tensor Core GPU Architecture: The World's Most Advanced Data Center GPU. https:\/\/images.nvidia.com\/aem-dam\/en-zz\/Solutions\/data-center\/nvidia-ampere-architecture-whitepaper.pdf. [Online","year":"2022","unstructured":"Nvidia. 2020. NVIDIA A100 Tensor Core GPU Architecture: The World's Most Advanced Data Center GPU. https:\/\/images.nvidia.com\/aem-dam\/en-zz\/Solutions\/data-center\/nvidia-ampere-architecture-whitepaper.pdf. [Online ; accessed 2022 -04-16]. Nvidia. 2020. NVIDIA A100 Tensor Core GPU Architecture: The World's Most Advanced Data Center GPU. https:\/\/images.nvidia.com\/aem-dam\/en-zz\/Solutions\/data-center\/nvidia-ampere-architecture-whitepaper.pdf. [Online; accessed 2022-04-16]."},{"key":"e_1_3_2_1_32_1","volume-title":"NVIDIA cuDNN. https:\/\/developer.nvidia.com\/cudnn. [Online","year":"2022","unstructured":"Nvidia. 2020. NVIDIA cuDNN. https:\/\/developer.nvidia.com\/cudnn. [Online ; accessed 2022 -04-16]. Nvidia. 2020. NVIDIA cuDNN. https:\/\/developer.nvidia.com\/cudnn. [Online; accessed 2022-04-16]."},{"key":"e_1_3_2_1_33_1","volume-title":"NVIDIA CUDA SDK Code Samples. https:\/\/docs.nvidia.com\/cuda\/cuda-samples\/index.html. [Online","year":"2022","unstructured":"Nvidia. 2022. NVIDIA CUDA SDK Code Samples. https:\/\/docs.nvidia.com\/cuda\/cuda-samples\/index.html. [Online ; accessed 2022 -04-16]. Nvidia. 2022. NVIDIA CUDA SDK Code Samples. https:\/\/docs.nvidia.com\/cuda\/cuda-samples\/index.html. [Online; accessed 2022-04-16]."},{"key":"e_1_3_2_1_34_1","volume-title":"NVIDIA NVLINK: High-speed GPU Interconnect. https:\/\/www.nvidia.com\/en-us\/design-visualization\/nvlink-bridges\/. [Online","year":"2022","unstructured":"Nvidia. 2022 . NVIDIA NVLINK: High-speed GPU Interconnect. https:\/\/www.nvidia.com\/en-us\/design-visualization\/nvlink-bridges\/. [Online ; accessed 2022-04-16]. Nvidia. 2022. NVIDIA NVLINK: High-speed GPU Interconnect. https:\/\/www.nvidia.com\/en-us\/design-visualization\/nvlink-bridges\/. [Online; accessed 2022-04-16]."},{"key":"e_1_3_2_1_35_1","volume-title":"Proceedings of the International Symposium on Computer Architecture (ISCA). IEEE, 167--178","author":"Qureshi Moinuddin K","year":"2006","unstructured":"Moinuddin K Qureshi , Daniel N Lynch , Onur Mutlu , and Yale N Patt . 2006 . A Case for MLP-Aware Cache Replacement . In Proceedings of the International Symposium on Computer Architecture (ISCA). IEEE, 167--178 . Moinuddin K Qureshi, Daniel N Lynch, Onur Mutlu, and Yale N Patt. 2006. A Case for MLP-Aware Cache Replacement. In Proceedings of the International Symposium on Computer Architecture (ISCA). IEEE, 167--178."},{"key":"e_1_3_2_1_36_1","volume-title":"Proceedings of the International Symposium on High Performance Computer Architecture (HPCA). IEEE, 582--595","author":"Ren Xiaowei","year":"2020","unstructured":"Xiaowei Ren , Daniel Lustig , Evgeny Bolotin , Aamer Jaleel , Oreste Villa , and David Nellans . 2020 . HMG: Extending Cache Coherence Protocols Across Modern Hierarchical Multi-GPU Systems . In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA). IEEE, 582--595 . Xiaowei Ren, Daniel Lustig, Evgeny Bolotin, Aamer Jaleel, Oreste Villa, and David Nellans. 2020. HMG: Extending Cache Coherence Protocols Across Modern Hierarchical Multi-GPU Systems. In Proceedings of the International Symposium on High Performance Computer Architecture (HPCA). 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Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio. In Proceedings of the Annual International Symposium on Computer Architecture (ISCA). 384--393."},{"key":"e_1_3_2_1_39_1","volume-title":"Proceedings of the International Symposium on Microarchitecture (MICRO). IEEE, 14--27","author":"Shao Yakun Sophia","unstructured":"Yakun Sophia Shao , Jason Clemons , Rangharajan Venkatesan , Brian Zimmer , Matthew Fojtik , Nan Jiang , Ben Keller , Alicia Klinefelter , Nathaniel Pinckney , Priyanka Raina , Stephen G. Tell , Yanqing Zhang , William J. Dally , Joel Emer , C. Thomas Gray , Brucek Khailany , and Stephen W. Keckler . 2019. Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture . In Proceedings of the International Symposium on Microarchitecture (MICRO). IEEE, 14--27 . Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel Emer, C. Thomas Gray, Brucek Khailany, and Stephen W. Keckler. 2019. Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. In Proceedings of the International Symposium on Microarchitecture (MICRO). IEEE, 14--27."},{"key":"e_1_3_2_1_40_1","volume-title":"Proceedings of the Symposium on High-Performance Interconnects (HOTI). IEEE, 1--8.","author":"Sharma Debendra Das","year":"2020","unstructured":"Debendra Das Sharma . 2020 . PCI Express\u00ae 6.0 Specification: A Low-Latency, High-Bandwidth, High-Reliability, and Cost-Effective Interconnect With 64.0 GT\/s PAM-4 Signaling . In Proceedings of the Symposium on High-Performance Interconnects (HOTI). IEEE, 1--8. Debendra Das Sharma. 2020. PCI Express\u00ae 6.0 Specification: A Low-Latency, High-Bandwidth, High-Reliability, and Cost-Effective Interconnect With 64.0 GT\/s PAM-4 Signaling. In Proceedings of the Symposium on High-Performance Interconnects (HOTI). IEEE, 1--8."},{"key":"e_1_3_2_1_42_1","volume-title":"Geng Daniel Liu, and Wen-mei W Hwu","author":"Stratton John A","year":"2012","unstructured":"John A Stratton , Christopher Rodrigues , I- Jui Sung , Nady Obeid , Li-Wen Chang , Nasser Anssari , Geng Daniel Liu, and Wen-mei W Hwu . 2012 . Parboil : A Revised Benchmark Suite for Scientific and Commercial Throughput Computing. Technical Report. IMPACT-12-01, Center for Reliable and High-Performance Computing, University of Illinois at Urbana-Champaign. 29 pages. John A Stratton, Christopher Rodrigues, I-Jui Sung, Nady Obeid, Li-Wen Chang, Nasser Anssari, Geng Daniel Liu, and Wen-mei W Hwu. 2012. Parboil: A Revised Benchmark Suite for Scientific and Commercial Throughput Computing. Technical Report. IMPACT-12-01, Center for Reliable and High-Performance Computing, University of Illinois at Urbana-Champaign. 29 pages."},{"key":"e_1_3_2_1_43_1","volume-title":"Proceedings of the International Symposium on Networks-on-Chip (NOCS). IEEE, 201--210","author":"Sun Chen","year":"2012","unstructured":"Chen Sun , Chia-Hsin Owen Chen , George Kurian , Lan Wei , Jason Miller , Anant Agarwal , Li-Shiuan Peh , and Vladimir Stojanovic . 2012 . DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling . In Proceedings of the International Symposium on Networks-on-Chip (NOCS). IEEE, 201--210 . Chen Sun, Chia-Hsin Owen Chen, George Kurian, Lan Wei, Jason Miller, Anant Agarwal, Li-Shiuan Peh, and Vladimir Stojanovic. 2012. DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling. In Proceedings of the International Symposium on Networks-on-Chip (NOCS). IEEE, 201--210."},{"key":"e_1_3_2_1_44_1","volume-title":"DesignWare Library - Datapath and Building Block IP. https:\/\/www.synopsys.com\/dw\/buildingblock.php. [Online","year":"2023","unstructured":"Synopsys. 2022. DesignWare Library - Datapath and Building Block IP. https:\/\/www.synopsys.com\/dw\/buildingblock.php. [Online ; accessed 2023 -02-15]. Synopsys. 2022. DesignWare Library - Datapath and Building Block IP. https:\/\/www.synopsys.com\/dw\/buildingblock.php. [Online; accessed 2023-02-15]."},{"key":"e_1_3_2_1_45_1","volume-title":"Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 698--707","author":"Tabbakh Abdulaziz","year":"2017","unstructured":"Abdulaziz Tabbakh , Murali Annavaram , and Xuehai Qian . 2017 . Power Efficient Sharing-Aware GPU Data Management . In Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 698--707 . Abdulaziz Tabbakh, Murali Annavaram, and Xuehai Qian. 2017. Power Efficient Sharing-Aware GPU Data Management. In Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 698--707."},{"key":"e_1_3_2_1_46_1","volume-title":"Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT). IEEE, 166--179","author":"Tsai Po-An","year":"2017","unstructured":"Po-An Tsai , Nathan Beckmann , and Daniel Sanchez . 2017 . Nexus: A New Approach to Replication in Distributed Shared Caches . In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT). IEEE, 166--179 . Po-An Tsai, Nathan Beckmann, and Daniel Sanchez. 2017. Nexus: A New Approach to Replication in Distributed Shared Caches. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT). IEEE, 166--179."},{"key":"e_1_3_2_1_47_1","volume-title":"Proceedings of the International Symposium on Microarchitecture (MICRO). IEEE, 339--351","author":"Young Vinson","year":"2018","unstructured":"Vinson Young , Aamer Jaleel , Evgeny Bolotin , Eiman Ebrahimi , David Nellans , and Oreste Villa . 2018 . Combining HW\/SW Mechanisms to Improve NUMA Performance of Multi-GPU Systems . In Proceedings of the International Symposium on Microarchitecture (MICRO). IEEE, 339--351 . Vinson Young, Aamer Jaleel, Evgeny Bolotin, Eiman Ebrahimi, David Nellans, and Oreste Villa. 2018. Combining HW\/SW Mechanisms to Improve NUMA Performance of Multi-GPU Systems. In Proceedings of the International Symposium on Microarchitecture (MICRO). IEEE, 339--351."},{"key":"e_1_3_2_1_48_1","volume-title":"Proceedings of the International Symposium on Computer Architecture (ISCA). IEEE, 411--423","author":"Zhao Xia","year":"2019","unstructured":"Xia Zhao , Almutaz Adileh , Zhibin Yu , Zhiying Wang , Aamer Jaleel , and Lieven Eeckhout . 2019 . Adaptive Memory-Side Last-Level GPU Caching . In Proceedings of the International Symposium on Computer Architecture (ISCA). IEEE, 411--423 . Xia Zhao, Almutaz Adileh, Zhibin Yu, Zhiying Wang, Aamer Jaleel, and Lieven Eeckhout. 2019. Adaptive Memory-Side Last-Level GPU Caching. In Proceedings of the International Symposium on Computer Architecture (ISCA). IEEE, 411--423."},{"key":"e_1_3_2_1_49_1","volume-title":"Proceedings of the International Symposium on Microarchitecture (MICRO). IEEE, 967--980","author":"Zhao Xia","year":"2020","unstructured":"Xia Zhao , Magnus Jahre , and Lieven Eeckhout . 2020 . Selective Replication in Memory-Side GPU Caches . In Proceedings of the International Symposium on Microarchitecture (MICRO). IEEE, 967--980 . Xia Zhao, Magnus Jahre, and Lieven Eeckhout. 2020. Selective Replication in Memory-Side GPU Caches. In Proceedings of the International Symposium on Microarchitecture (MICRO). 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