{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,26]],"date-time":"2025-06-26T04:52:40Z","timestamp":1750913560310,"version":"3.41.0"},"reference-count":30,"publisher":"Association for Computing Machinery (ACM)","issue":"5","license":[{"start":{"date-parts":[[2023,9,9]],"date-time":"2023-09-09T00:00:00Z","timestamp":1694217600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"DARPA IDEA program"},{"name":"SPAWAR Contract","award":["N660011824048"],"award-info":[{"award-number":["N660011824048"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2023,9,30]]},"abstract":"<jats:p>\n            Well island generation and well tap placement is an important problem in analog\/mixed-signal (AMS) circuits. Well taps can only prevent latchups within a certain radius of influence within a well island, and hence must be appropriately inserted to cover all devices. However, existing automated AMS layout paradigms typically defer the insertion of well taps and creation of well islands to a post-processing step after placement. This alters the placement, resulting in increased area and wire length, as well as circuit performance degradation. Therefore, there is a strong need for a solution that generates well islands and inserts well taps\n            <jats:italic>during placement<\/jats:italic>\n            so the placer can account for well overheads in optimizing placement metrics. In this work, we propose a modular solution using a graph-based optimization scheme that can be used within multiple placement paradigms with minimal intrusion. We demonstrate the integration of this scheme into stochastic, analytical, and designer-driven row-based placement. The method is demonstrated in advanced FinFET technologies. Layouts generated using this scheme show better area, wire length, and performance metrics at the cost of a marginal runtime degradation when compared to the post-processing approach. Using our scheme, there is an average improvement of 3% and 4% and a maximum improvement of 23% and 11% in area and wirelength, respectively, of layouts of various classes of AMS circuits at the cost of 17% average and 29% maximum increase in total runtime.\n          <\/jats:p>","DOI":"10.1145\/3580477","type":"journal-article","created":{"date-parts":[[2023,3,13]],"date-time":"2023-03-13T14:01:49Z","timestamp":1678716109000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog\/Mixed-signal Layouts"],"prefix":"10.1145","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9487-9340","authenticated-orcid":false,"given":"Ramprasath Srinivasa","family":"Gopalakrishnan","sequence":"first","affiliation":[{"name":"University of Minnesota, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5101-2421","authenticated-orcid":false,"given":"Meghna","family":"Madhusudan","sequence":"additional","affiliation":[{"name":"University of Minnesota, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9250-9642","authenticated-orcid":false,"given":"Arvind K.","family":"Sharma","sequence":"additional","affiliation":[{"name":"University of Minnesota, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7548-9064","authenticated-orcid":false,"given":"Jitesh","family":"Poojary","sequence":"additional","affiliation":[{"name":"University of Minnesota, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0715-0859","authenticated-orcid":false,"given":"Soner","family":"Yaldiz","sequence":"additional","affiliation":[{"name":"Intel Labs, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7691-566X","authenticated-orcid":false,"given":"Ramesh","family":"Harjani","sequence":"additional","affiliation":[{"name":"University of Minnesota, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0248-5403","authenticated-orcid":false,"given":"Steven M.","family":"Burns","sequence":"additional","affiliation":[{"name":"Intel Labs, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5353-2364","authenticated-orcid":false,"given":"Sachin S.","family":"Sapatnekar","sequence":"additional","affiliation":[{"name":"University of Minnesota, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,9,9]]},"reference":[{"unstructured":"P. Sriram. 2018. Cadence Virtuoso: Doing Placement in a Row-based Environment. Retrieved from https:\/\/community.cadence.com\/cadence_blogs_8\/b\/cic\/posts\/virtuosity-doing-layout-in-a-row-based-environment.","key":"e_1_3_2_2_2"},{"doi-asserted-by":"publisher","key":"e_1_3_2_3_2","DOI":"10.1109\/ICCAD.2000.896443"},{"doi-asserted-by":"publisher","key":"e_1_3_2_4_2","DOI":"10.1109\/ASPDAC.2003.1195124"},{"unstructured":"Michel Berkelaar Kjell Eikland and Peter Notebaert. 2004. lp_solve 5.5 Open source (Mixed-Integer) Linear Programming system. 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