{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,2]],"date-time":"2026-07-02T23:33:49Z","timestamp":1783035229159,"version":"3.54.6"},"reference-count":37,"publisher":"Association for Computing Machinery (ACM)","issue":"2","license":[{"start":{"date-parts":[[2023,6,20]],"date-time":"2023-06-20T00:00:00Z","timestamp":1687219200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"NSF","award":["1907401"],"award-info":[{"award-number":["1907401"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Parallel Comput."],"published-print":{"date-parts":[[2023,6,30]]},"abstract":"<jats:p>\n            The current trend of performance growth in HPC systems is accompanied by a massive increase in energy consumption. In this article, we introduce GreenMD, an energy-efficient framework for heterogeneous systems for LU factorization utilizing multi-GPUs. LU factorization is a crucial kernel from the MAGMA library, which is highly optimized. Our aim is to apply DVFS to this application by leveraging slacks intelligently on both CPUs and multiple GPUs. To predict the slack times, accurate performance models are developed separately for both CPUs and GPUs based on the algorithmic knowledge and manufacturer\u2019s specifications. Since DVFS does not reduce static energy consumption, we also develop undervolting techniques for both CPUs and GPUs. Reducing voltage below threshold values may give rise to errors; hence, we extract the minimum safe voltages (\n            <jats:italic>\n              V\n              <jats:sub>safeMin<\/jats:sub>\n            <\/jats:italic>\n            ) for the CPUs and GPUs utilizing a low overhead profiling phase and apply them before execution. It is shown that GreenMD improves the CPU, GPU, and total energy about 59%, 21%, and 31%, respectively, while delivering similar performance to the state-of-the-art linear algebra MAGMA library.\n          <\/jats:p>","DOI":"10.1145\/3583590","type":"journal-article","created":{"date-parts":[[2023,2,17]],"date-time":"2023-02-17T11:58:34Z","timestamp":1676635114000},"page":"1-23","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":7,"title":["GreenMD: Energy-efficient Matrix Decomposition on Heterogeneous Multi-GPU Systems"],"prefix":"10.1145","volume":"10","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9637-6576","authenticated-orcid":false,"given":"Hadi","family":"Zamani","sequence":"first","affiliation":[{"name":"University of California, Riverside, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8759-0458","authenticated-orcid":false,"given":"Laxmi","family":"Bhuyan","sequence":"additional","affiliation":[{"name":"University of California, Riverside, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1905-9171","authenticated-orcid":false,"given":"Jieyang","family":"Chen","sequence":"additional","affiliation":[{"name":"Oak Ridge National Laboratory, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2578-4940","authenticated-orcid":false,"given":"Zizhong","family":"Chen","sequence":"additional","affiliation":[{"name":"University of California, Riverside, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2023,6,20]]},"reference":[{"key":"e_1_3_1_2_2","unstructured":"MSI Afterburner. [n. d.]. http:\/\/goo.gl\/fs2pti."},{"key":"e_1_3_1_3_2","doi-asserted-by":"crossref","unstructured":"R. Begum M. Hempstead G. P. Srinivasa and G. Challen. 2016. Algorithms for CPU and DRAM DVFS under inefficiency constraints. IEEE 34th International Conference on Computer Design (ICCD\u201916) 161\u2013168.","DOI":"10.1109\/ICCD.2016.7753276"},{"key":"e_1_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.4143"},{"key":"e_1_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1145\/1837853.1693484"},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2019803"},{"key":"e_1_3_1_7_2","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2018.00071"},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2016.56"},{"key":"e_1_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.1145\/155332.155333"},{"key":"e_1_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870912"},{"key":"e_1_3_1_11_2","doi-asserted-by":"crossref","first-page":"958","DOI":"10.1109\/IPDPSW.2014.109","volume-title":"2014 IEEE International Parallel Distributed Processing Symposium Workshops","author":"Donfack S.","year":"2014","unstructured":"S. Donfack, S. Tomov, and J. Dongarra. 2014. Dynamically balanced synchronization-avoiding LU factorization with multicore and GPUs. In 2014 IEEE International Parallel Distributed Processing Symposium Workshops. 958\u2013965."},{"key":"e_1_3_1_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2019.8854386"},{"key":"e_1_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.parco.2018.02.001"},{"key":"e_1_3_1_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2019.2917181"},{"key":"e_1_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815998"},{"key":"e_1_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.1109\/GreenCom-CPSCom.2010.143"},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830811"},{"key":"e_1_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.1145\/2508148.2485964"},{"key":"e_1_3_1_19_2","volume-title":"Workshop on Silicon Errors in Logic-System Effects (SELSE\u201914)","author":"Leng Jingwen","year":"2014","unstructured":"Jingwen Leng, Yazhou Zu, and Vijay Janapa Reddi. 2014. Energy efficiency benefits of reducing the voltage guardband on the Kepler GPU architecture. In Workshop on Silicon Errors in Logic-System Effects (SELSE\u201914)."},{"key":"e_1_3_1_20_2","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627605"},{"key":"e_1_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2015.08.004"},{"key":"e_1_3_1_22_2","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2015.2440219"},{"key":"e_1_3_1_23_2","doi-asserted-by":"publisher","DOI":"10.1145\/2525526.2525852"},{"key":"e_1_3_1_24_2","unstructured":"R. M. Miller. 2013. Exascale computing. https:\/\/www.datacenterknowledge.com\/archives\/2010\/12\/10\/exascale-computing-gigawatts-of-power."},{"key":"e_1_3_1_25_2","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830826"},{"key":"e_1_3_1_26_2","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124537"},{"key":"e_1_3_1_27_2","unstructured":"Antoine Petitet. 2004. HPL-a portable implementation of the high-performance Linpack benchmark for distributed-memory computers. http:\/\/www.netlib.org\/benchmark\/hpl\/."},{"key":"e_1_3_1_28_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2606579"},{"key":"e_1_3_1_29_2","doi-asserted-by":"publisher","DOI":"10.1145\/1542275.1542340"},{"key":"e_1_3_1_30_2","doi-asserted-by":"publisher","DOI":"10.1145\/1362622.1362688"},{"key":"e_1_3_1_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2007.913186"},{"key":"e_1_3_1_32_2","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2013.73"},{"key":"e_1_3_1_33_2","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2015.108"},{"key":"e_1_3_1_34_2","doi-asserted-by":"publisher","DOI":"10.1145\/3307772.3328315"},{"key":"e_1_3_1_35_2","doi-asserted-by":"publisher","DOI":"10.1145\/3330345.3330373"},{"key":"e_1_3_1_36_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749745"},{"key":"e_1_3_1_37_2","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830824"},{"key":"e_1_3_1_38_2","first-page":"308","volume-title":"2015 48th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO\u201915)","author":"Zu Yazhou","year":"2015","unstructured":"Yazhou Zu, Charles R. Lefurgy, Jingwen Leng, Matthew Halpern, Michael S. Floyd, and Vijay Janapa Reddi. 2015. Adaptive guardband scheduling to improve system-level efficiency of the POWER7+. In 2015 48th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO\u201915). IEEE, 308\u2013321."}],"container-title":["ACM Transactions on Parallel Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3583590","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3583590","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3583590","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T16:37:54Z","timestamp":1750178274000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3583590"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,6,20]]},"references-count":37,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2023,6,30]]}},"alternative-id":["10.1145\/3583590"],"URL":"https:\/\/doi.org\/10.1145\/3583590","relation":{},"ISSN":["2329-4949","2329-4957"],"issn-type":[{"value":"2329-4949","type":"print"},{"value":"2329-4957","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,6,20]]},"assertion":[{"value":"2022-09-07","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2022-12-24","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-06-20","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}