{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,16]],"date-time":"2026-05-16T00:03:32Z","timestamp":1778889812402,"version":"3.51.4"},"publisher-location":"New York, NY, USA","reference-count":27,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,6,5]],"date-time":"2023-06-05T00:00:00Z","timestamp":1685923200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["2153394"],"award-info":[{"award-number":["2153394"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,6,5]]},"DOI":"10.1145\/3583781.3590233","type":"proceedings-article","created":{"date-parts":[[2023,5,31]],"date-time":"2023-05-31T22:40:19Z","timestamp":1685572819000},"page":"697-702","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":8,"title":["System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-4623-6940","authenticated-orcid":false,"given":"Kaniz","family":"Mishty","sequence":"first","affiliation":[{"name":"Auburn University, Auburn, AL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0468-7810","authenticated-orcid":false,"given":"Mehdi","family":"Sadi","sequence":"additional","affiliation":[{"name":"Auburn University, Auburn, AL, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,6,5]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2015. High-Bandwidth Memory(HBM). Retrieved January 2 2023 from https: \/\/www.amd.com\/system\/files\/documents\/high-bandwidth-memory-hbm.pdf"},{"key":"e_1_3_2_1_2_1","volume-title":"Heterogeneous Integration Roadmap. Retrieved","year":"2023","unstructured":"2021. Heterogeneous Integration Roadmap. Retrieved January 2, 2023 from https:\/\/eps.ieee.org\/technology\/heterogeneous-integration-roadmap\/2021-edition.html"},{"key":"e_1_3_2_1_3_1","volume-title":"2019 IEEE 69th Electronic Components and Technology Conference.","author":"Chen F.C.","unstructured":"Chen, F.C. et al. 2019. System on Integrated Chips (SoICTM) for 3D Heterogeneous Integration. In 2019 IEEE 69th Electronic Components and Technology Conference."},{"key":"e_1_3_2_1_4_1","volume-title":"Ayse et al","author":"Coskun","year":"2022","unstructured":"Coskun, Ayse et al. 2022. Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems. In 2020 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. 39."},{"key":"e_1_3_2_1_5_1","unstructured":"Peter I. Frazier. 2018. A Tutorial on Bayesian Optimization. arXiv:arXiv:1807.02811"},{"key":"e_1_3_2_1_6_1","volume-title":"2020 IEEE International Solid-State Circuits Conference. 144--146","author":"Gomes","unstructured":"Gomes, Wilfred et al. 2020. 8.1 Lakefield and Mobility Compute: A 3D Stacked 10nm and 22FFL Hybrid Processor System in 12\u00d712mm2, 1mm Package-on-Package. In 2020 IEEE International Solid-State Circuits Conference. 144--146."},{"key":"e_1_3_2_1_7_1","volume-title":"Designs of Communication Circuits for Side-by-Side and Stacked Chiplets. In ISSCC 2021 Forums.","author":"Kenny Cheng-Hsiang Hsieh","year":"2021","unstructured":"Kenny Cheng-Hsiang Hsieh. 2021. Designs of Communication Circuits for Side-by-Side and Stacked Chiplets. In ISSCC 2021 Forums."},{"key":"e_1_3_2_1_8_1","volume-title":"Hybrid Sparse-Dense Accelerator for Personalized Recommendations. In 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture. IEEE Computer Society","author":"Hwang","unstructured":"Hwang, Ranggi et al. 2020. Centaur: A Chiplet-based, Hybrid Sparse-Dense Accelerator for Personalized Recommendations. In 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture. IEEE Computer Society, Los Alamitos, CA, USA, 968--981."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993637"},{"key":"e_1_3_2_1_10_1","volume-title":"Systems Software. In 2022 IEEE Hot Chips 34 Symposium. 1--29","author":"Hong Jiang","year":"2022","unstructured":"Hong Jiang. 2022. Intel's Ponte Vecchio GPU: Architecture, Systems Software. In 2022 IEEE Hot Chips 34 Symposium. 1--29."},{"key":"e_1_3_2_1_11_1","volume-title":"Sheng-Chun et al","author":"Kao","year":"2020","unstructured":"Kao, Sheng-Chun et al. 2020. ConfuciuX: Autonomous Hardware Resource Assignment for DNN Accelerators using Reinforcement Learning. arXiv:2009.02010"},{"key":"e_1_3_2_1_12_1","volume-title":"Srivatsan et al","author":"Krishnan","year":"2022","unstructured":"Krishnan, Srivatsan et al. 2022. Multi-Agent Reinforcement Learning for Micro- processor Design Space Exploration. arXiv:2211.16385"},{"key":"e_1_3_2_1_13_1","volume-title":"Aviral et al","author":"Kumar","year":"2022","unstructured":"Kumar, Aviral et al. 2022. DATA-DRIVEN OFFLINE OPTIMIZATION FOR ARCHITECTING HARDWARE ACCELERATORS. arXiv:2110.11346"},{"key":"e_1_3_2_1_14_1","volume-title":"Heterogeneous System-Level Package Integration - Trends and Challenges. In 2020 IEEE Symposium on VLSI Technology. 1--2.","author":"Lee Frank J. C.","unstructured":"Lee, Frank J. C. et al. 2020. Heterogeneous System-Level Package Integration - Trends and Challenges. In 2020 IEEE Symposium on VLSI Technology. 1--2."},{"key":"e_1_3_2_1_15_1","volume-title":"2019 Symposium on VLSI Circuits. C28-C29","author":"Lin","unstructured":"Lin, Mu-Shan et al. 2019. A 7nm 4GHz Arm\u00ae-core-based CoWoS\u00ae Chiplet Design for High Performance Computing. In 2019 Symposium on VLSI Circuits. C28-C29."},{"key":"e_1_3_2_1_16_1","volume-title":"2020 IEEE International Symposium on High Performance Computer Architecture. 99--110","author":"Lin","unstructured":"Lin, Ting-Ru et al. 2020. A Deep Reinforcement Learning Framework for Archi-tectural Exploration: A Routerless NoC Case Study. In 2020 IEEE International Symposium on High Performance Computer Architecture. 99--110."},{"key":"e_1_3_2_1_17_1","volume-title":"High Bandwidth Packaging Interconnect. In 2016 IEEE 66th Electronic Components and Technology Conference. 557--565","author":"Mahajan","unstructured":"Mahajan, Ravi et al. 2016. Embedded Multi-die Interconnect Bridge (EMIB) -- A High Density, High Bandwidth Packaging Interconnect. In 2016 IEEE 66th Electronic Components and Technology Conference. 557--565."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3105958"},{"key":"e_1_3_2_1_19_1","volume-title":"2020 IEEE International Solid-State Circuits Conference-(ISSCC). IEEE, 44--45","author":"Naffziger","unstructured":"Naffziger, Samuel et al. 2020. 2.2 AMD chiplet architecture for high-performance server and desktop products. In 2020 IEEE International Solid-State Circuits Conference-(ISSCC). IEEE, 44--45."},{"key":"e_1_3_2_1_20_1","volume-title":"Processor Families: Industrial Product. In 2021 ACM\/IEEE 48th Annual International Symposium on Computer Architecture. 57--70","author":"Naffziger","unstructured":"Naffziger, Samuel et al. 2021. Pioneering Chiplet Technology and Design for the AMD EPYC? and Ryzen? Processor Families: Industrial Product. In 2021 ACM\/IEEE 48th Annual International Symposium on Computer Architecture. 57--70."},{"key":"e_1_3_2_1_21_1","unstructured":"John Park. 2022. 3D-IC Design Challenges and Requirements. In Cadence."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.5555\/1953048.2078195"},{"key":"e_1_3_2_1_23_1","volume-title":"Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture. 14--27","author":"Shao Yakun","unstructured":"Shao, Yakun Sophia et al. 2019. Simba: Scaling deep-learning inference with multi- chip-module-based architecture. In Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture. 14--27."},{"key":"e_1_3_2_1_24_1","volume-title":"NN-Baton: DNN Workload Orchestration and Chiplet Granularity Exploration for Multichip Accelerators. In 2021 ACM\/IEEE 48th Annual International Symposium on Computer Architecture. 1013--1026","author":"Tan","unstructured":"Tan, Zhanhong et al. 2021. NN-Baton: DNN Workload Orchestration and Chiplet Granularity Exploration for Multichip Accelerators. In 2021 ACM\/IEEE 48th Annual International Symposium on Computer Architecture. 1013--1026."},{"key":"e_1_3_2_1_25_1","volume-title":"2022 IEEE International Symposium on High-Performance Computer Architecture. 1198--1210","author":"Wang","unstructured":"Wang, Tianqi et al. 2022. Application Defined On-chip Networks for Hetero- geneous Chiplets: An Implementation Perspective. In 2022 IEEE International Symposium on High-Performance Computer Architecture. 1198--1210."},{"key":"e_1_3_2_1_26_1","volume-title":"2022 IEEE International Symposium on High- Performance Computer Architecture. 986--1000","author":"Wu","unstructured":"Wu, Yibo et al. 2022. Upward Packet Popup for Deadlock Freedom in Mod- ular Chiplet-Based Systems. In 2022 IEEE International Symposium on High- Performance Computer Architecture. 986--1000."},{"key":"e_1_3_2_1_27_1","volume-title":"Dan et al","author":"Zhang","year":"2022","unstructured":"Zhang, Dan et al. 2022. A Full-Stack Search Technique for Domain Optimized Deep Learning Accelerators. arXiv:2105.12842"}],"event":{"name":"GLSVLSI '23: Great Lakes Symposium on VLSI 2023","location":"Knoxville TN USA","acronym":"GLSVLSI '23","sponsor":["SIGDA ACM Special Interest Group on Design Automation"]},"container-title":["Proceedings of the Great Lakes Symposium on VLSI 2023"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3583781.3590233","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3583781.3590233","content-type":"application\/pdf","content-version":"vor","intended-application":"syndication"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3583781.3590233","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T16:37:05Z","timestamp":1750178225000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3583781.3590233"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,6,5]]},"references-count":27,"alternative-id":["10.1145\/3583781.3590233","10.1145\/3583781"],"URL":"https:\/\/doi.org\/10.1145\/3583781.3590233","relation":{},"subject":[],"published":{"date-parts":[[2023,6,5]]},"assertion":[{"value":"2023-06-05","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}