{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:10:47Z","timestamp":1750219847152,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":15,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,6,5]],"date-time":"2023-06-05T00:00:00Z","timestamp":1685923200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,6,5]]},"DOI":"10.1145\/3583781.3590317","type":"proceedings-article","created":{"date-parts":[[2023,5,31]],"date-time":"2023-05-31T22:40:19Z","timestamp":1685572819000},"page":"477-481","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Verilog-A Implementation of Generic Defect Templates for Analog Fault Injection"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0656-9786","authenticated-orcid":false,"given":"Nicola","family":"Dall'Ora","sequence":"first","affiliation":[{"name":"University of Verona, Verona, Italy"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0480-4607","authenticated-orcid":false,"given":"Sadia","family":"Azam","sequence":"additional","affiliation":[{"name":"University of Verona, Verona, Italy"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9739-6501","authenticated-orcid":false,"given":"Enrico","family":"Fraccaroli","sequence":"additional","affiliation":[{"name":"University of North Carolina at Chapel Hill, Chapel Hill, NC, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0980-5238","authenticated-orcid":false,"given":"Renaud","family":"Gillon","sequence":"additional","affiliation":[{"name":"Sydelity B.V., Kruisem, Belgium"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4404-5791","authenticated-orcid":false,"given":"Franco","family":"Fummi","sequence":"additional","affiliation":[{"name":"University of Verona, Verona, Italy"}]}],"member":"320","published-online":{"date-parts":[[2023,6,5]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/BMAS.2010.6156601"},{"volume-title":"A Common Manipulation Framework for Transistor-Level Languages. In 2021 Forum on specification & Design Languages (FDL)","author":"Dall'Ora Nicola","key":"e_1_3_2_1_2_1","unstructured":"Nicola Dall'Ora, Sadia Azam, Enrico Fraccaroli, Andr\u00e9 Alberts, and Franco Fummi. 2021. A Common Manipulation Framework for Transistor-Level Languages. In 2021 Forum on specification & Design Languages (FDL). IEEE, 01-07."},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS52668.2021.9417072"},{"key":"e_1_3_2_1_4_1","unstructured":"Siemens EDA. 2023. Tessent DefectSim. https:\/\/eda.sw.siemens.com\/en-US\/ic\/ tessent\/test\/defectsim\/"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2016.7805830"},{"volume-title":"IEEE-SA Standards Board P2427\/D0.13 Draft Standard for Analog Defect Modeling and Coverage","author":"IEEE.","key":"e_1_3_2_1_6_1","unstructured":"IEEE. 2019. IEEE-SA Standards Board P2427\/D0.13 Draft Standard for Analog Defect Modeling and Coverage. IEEE. https:\/\/standards.ieee.org\/project\/2427.html"},{"key":"e_1_3_2_1_7_1","unstructured":"ISO 2011. ISO 26262 -- Road vehicles -- Functional safety. ISO."},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1023\/B:ALOG.0000024065.22617.5a"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2019.8780332"},{"key":"e_1_3_2_1_10_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.841071"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPCES.2014.7062809"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/ETS48528.2020.9131581"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2616159"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2017.8242079"},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2011.5783780"}],"event":{"name":"GLSVLSI '23: Great Lakes Symposium on VLSI 2023","sponsor":["SIGDA ACM Special Interest Group on Design Automation"],"location":"Knoxville TN USA","acronym":"GLSVLSI '23"},"container-title":["Proceedings of the Great Lakes Symposium on VLSI 2023"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3583781.3590317","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3583781.3590317","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T16:46:59Z","timestamp":1750178819000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3583781.3590317"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,6,5]]},"references-count":15,"alternative-id":["10.1145\/3583781.3590317","10.1145\/3583781"],"URL":"https:\/\/doi.org\/10.1145\/3583781.3590317","relation":{},"subject":[],"published":{"date-parts":[[2023,6,5]]},"assertion":[{"value":"2023-06-05","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}