{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,11]],"date-time":"2026-06-11T15:57:48Z","timestamp":1781193468844,"version":"3.54.1"},"reference-count":48,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2023,6,21]],"date-time":"2023-06-21T00:00:00Z","timestamp":1687305600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100000266","name":"UK Engineering and Physical Sciences Research Council","doi-asserted-by":"crossref","award":["EP\/N509796\/1"],"award-info":[{"award-number":["EP\/N509796\/1"]}],"id":[{"id":"10.13039\/501100000266","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Reconfigurable Technol. Syst."],"published-print":{"date-parts":[[2023,9,30]]},"abstract":"<jats:p>Partial reconfiguration (PR) is a key enabler to the design and development of adaptive systems on modern Field Programmable Gate Array (FPGA) Systems-on-Chip (SoCs), allowing hardware to be adapted dynamically at runtime. Vendor-supported PR infrastructure is performance-limited and blocking, drivers entail complex memory management, and software\/hardware design requires bespoke knowledge of the underlying hardware. This article presents ZyPR: a complete end-to-end framework that provides high-performance reconfiguration of hardware from within a software abstraction in the Linux userspace, automating the process of building PR applications with support for the Xilinx Zynq and Zynq UltraScale+ architectures, aimed at enabling non-expert application designers to leverage PR for edge applications. We compare ZyPR against traditional vendor tooling for PR management as well as recent open source tools that support PR under Linux. The framework provides a high-performance runtime along with low overhead for its provided abstractions. We introduce improvements to our previous work, increasing the provisioning throughput for PR bitstreams on the Zynq Ultrascale+ by \u00a02\u00d7 and \u00a05.4\u00d7 compared to Xilinx\u2019s FPGA Manager.<\/jats:p>","DOI":"10.1145\/3585521","type":"journal-article","created":{"date-parts":[[2023,2,27]],"date-time":"2023-02-27T12:03:47Z","timestamp":1677499427000},"page":"1-33","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":9,"title":["ZyPR: End-to-end Build Tool and Runtime Manager for Partial Reconfiguration of FPGA SoCs at the Edge"],"prefix":"10.1145","volume":"16","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7077-2466","authenticated-orcid":false,"given":"Alex R.","family":"Bucknall","sequence":"first","affiliation":[{"name":"University of Warwick, United Kingdom"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0568-5048","authenticated-orcid":false,"given":"Suhaib A.","family":"Fahmy","sequence":"additional","affiliation":[{"name":"King Abdullah University of Science and Technology (KAUST), Saudi Arabia"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2023,6,21]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2018.8541369"},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2013.110"},{"key":"e_1_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272532"},{"key":"e_1_3_1_5_2","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1109\/FCCM.2012.17","volume-title":"IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201912)","author":"Beckhoff Christian","year":"2012","unstructured":"Christian Beckhoff, Dirk Koch, and Jim Torresen. 2012. Go Ahead: A partial reconfiguration framework. In IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201912). 37\u201344."},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-36424-2_26"},{"key":"e_1_3_1_7_2","doi-asserted-by":"crossref","unstructured":"Alex R. Bucknall and Suhaib A. Fahmy. 2021. Runtime Abstraction for Autonomous Adaptive Systems on Reconfigurable Hardware. In Design Automation Test in Europe Conference Exhibition (DATE\u201921) . 1616\u20131621.","DOI":"10.23919\/DATE51398.2021.9474199"},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT47387.2019.00042"},{"key":"e_1_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT51103.2020.00037"},{"key":"e_1_3_1_10_2","first-page":"109","volume-title":"IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201914)","author":"Byma Stuart","year":"2014","unstructured":"Stuart Byma, J. Gregory Steffan, Hadi Bannazadeh, Alberto Leon Garcia, and Paul Chow. 2014. FPGAs in the cloud: Booting virtualized hardware accelerators with openstack. In IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201914). 109\u2013116."},{"key":"e_1_3_1_11_2","first-page":"309","volume-title":"IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201919)","author":"Deak Norbert","year":"2019","unstructured":"Norbert Deak, Octavian Cret, and Horia Hedesiu. 2019. Efficient FPGA floorplanning for partial reconfiguration-based applications. In IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201919). 309\u2013309."},{"key":"e_1_3_1_12_2","first-page":"253","volume-title":"International Symposium on Applied Reconfigurable Computing","author":"Duhem Fran\u00e7ois","year":"2011","unstructured":"Fran\u00e7ois Duhem, Fabrice Muller, and Philippe Lorenzini. 2011. FaRM: Fast reconfiguration manager for reducing reconfiguration time overhead on FPGA. In International Symposium on Applied Reconfigurable Computing. Springer, 253\u2013260."},{"key":"e_1_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/CloudCom.2015.60"},{"key":"e_1_3_1_14_2","doi-asserted-by":"crossref","first-page":"174","DOI":"10.1109\/IPDPS.2011.139","volume-title":"IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum","author":"Hansen Simen Gimle","year":"2011","unstructured":"Simen Gimle Hansen, Dirk Koch, and Jim Torresen. 2011. High speed partial run-time reconfiguration using enhanced ICAP hard macro. In IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum. 174\u2013180."},{"key":"e_1_3_1_15_2","article-title":"u-dma-buf","author":"Ichiro Kawazome","year":"2015","unstructured":"Kawazome Ichiro. 2015. u-dma-buf. Retrieved from https:\/\/github.com\/ikwzm\/udmabuf.","journal-title":"Retrieved from https:\/\/github.com\/ikwzm\/udmabuf"},{"key":"e_1_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2018.00031"},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3023548"},{"key":"e_1_3_1_18_2","article-title":"Edalize: Python Library for Interacting with EDA Tools","author":"Kindgren Olof","year":"2018","unstructured":"Olof Kindgren. 2018. Edalize: Python Library for Interacting with EDA Tools. Retrieved from: https:\/\/github.com\/olofk\/edalize.","journal-title":"Retrieved from: https:\/\/github.com\/olofk\/edalize"},{"key":"e_1_3_1_19_2","article-title":"FuseSoC: Package Manager and Build Abstraction Tool for FPGA\/ASIC Development","author":"Kindgren Olof","year":"2018","unstructured":"Olof Kindgren. 2018. FuseSoC: Package Manager and Build Abstraction Tool for FPGA\/ASIC Development. Retrieved from: https:\/\/github.com\/olofk\/fusesoc.","journal-title":"Retrieved from: https:\/\/github.com\/olofk\/fusesoc"},{"key":"e_1_3_1_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT51103.2020.00046"},{"key":"e_1_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723190"},{"key":"e_1_3_1_22_2","doi-asserted-by":"publisher","DOI":"10.1051\/epjconf\/201921407029"},{"key":"e_1_3_1_23_2","article-title":"Xilinx AXI DMA Linux Driver","author":"Perez Brendan","year":"2015","unstructured":"Brendan Perez and Jared Choi. 2015. Xilinx AXI DMA Linux Driver. Retrieved from: https:\/\/github.com\/bperez77\/xilinx_axidma.","journal-title":"Retrieved from: https:\/\/github.com\/bperez77\/xilinx_axidma"},{"key":"e_1_3_1_24_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT51103.2020.00038"},{"key":"e_1_3_1_25_2","first-page":"894","volume-title":"Design, Automation and Test in Europe Conference and Exhibition (DATE\u201917)","author":"Pham Khoa Dang","year":"2017","unstructured":"Khoa Dang Pham, Edson Horta, and Dirk Koch. 2017. BITMAN: A tool and API for FPGA bitstream manipulations. In Design, Automation and Test in Europe Conference and Exhibition (DATE\u201917). 894\u2013897."},{"key":"e_1_3_1_26_2","doi-asserted-by":"publisher","DOI":"10.1109\/DASIP.2018.8596910"},{"key":"e_1_3_1_27_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2562361"},{"key":"e_1_3_1_28_2","doi-asserted-by":"publisher","DOI":"10.3390\/s18061877"},{"key":"e_1_3_1_29_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2018.10.006"},{"key":"e_1_3_1_30_2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00038"},{"key":"e_1_3_1_31_2","doi-asserted-by":"crossref","unstructured":"Shanker Shreejith Kizhepatt Vipin Suhaib A. Fahmy and Martin Lukasiewycz. 2013. An approach for redundancy in FlexRay networks using FPGA partial reconfiguration. In Design Automation Test in Europe Conference and Exhibition (DATE\u201913) . 721\u2013724.","DOI":"10.7873\/DATE.2013.155"},{"key":"e_1_3_1_32_2","doi-asserted-by":"crossref","first-page":"451","DOI":"10.1007\/978-3-319-16214-0_42","volume-title":"Applied Reconfigurable Computing (Lecture Notes in Computer Science)","author":"Takamaeda-Yamazaki Shinya","year":"2015","unstructured":"Shinya Takamaeda-Yamazaki. 2015. Pyverilog: A Python-based hardware design processing toolkit for Verilog HDL. In Applied Reconfigurable Computing (Lecture Notes in Computer Science), Vol. 9040. Springer International Publishing, 451\u2013460."},{"issue":"4","key":"e_1_3_1_33_2","article-title":"FOS: A modular FPGA operating system for dynamic workloads","volume":"13","author":"Vaishnav Anuj","year":"2020","unstructured":"Anuj Vaishnav, Khoa Dang Pham, Joseph Powell, and Dirk Koch. 2020. FOS: A modular FPGA operating system for dynamic workloads. ACM Trans. Reconfig. Technol. Syst. 13, 4 (Sept.2020).","journal-title":"ACM Trans. Reconfig. Technol. Syst."},{"key":"e_1_3_1_34_2","first-page":"13","volume-title":"International Symposium on Applied Reconfigurable Computing","author":"Vipin Kizheppatt","year":"2012","unstructured":"Kizheppatt Vipin and Suhaib A Fahmy. 2012. Architecture-aware reconfiguration-centric floorplanning for partial reconfiguration. In International Symposium on Applied Reconfigurable Computing. Springer, 13\u201325."},{"key":"e_1_3_1_35_2","first-page":"202","volume-title":"IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201914)","author":"Vipin Kizheppatt","year":"2014","unstructured":"Kizheppatt Vipin and Suhaib A. Fahmy. 2014. Automated partial reconfiguration design for adaptive systems with CoPR for Zynq. In IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM\u201914). 202\u2013205."},{"key":"e_1_3_1_36_2","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2014.2314390"},{"key":"e_1_3_1_37_2","doi-asserted-by":"publisher","DOI":"10.1145\/3193827"},{"key":"e_1_3_1_38_2","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2020.2990924"},{"key":"e_1_3_1_39_2","article-title":"nmigen","year":"2018","unstructured":"Whitequark. 2018. nmigen. Retrieved from: https:\/\/github.com\/nmigen\/nmigen.","journal-title":"Retrieved from: https:\/\/github.com\/nmigen\/nmigen"},{"key":"e_1_3_1_40_2","unstructured":"Xilinx. 2020. Retrieved from: https:\/\/www.xilinx.com\/products\/design-tools\/vitis\/vitis-libraries\/vitis-vision.html."},{"key":"e_1_3_1_41_2","volume-title":"PG059: AXI Interconnect v2.1","author":"Xilinx Inc.","year":"2017","unstructured":"Xilinx Inc. 2017. PG059: AXI Interconnect v2.1. Xilinx Inc. v2.1."},{"key":"e_1_3_1_42_2","volume-title":"PG085: AXI4-Stream Infrastructure IP Suite v3.0","author":"Xilinx Inc.","year":"2018","unstructured":"Xilinx Inc. 2018. PG085: AXI4-Stream Infrastructure IP Suite v3.0. Xilinx Inc. v3.0."},{"key":"e_1_3_1_43_2","volume-title":"Python Productivity for Zynq","author":"Xilinx Inc.","year":"2020","unstructured":"Xilinx Inc. 2020. Python Productivity for Zynq. Xilinx Inc. http:\/\/pynq.io\/."},{"key":"e_1_3_1_44_2","volume-title":"UG1137: Zynq UltraScale+ MPSoC: Software Developers Guide","author":"Xilinx Inc.","year":"2020","unstructured":"Xilinx Inc. 2020. UG1137: Zynq UltraScale+ MPSoC: Software Developers Guide. Xilinx Inc. v12.0."},{"key":"e_1_3_1_45_2","volume-title":"UG909: Dynamic Function eXchange v2019.2","author":"Xilinx Inc.","year":"2020","unstructured":"Xilinx Inc. 2020. UG909: Dynamic Function eXchange v2019.2. Xilinx Inc. v2019.2."},{"key":"e_1_3_1_46_2","volume-title":"PG116: MicroBlaze Micro Controller System v3.0","author":"Xilinx Inc.","year":"2021","unstructured":"Xilinx Inc. 2021. PG116: MicroBlaze Micro Controller System v3.0. Xilinx Inc. v3.0."},{"key":"e_1_3_1_47_2","doi-asserted-by":"publisher","DOI":"10.1109\/RECONFIG.2018.8641703"},{"key":"e_1_3_1_48_2","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.3026189"},{"key":"e_1_3_1_49_2","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2943179"}],"container-title":["ACM Transactions on Reconfigurable Technology and Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3585521","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3585521","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T16:46:08Z","timestamp":1750178768000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3585521"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,6,21]]},"references-count":48,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2023,9,30]]}},"alternative-id":["10.1145\/3585521"],"URL":"https:\/\/doi.org\/10.1145\/3585521","relation":{},"ISSN":["1936-7406","1936-7414"],"issn-type":[{"value":"1936-7406","type":"print"},{"value":"1936-7414","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,6,21]]},"assertion":[{"value":"2022-07-21","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-02-10","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-06-21","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}