{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,8]],"date-time":"2026-02-08T19:35:24Z","timestamp":1770579324137,"version":"3.49.0"},"reference-count":20,"publisher":"Association for Computing Machinery (ACM)","issue":"5","license":[{"start":{"date-parts":[[2023,9,8]],"date-time":"2023-09-08T00:00:00Z","timestamp":1694131200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2023,9,30]]},"abstract":"<jats:p>In high-performance three-dimensional Integrated Circuits (3D ICs), clock networks consume a large portion of the full-chip power. However, no previous 3D IC work has ever optimized 3D clock networks for both power and performance simultaneously, which results in sub-optimal 3D designs. To overcome this issue, in this article, we propose a GNN-based flip-flop clustering algorithm that merges single-bit flip-flops into multi-bit flip-flops in an unsupervised manner, which jointly optimizes the power and performance metrics of clock networks. Moreover, we integrate our algorithm into the state-of-the-art 3D physical design flow and verify the integration, which leads to a better 3D full-chip design. Experimental results on eight industrial benchmarks demonstrate that the algorithm achieves improvements up to 18% in total power and 8.2% in performance over the state-of-the-art 3D flow.<\/jats:p>","DOI":"10.1145\/3588570","type":"journal-article","created":{"date-parts":[[2023,4,6]],"date-time":"2023-04-06T13:27:19Z","timestamp":1680787639000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["GNN-based Multi-bit Flip-flop Clustering and Post-clustering Design Optimization for Energy-efficient 3D ICs"],"prefix":"10.1145","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2897-7142","authenticated-orcid":false,"given":"Pruek","family":"Vanna-Iampikul","sequence":"first","affiliation":[{"name":"Georgia Institute of Technology, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1481-9167","authenticated-orcid":false,"given":"Yi-Chen","family":"Lu","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2246-1022","authenticated-orcid":false,"given":"Da Eun","family":"Shim","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2267-5282","authenticated-orcid":false,"given":"Sung Kyu","family":"Lim","sequence":"additional","affiliation":[{"name":"Georgia Institute of Technology, USA"}]}],"member":"320","published-online":{"date-parts":[[2023,9,8]]},"reference":[{"key":"e_1_3_1_2_2","first-page":"47","volume-title":"Proceedings of the International Symposium on Physical Design","author":"Park Heechun","year":"2020","unstructured":"Heechun Park et\u00a0al. 2020. Pseudo-3D approaches for commercial-grade RTL-to-GDS tool flow targeting monolithic 3D ICs. In Proceedings of the International Symposium on Physical Design. 47\u201354."},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2002.1016875"},{"key":"e_1_3_1_4_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2648839"},{"key":"e_1_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2019.8824801"},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1145\/3439706.3447049"},{"key":"e_1_3_1_7_2","doi-asserted-by":"crossref","DOI":"10.1002\/0471723703","volume-title":"Digital System Clocking: High-Performance and Low-Power Aspects (1st ed.)","author":"Oklobdzija Vojin G.","year":"2003","unstructured":"Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, and Nikola M. Nedovic. 2003. Digital System Clocking: High-Performance and Low-Power Aspects (1st ed.). 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Design of low-power structural FIR filter using data-driven clock gating and multibit flip-flops. J. Electr. Comput. Eng. (2020).","journal-title":"J. Electr. Comput. Eng."},{"key":"e_1_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.1145\/567270.567271"},{"key":"e_1_3_1_17_2","first-page":"1","volume-title":"Proceedings of the 57th ACM\/IEEE Design Automation Conference (DAC\u201920)","author":"Lu Yi-Chen","year":"2020","unstructured":"Yi-Chen Lu et\u00a0al. 2020. TP-GNN: A graph neural network framework for tier partitioning in monolithic 3D ICs. In Proceedings of the 57th ACM\/IEEE Design Automation Conference (DAC\u201920). IEEE, 1\u20136."},{"key":"e_1_3_1_18_2","first-page":"173","volume-title":"International Statistical and Optimization Perspectives Workshop \u201cSubspace, Latent Structure and Feature Selection.\u201d","author":"Rogers Jeremy","year":"2005","unstructured":"Jeremy Rogers and Steve Gunn. 2005. Identifying feature relevance using a random forest. In International Statistical and Optimization Perspectives Workshop \u201cSubspace, Latent Structure and Feature Selection.\u201d Springer, 173\u2013184."},{"key":"e_1_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.1145\/3439706.3447045"},{"key":"e_1_3_1_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2020.2978386"},{"key":"e_1_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00014"}],"container-title":["ACM Transactions on Design Automation of Electronic Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3588570","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3588570","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T16:47:13Z","timestamp":1750178833000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3588570"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,9,8]]},"references-count":20,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2023,9,30]]}},"alternative-id":["10.1145\/3588570"],"URL":"https:\/\/doi.org\/10.1145\/3588570","relation":{},"ISSN":["1084-4309","1557-7309"],"issn-type":[{"value":"1084-4309","type":"print"},{"value":"1557-7309","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,9,8]]},"assertion":[{"value":"2022-08-18","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-02-21","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-09-08","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}