{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,24]],"date-time":"2025-08-24T01:15:53Z","timestamp":1755998153225,"version":"3.41.0"},"publisher-location":"New York, NY, USA","reference-count":33,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,6,6]],"date-time":"2023-06-06T00:00:00Z","timestamp":1686009600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"DOI":"10.13039\/100000001","name":"NSF (National Science Foundation)","doi-asserted-by":"publisher","award":["CNS-1618497, CNS-1900803, CCF-2217395, CCF-2114319, NSF-1909099, CCF-2006542, and CCF-1763699"],"award-info":[{"award-number":["CNS-1618497, CNS-1900803, CCF-2217395, CCF-2114319, NSF-1909099, CCF-2006542, and CCF-1763699"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,6,6]]},"DOI":"10.1145\/3591195.3595267","type":"proceedings-article","created":{"date-parts":[[2023,6,6]],"date-time":"2023-06-06T20:32:43Z","timestamp":1686083563000},"page":"124-136","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Blast from the Past: Least Expected Use (LEU) Cache Replacement with Statistical History"],"prefix":"10.1145","author":[{"given":"Sayak","family":"Chakraborti","sequence":"first","affiliation":[{"name":"University of Rochester, USA"}]},{"given":"Zhizhou","family":"Zhang","sequence":"additional","affiliation":[{"name":"University of California at Santa Barbara, USA"}]},{"given":"Noah","family":"Bertram","sequence":"additional","affiliation":[{"name":"Cornell University, USA"}]},{"given":"Chen","family":"Ding","sequence":"additional","affiliation":[{"name":"University of Rochester, USA"}]},{"given":"Sandhya","family":"Dwarkadas","sequence":"additional","affiliation":[{"name":"University of Virginia, USA"}]}],"member":"320","published-online":{"date-parts":[[2023,6,6]]},"reference":[{"volume-title":"d.]. The 2nd cache replacement championship-co-located with isca june","year":"2017","key":"e_1_3_2_1_1_1","unstructured":"[n. d.]. The 2nd cache replacement championship-co-located with isca june 2017 . https:\/\/crc2.ece.tamu.edu\/ [n. d.]. The 2nd cache replacement championship-co-located with isca june 2017. https:\/\/crc2.ece.tamu.edu\/"},{"key":"e_1_3_2_1_2_1","unstructured":"[n. d.]. Standard Performance Evaluation Corporation. https:\/\/www.spec.org\/cpu2006\/ \t\t\t\t  [n. d.]. Standard Performance Evaluation Corporation. https:\/\/www.spec.org\/cpu2006\/"},{"key":"e_1_3_2_1_3_1","volume-title":"2016 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 225-236","author":"Beckmann Nathan","year":"2016","unstructured":"Nathan Beckmann and Daniel Sanchez . 2016 . Modeling cache performance beyond LRU . In 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 225-236 . Nathan Beckmann and Daniel Sanchez. 2016. Modeling cache performance beyond LRU. In 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE, 225-236."},{"key":"e_1_3_2_1_4_1","doi-asserted-by":"crossref","DOI":"10.1147\/sj.52.0078","article-title":"A study of replacement algorithms for a virtualstorage computer","volume":"5","author":"Belady L. A.","year":"1966","unstructured":"L. A. Belady . 1966 . A study of replacement algorithms for a virtualstorage computer . IBM Systems Journal 5 , 2 ( 1966 ), 78-101. L. A. Belady. 1966. A study of replacement algorithms for a virtualstorage computer. IBM Systems Journal 5, 2 ( 1966 ), 78-101.","journal-title":"IBM Systems Journal"},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2004.1291352"},{"volume-title":"Operating systems theory","author":"Cofman Edward Grady","key":"e_1_3_2_1_6_1","unstructured":"Edward Grady Cofman and Peter J Denning . 1973. Operating systems theory . Vol. 973 . prentice-Hall Englewood Clifs , NJ. Edward Grady Cofman and Peter J Denning. 1973. Operating systems theory. Vol. 973. prentice-Hall Englewood Clifs, NJ."},{"key":"e_1_3_2_1_7_1","article-title":"Reuse distancebased probabilistic cache replacement","volume":"12","author":"Das Subhasis","year":"2015","unstructured":"Subhasis Das , Tor M Aamodt , and William J Dally . 2015 . Reuse distancebased probabilistic cache replacement . ACM Transactions on Architecture and Code Optimization (TACO) 12 , 4 ( 2015 ), 1-22. Subhasis Das, Tor M Aamodt, and William J Dally. 2015. Reuse distancebased probabilistic cache replacement. ACM Transactions on Architecture and Code Optimization (TACO) 12, 4 ( 2015 ), 1-22.","journal-title":"ACM Transactions on Architecture and Code Optimization (TACO)"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.43"},{"key":"e_1_3_2_1_9_1","first-page":"179","volume-title":"AMD, and VIA CPUs. ( 1996-2019)","author":"Fog Agner","unstructured":"Agner Fog . 1996-2019. Instruction Tables , Lists of instruction latencies , throughputs and micro-operation breakdowns for Intel , AMD, and VIA CPUs. ( 1996-2019) , 179 - 180 . https:\/\/www.agner.org\/optimize\/ instruction_tables.pdf Agner Fog. 1996-2019. Instruction Tables,Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD, and VIA CPUs. ( 1996-2019), 179-180. https:\/\/www.agner.org\/optimize\/ instruction_tables.pdf"},{"key":"e_1_3_2_1_10_1","first-page":"1","article-title":"Auto-tuning a high-level language targeted to GPU codes. In 2012 Innovative Parallel Computing (InPar)","author":"Grauer-Gray Scott","year":"2012","unstructured":"Scott Grauer-Gray , Lifan Xu , Robert Searles , Sudhee Ayalasomayajula , and John Cavazos . 2012 . Auto-tuning a high-level language targeted to GPU codes. In 2012 Innovative Parallel Computing (InPar) . Ieee , 1 - 10 . Scott Grauer-Gray, Lifan Xu, Robert Searles, Sudhee Ayalasomayajula, and John Cavazos. 2012. Auto-tuning a high-level language targeted to GPU codes. In 2012 Innovative Parallel Computing (InPar). Ieee, 1-10.","journal-title":"Ieee"},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.17"},{"key":"e_1_3_2_1_12_1","unstructured":"Aamer Jaleel. [n. d.]. Memory Characterization of Workloads Using Instrumentation-Driven Simulation A Pin-based Memory Characterization of the SPEC CPU2000 and SPEC CPU2006 Benchmark Suites. ([n. d.]). http:\/\/http:\/\/www.glue.umd.edu\/~ajaleel\/workload\/ \t\t\t\t  Aamer Jaleel. [n. d.]. Memory Characterization of Workloads Using Instrumentation-Driven Simulation A Pin-based Memory Characterization of the SPEC CPU2000 and SPEC CPU2006 Benchmark Suites. ([n. d.]). http:\/\/http:\/\/www.glue.umd.edu\/~ajaleel\/workload\/"},{"key":"e_1_3_2_1_13_1","volume-title":"Simon C Steely Jr, and Joel Emer","author":"Jaleel Aamer","year":"2015","unstructured":"Aamer Jaleel , Joseph Nuzman , Adrian Moga , Simon C Steely Jr, and Joel Emer . 2015 . High Performing Cache Hierarchies for Server Workloads. In High-Performance Computer Architecture (HPCA) . Aamer Jaleel, Joseph Nuzman, Adrian Moga, Simon C Steely Jr, and Joel Emer. 2015. High Performing Cache Hierarchies for Server Workloads. In High-Performance Computer Architecture (HPCA)."},{"key":"e_1_3_2_1_14_1","first-page":"60","volume-title":"ACM SIGARCH Computer Architecture News","volume":"38","author":"Jaleel Aamer","year":"2010","unstructured":"Aamer Jaleel , Kevin B Theobald , Simon C Steely Jr , and Joel Emer . 2010 . High performance cache replacement using re-reference interval prediction (RRIP) . In ACM SIGARCH Computer Architecture News , Vol. 38 . ACM, 60 - 71 . Aamer Jaleel, Kevin B Theobald, Simon C Steely Jr, and Joel Emer. 2010. High performance cache replacement using re-reference interval prediction (RRIP). In ACM SIGARCH Computer Architecture News, Vol. 38. ACM, 60-71."},{"volume-title":"Proceedings of the International Conference on Measurement and Modeling of Computer Systems. Marina Del Rey, California.","author":"Jiang S.","key":"e_1_3_2_1_15_1","unstructured":"S. Jiang and X. Zhang . 2002. LIRS: an eficient low inter-reference recency set replacement to improve bufer cache performance . In Proceedings of the International Conference on Measurement and Modeling of Computer Systems. Marina Del Rey, California. S. Jiang and X. Zhang. 2002. LIRS: an eficient low inter-reference recency set replacement to improve bufer cache performance. In Proceedings of the International Conference on Measurement and Modeling of Computer Systems. Marina Del Rey, California."},{"key":"e_1_3_2_1_16_1","article-title":"A simple algorithm for finding frequent elements in streams and bags","volume":"28","author":"Karp Richard M","year":"2003","unstructured":"Richard M Karp , Scott Shenker , and Christos H Papadimitriou . 2003 . A simple algorithm for finding frequent elements in streams and bags . ACM Transactions on Database Systems (TODS) 28 , 1 ( 2003 ), 51-55. Richard M Karp, Scott Shenker, and Christos H Papadimitriou. 2003. A simple algorithm for finding frequent elements in streams and bags. ACM Transactions on Database Systems (TODS) 28, 1 ( 2003 ), 51-55.","journal-title":"ACM Transactions on Database Systems (TODS)"},{"key":"e_1_3_2_1_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2007.4601909"},{"key":"e_1_3_2_1_18_1","article-title":"Kill the program counter: Reconstructing program behavior in the processor cache hierarchy","volume":"45","author":"Kim Jinchun","year":"2017","unstructured":"Jinchun Kim , Elvira Teran , Paul V Gratz , Daniel A Jim\u00e9nez , Seth H Pugsley , and Chris Wilkerson . 2017 . Kill the program counter: Reconstructing program behavior in the processor cache hierarchy . ACM SIGARCH Computer Architecture News 45 , 1 ( 2017 ), 737-749. Jinchun Kim, Elvira Teran, Paul V Gratz, Daniel A Jim\u00e9nez, Seth H Pugsley, and Chris Wilkerson. 2017. Kill the program counter: Reconstructing program behavior in the processor cache hierarchy. ACM SIGARCH Computer Architecture News 45, 1 ( 2017 ), 737-749.","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"e_1_3_2_1_19_1","first-page":"190","article-title":"Pin: building customized program analysis tools with dynamic instrumentation. In Acm sigplan notices, Vol. 40","author":"Luk Chi-Keung","year":"2005","unstructured":"Chi-Keung Luk , Robert Cohn , Robert Muth , Harish Patil , Artur Klauser , Geof Lowney , Steven Wallace , Vijay Janapa Reddi , and Kim Hazelwood . 2005 . Pin: building customized program analysis tools with dynamic instrumentation. In Acm sigplan notices, Vol. 40 . ACM , 190 - 200 . Chi-Keung Luk, Robert Cohn, Robert Muth, Harish Patil, Artur Klauser, Geof Lowney, Steven Wallace, Vijay Janapa Reddi, and Kim Hazelwood. 2005. Pin: building customized program analysis tools with dynamic instrumentation. In Acm sigplan notices, Vol. 40. ACM, 190-200.","journal-title":"ACM"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749733"},{"key":"e_1_3_2_1_21_1","volume-title":"Traiger","author":"Mattson Richard L.","year":"1970","unstructured":"Richard L. Mattson , Jan Gecsei , Donald R. Slutz , and Irving L . Traiger . 1970 . Evaluation techniques for storage hierarchies. IBM Systems journal 9, 2 ( 1970 ), 78-117. Richard L. Mattson, Jan Gecsei, Donald R. Slutz, and Irving L. Traiger. 1970. Evaluation techniques for storage hierarchies. IBM Systems journal 9, 2 ( 1970 ), 78-117."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"crossref","unstructured":"Naveen Muralimanohar Rajeev Balasubramonian and Norman P Jouppi. 2009. CACTI 6.0: A tool to model large caches. HP laboratories 27 ( 2009 ) 28. \t\t\t\t  Naveen Muralimanohar Rajeev Balasubramonian and Norman P Jouppi. 2009. CACTI 6.0: A tool to model large caches. HP laboratories 27 ( 2009 ) 28.","DOI":"10.1109\/MM.2008.2"},{"key":"e_1_3_2_1_23_1","volume-title":"2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA). IEEE, 118-131","author":"Pakalapati Samuel","year":"2020","unstructured":"Samuel Pakalapati and Biswabandan Panda . 2020 . Bouquet of instruction pointers: Instruction pointer classifier-based spatial hardware prefetching . In 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA). IEEE, 118-131 . Samuel Pakalapati and Biswabandan Panda. 2020. Bouquet of instruction pointers: Instruction pointer classifier-based spatial hardware prefetching. In 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA). IEEE, 118-131."},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICSAMOS.2009.5289241"},{"key":"e_1_3_2_1_25_1","unstructured":"Louis-No\u00ebl Pouchet. [n. d.]. PolyBench\/C 4.0. http:\/\/polybench.sourceforge.net. \t\t\t\t  Louis-No\u00ebl Pouchet. [n. d.]. PolyBench\/C 4.0. http:\/\/polybench.sourceforge.net."},{"key":"e_1_3_2_1_26_1","volume-title":"Polybench: The polyhedral benchmark suite. URL: http:\/\/www. cs. ucla. edu\/pouchet\/software\/polybench ( 2012 ).","author":"Pouchet Louis-No\u00ebl","year":"2012","unstructured":"Louis-No\u00ebl Pouchet . 2012 . Polybench: The polyhedral benchmark suite. URL: http:\/\/www. cs. ucla. edu\/pouchet\/software\/polybench ( 2012 ). Louis-No\u00ebl Pouchet. 2012. Polybench: The polyhedral benchmark suite. URL: http:\/\/www. cs. ucla. edu\/pouchet\/software\/polybench ( 2012 )."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.25"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00048"},{"key":"e_1_3_2_1_29_1","volume-title":"Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture. ACM, 413-425","author":"Shi Zhan","year":"2019","unstructured":"Zhan Shi , Xiangru Huang , Akanksha Jain , and Calvin Lin . 2019 . Applying Deep Learning to the Cache Replacement Problem . In Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture. ACM, 413-425 . Zhan Shi, Xiangru Huang, Akanksha Jain, and Calvin Lin. 2019. Applying Deep Learning to the Cache Replacement Problem. In Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture. ACM, 413-425."},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155671"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/2451116.2451153"},{"key":"e_1_3_2_1_32_1","article-title":"A Relational Theory of Locality","volume":"16","author":"Yuan Liang","year":"2019","unstructured":"Liang Yuan , Chen Ding , Wesley Smith , Peter Denning , and Yunquan Zhang . 2019 . A Relational Theory of Locality . ACM Transactions on Architecture and Code Optimization (TACO) 16 , 3 ( 2019 ), 33. Liang Yuan, Chen Ding, Wesley Smith, Peter Denning, and Yunquan Zhang. 2019. A Relational Theory of Locality. ACM Transactions on Architecture and Code Optimization (TACO) 16, 3 ( 2019 ), 33.","journal-title":"ACM Transactions on Architecture and Code Optimization (TACO)"},{"key":"e_1_3_2_1_33_1","unstructured":"Tomofumi Yuki and Louis-No\u00a8 el Pouchet. 2015. POLYBENCH 4.0. ( 2015 ). \t\t\t\t  Tomofumi Yuki and Louis-No\u00a8 el Pouchet. 2015. POLYBENCH 4.0. ( 2015 )."}],"event":{"name":"ISMM '23: 2023 ACM SIGPLAN International Symposium on Memory Management","sponsor":["SIGPLAN ACM Special Interest Group on Programming Languages"],"location":"Orlando FL USA","acronym":"ISMM '23"},"container-title":["Proceedings of the 2023 ACM SIGPLAN International Symposium on Memory Management"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3591195.3595267","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3591195.3595267","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T16:37:31Z","timestamp":1750178251000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3591195.3595267"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,6,6]]},"references-count":33,"alternative-id":["10.1145\/3591195.3595267","10.1145\/3591195"],"URL":"https:\/\/doi.org\/10.1145\/3591195.3595267","relation":{},"subject":[],"published":{"date-parts":[[2023,6,6]]},"assertion":[{"value":"2023-06-06","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}