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Lang."],"published-print":{"date-parts":[[2023,6,6]]},"abstract":"<jats:p>\n            We introduce the new problem of\n            <jats:italic>hardware decompilation<\/jats:italic>\n            . Analogous to software decompilation, hardware decompilation is about analyzing a low-level artifact\u2014in this case a\n            <jats:italic>netlist<\/jats:italic>\n            , i.e., a graph of wires and logical gates representing a digital circuit\u2014in order to recover higher-level programming abstractions, and using those abstractions to generate code written in a hardware description language (HDL). The overall problem of hardware decompilation requires a number of pieces. In this paper we focus on one specific piece of the puzzle: a technique we call\n            <jats:italic>hardware loop rerolling<\/jats:italic>\n            . Hardware loop rerolling leverages clone detection and program synthesis techniques to identify repeated logic in netlists (such as would be synthesized from loops in the original HDL code) and\n            <jats:italic>reroll<\/jats:italic>\n            them into syntactic loops in the recovered HDL code. We evaluate hardware loop rerolling for hardware decompilation over a set of hardware design benchmarks written in the PyRTL HDL and industry standard SystemVerilog. Our implementation identifies and rerolls loops in 52 out of 53 of the netlists in our benchmark suite, and we show three examples of how hardware decompilation can provide concrete benefits: transpilation between HDLs, faster simulation times over netlists (with mean speedup of 6x), and artifact compaction (39% smaller on average).\n          <\/jats:p>","DOI":"10.1145\/3591237","type":"journal-article","created":{"date-parts":[[2023,6,6]],"date-time":"2023-06-06T20:06:24Z","timestamp":1686081984000},"page":"420-442","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":10,"title":["Loop Rerolling for Hardware Decompilation"],"prefix":"10.1145","volume":"7","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-8349-7701","authenticated-orcid":false,"given":"Zachary D.","family":"Sisco","sequence":"first","affiliation":[{"name":"University of California at Santa Barbara, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1443-1373","authenticated-orcid":false,"given":"Jonathan","family":"Balkind","sequence":"additional","affiliation":[{"name":"University of California at Santa Barbara, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6550-6075","authenticated-orcid":false,"given":"Timothy","family":"Sherwood","sequence":"additional","affiliation":[{"name":"University of California at Santa Barbara, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-1199-6129","authenticated-orcid":false,"given":"Ben","family":"Hardekopf","sequence":"additional","affiliation":[{"name":"University of California at Santa Barbara, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2023,6,6]]},"reference":[{"key":"e_1_2_1_1_1","volume-title":"Proceedings of the 2019 ACM SIGSAC Conference on Computer and Communications Security (CCS \u201919)","author":"Ardeshiricham Armaiti","year":"2019","unstructured":"Armaiti Ardeshiricham , Yoshiki Takashima , Sicun Gao , and Ryan Kastner . 2019 . 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International Journal of Information , 9 , 2 (2006), March , 249 \u2013 264 . http:\/\/eprints.gla.ac.uk\/3461\/ J.T. O\u2019Donnell. 2006. Overview of Hydra: a concurrent language for synchronous digital circuit design. International Journal of Information, 9, 2 (2006), March, 249\u2013264. http:\/\/eprints.gla.ac.uk\/3461\/","journal-title":"International Journal of Information"},{"key":"e_1_2_1_25_1","volume-title":"2019 Asian Hardware Oriented Security and Trust Symposium (AsianHOST). 1\u20136. https:\/\/doi.org\/10","author":"Portillo J.","year":"2019","unstructured":"J. Portillo , T. Meade , J. Hacker , S. Zhang , and Y. Jin . 2019. RERTL: Finite State Transducer Logic Recovery at Register Transfer Level . In 2019 Asian Hardware Oriented Security and Trust Symposium (AsianHOST). 1\u20136. https:\/\/doi.org\/10 .1109\/AsianHOST47458. 2019 .9006699 10.1109\/AsianHOST47458.2019.9006699 10.1109\/AsianHOST47458.2019.9006699 J. Portillo, T. Meade, J. Hacker, S. Zhang, and Y. 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