{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,8]],"date-time":"2026-05-08T14:23:08Z","timestamp":1778250188176,"version":"3.51.4"},"reference-count":87,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2023,6,30]],"date-time":"2023-06-30T00:00:00Z","timestamp":1688083200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2023,7,31]]},"abstract":"<jats:p>\n            Due to the advancement of transistor technology, a single chip processor can now have hundreds of cores.\n            <jats:bold>Network-on-Chip (NoC)<\/jats:bold>\n            has been the superior interconnect fabric for multi\/many-core on-chip systems because of its scalability and parallelism. Due to the rise of dark silicon with the end of Dennard Scaling, it becomes essential to design energy efficient and high performance heterogeneous NoC-based multi\/many-core architectures. Because of the large and complex design space, the solution space becomes difficult to explore within a reasonable time for optimal trade-offs of energy-performance-reliability. Furthermore, reactive resource management is not effective in preventing problems from happening in adaptive systems. Therefore, in this work, we explore machine learning techniques to design and configure the NoC resources based on the learning of the system and applications workloads. Machine learning can automatically learn from past experiences and guide the NoC intelligently to achieve its objective on performance, power, and reliability. We present the challenges of NoC design and resource management and propose a generalized machine learning framework to uncover near-optimal solutions quickly. We propose and implement a NoC design and optimization solution enabled by neural networks, using the generalized machine learning framework. Simulation results demonstrated that the proposed neural networks-based design and optimization solution improves performance by 15% and reduces energy consumption by 6% compared to an existing non-machine learning-based solution while the proposed solution improves NoC latency and throughput compared to two existing machine learning-based NoC optimization solutions. The challenges of machine learning technique adaptation in multi\/many-core NoC have been presented to guide future research.\n          <\/jats:p>","DOI":"10.1145\/3591470","type":"journal-article","created":{"date-parts":[[2023,4,17]],"date-time":"2023-04-17T12:18:15Z","timestamp":1681733895000},"page":"1-26","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":13,"title":["Machine Learning Enabled Solutions for Design and Optimization Challenges in Networks-on-Chip based Multi\/Many-Core Architectures"],"prefix":"10.1145","volume":"19","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2978-6671","authenticated-orcid":false,"given":"Md Farhadur","family":"Reza","sequence":"first","affiliation":[{"name":"Department of Mathematics and Computer Science, Eastern Illinois University, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,6,30]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1145\/2967614"},{"key":"e_1_3_1_3_2","first-page":"33","volume-title":"Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS\u201909)","author":"Agarwal N.","year":"2009","unstructured":"N. Agarwal, T. Krishna, L. S. Peh, and N. K. Jha. 2009. GARNET: A detailed on-chip network model inside a full-system simulator. In Proceedings of IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS\u201909). 33\u201342. 10.1109\/ISPASS.2009.4919636"},{"key":"e_1_3_1_4_2","first-page":"825","volume-title":"Proceedings of ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS\u201917)","author":"Bai Yuxin","year":"2017","unstructured":"Yuxin Bai, Victor W. Lee, and Engin Ipek. 2017. Voltage regulator efficiency aware power management. In Proceedings of ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS\u201917). 825\u2013838. 10.1145\/3037697.3037717"},{"key":"e_1_3_1_5_2","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.6"},{"key":"e_1_3_1_6_2","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045100"},{"key":"e_1_3_1_7_2","unstructured":"Keren Bergman et\u00a0al. 2008. ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems. (2008)."},{"key":"e_1_3_1_8_2","first-page":"15","volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe: Proceedings (DATE\u201906)","author":"Bertozzi Stefano","year":"2006","unstructured":"Stefano Bertozzi, Andrea Acquaviva, Davide Bertozzi, and Antonio Poggiali. 2006. Supporting task migration in multi-processor systems-on-chip: A feasibility study. In Proceedings of the Conference on Design, Automation and Test in Europe: Proceedings (DATE\u201906). European Design and Automation Association, 3001 Leuven, Belgium, 15\u201320. http:\/\/dl.acm.org\/citation.cfm?id=1131481.1131488."},{"key":"e_1_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.1145\/3145812"},{"key":"e_1_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2638459"},{"key":"e_1_3_1_11_2","first-page":"154","volume-title":"Proceedings of the Conference on Design, Automation and Test in Europe: Designers\u2019 Forum (DATE\u201906)","author":"Bononi Luciano","year":"2006","unstructured":"Luciano Bononi and Nicola Concer. 2006. Simulation and analysis of network on chip architectures: Ring, spidergon and 2D mesh. In Proceedings of the Conference on Design, Automation and Test in Europe: Designers\u2019 Forum (DATE\u201906). European Design and Automation Association, 3001 Leuven, Belgium, 154\u2013159. http:\/\/dl.acm.org\/citation.cfm?id=1131355.1131388."},{"key":"e_1_3_1_12_2","doi-asserted-by":"publisher","DOI":"10.1109\/40.782564"},{"key":"e_1_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"e_1_3_1_14_2","doi-asserted-by":"publisher","DOI":"10.1145\/1941487.1941507"},{"key":"e_1_3_1_15_2","first-page":"666","volume-title":"Proceedings of International Symposium on Computer Architecture (ISCA\u201917)","author":"Boyapati R.","year":"2017","unstructured":"R. Boyapati, J. Huang, P. Majumder, K. H. Yum, and E. J. Kim. 2017. APPROX-NOC: A data approximation framework for network-on-chip architectures. In Proceedings of International Symposium on Computer Architecture (ISCA\u201917). 666\u2013677. 10.1145\/3079856.3080241"},{"key":"e_1_3_1_16_2","first-page":"34","volume-title":"Proceedings of IEEE\/IFIP International Workshop on Rapid System Prototyping (RSP\u201907)","author":"Carvalho E.","year":"2007","unstructured":"E. Carvalho, N. Calazans, and F. Moraes. 2007. Heuristics for dynamic task mapping in NoC-based heterogeneous MPSoCs. In Proceedings of IEEE\/IFIP International Workshop on Rapid System Prototyping (RSP\u201907). 34\u201340. 10.1109\/RSP.2007.26"},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2008.4771806"},{"key":"e_1_3_1_18_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.33"},{"key":"e_1_3_1_19_2","doi-asserted-by":"crossref","first-page":"161","DOI":"10.1145\/1289816.1289857","volume-title":"Proceedings of International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS\u201907)","author":"Chou Chen-Ling","year":"2007","unstructured":"Chen-Ling Chou and R. Marculescu. 2007. Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels. In Proceedings of International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS\u201907). 161\u2013166."},{"key":"e_1_3_1_20_2","volume-title":"Principles and Practices of Interconnection Networks","author":"Dally William","year":"2003","unstructured":"William Dally and Brian Towles. 2003. Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA."},{"key":"e_1_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1109\/71.219761"},{"key":"e_1_3_1_22_2","first-page":"684","volume-title":"Proceedings of the 38th Design Automation Conference","author":"Dally William J.","year":"2001","unstructured":"William J. Dally and Brian Towles. 2001. Route packets, not wires: On-chip inteconnection networks. In Proceedings of the 38th Design Automation Conference. 684\u2013689. 10.1145\/378239.379048"},{"key":"e_1_3_1_23_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2160348"},{"key":"e_1_3_1_24_2","doi-asserted-by":"crossref","first-page":"705","DOI":"10.1109\/ICCAD.2015.7372639","volume-title":"2015 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD\u201915)","author":"Das S.","year":"2015","unstructured":"S. Das, J. R. Doppa, D. H. Kim, P. P. Pande, and K. Chakrabarty. 2015. Optimizing 3D NoC design for energy efficiency: A machine learning approach. In 2015 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD\u201915). 705\u2013712. 10.1109\/ICCAD.2015.7372639"},{"key":"e_1_3_1_25_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050511"},{"key":"e_1_3_1_26_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783734"},{"key":"e_1_3_1_27_2","first-page":"1354","volume-title":"Proceedings of IEEE Design, Automation and Test in Europe (DATE\u201917)","author":"DiTomaso Dominic","year":"2017","unstructured":"Dominic DiTomaso, Ashif Sikder, Avinash Kodi, and Ahmed Louri. 2017. Machine learning enabled power-aware network-on-chip design. In Proceedings of IEEE Design, Automation and Test in Europe (DATE\u201917). 1354\u20131359. http:\/\/dl.acm.org\/citation.cfm?id=3130379.3130699."},{"key":"e_1_3_1_28_2","volume-title":"Interconnection Networks: An Engineering Approach","author":"Duato Jose","year":"2002","unstructured":"Jose Duato, Sudhakar Yalamanchili, and Ni Lionel. 2002. Interconnection Networks: An Engineering Approach. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA."},{"key":"e_1_3_1_29_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2012.17"},{"key":"e_1_3_1_30_2","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.31"},{"key":"e_1_3_1_31_2","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"e_1_3_1_32_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2014.36"},{"key":"e_1_3_1_33_2","first-page":"760","volume-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC\u201908)","author":"Faruque Mohammad Abdullah Al","year":"2008","unstructured":"Mohammad Abdullah Al Faruque, R. Krist, and J. Henkel. 2008. ADAM: Run-time agent-based distributed application mapping for on-chip communication. In Proceedings of ACM\/IEEE Design Automation Conference (DAC\u201908). 760\u2013765. 10.1145\/1391469.1391664"},{"key":"e_1_3_1_34_2","first-page":"1","volume-title":"Proceedings of Design Automation Conference (DAC\u201913)","author":"Fattah M.","year":"2013","unstructured":"M. Fattah, M. Daneshtalab, P. Liljeberg, and J. Plosila. 2013. Smart hill climbing for agile dynamic mapping in many-core systems. In Proceedings of Design Automation Conference (DAC\u201913). 1\u20136."},{"key":"e_1_3_1_35_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2875476"},{"key":"e_1_3_1_36_2","doi-asserted-by":"crossref","DOI":"10.1201\/b10477","volume-title":"Designing Network On-Chip Architectures in the Nanoscale Era","author":"Flich Jose","year":"2010","unstructured":"Jose Flich and Davide Bertozzi. 2010. Designing Network On-Chip Architectures in the Nanoscale Era. Chapman & Hall\/CRC."},{"key":"e_1_3_1_37_2","doi-asserted-by":"publisher","DOI":"10.1145\/146628.140384"},{"key":"e_1_3_1_38_2","doi-asserted-by":"publisher","DOI":"10.1109\/5.920580"},{"key":"e_1_3_1_39_2","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-014-1144-7"},{"key":"e_1_3_1_40_2","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1109\/ISSCC.2014.6757323","volume-title":"2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC\u201914)","author":"Horowitz M.","year":"2014","unstructured":"M. Horowitz. 2014. 1.1 computing\u2019s energy problem (and what we can do about it). In 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC\u201914). 10\u201314. 10.1109\/ISSCC.2014.6757323"},{"key":"e_1_3_1_41_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378783"},{"key":"e_1_3_1_42_2","doi-asserted-by":"publisher","DOI":"10.1145\/3055202"},{"key":"e_1_3_1_43_2","first-page":"86","volume-title":"Proceedings of the 14th International Conference on Languages and Compilers for Parallel Computing (LCPC\u201901)","author":"Hsu Chung-Hsing","year":"2003","unstructured":"Chung-Hsing Hsu and Ulrich Kremer. 2003. Dynamic voltage and frequency scaling for scientific applications. In Proceedings of the 14th International Conference on Languages and Compilers for Parallel Computing (LCPC\u201901). Springer-Verlag, Berlin, 86\u201399. http:\/\/dl.acm.org\/citation.cfm?id=1769331.1769337."},{"key":"e_1_3_1_44_2","first-page":"32","volume-title":"Proceedings of ACM\/IEEE International Symposium on Low Power Electronics and Design (ISLPED\u201904)","author":"Hu Zhigang","year":"2004","unstructured":"Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor Zyuban, Hans Jacobson, and Pradip Bose. 2004. Microarchitectural techniques for power gating of execution units. In Proceedings of ACM\/IEEE International Symposium on Low Power Electronics and Design (ISLPED\u201904). 32\u201337. 10.1109\/LPE.2004.1349303"},{"key":"e_1_3_1_45_2","volume-title":"Proceedings of International Conference on Computer-Aided Design (ICCAD\u201918)","author":"Joardar Biresh Kumar","year":"2018","unstructured":"Biresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande, Diana Marculescu, and Radu Marculescu. 2018. Hybrid on-chip communication architectures for heterogeneous manycore systems. In Proceedings of International Conference on Computer-Aided Design (ICCAD\u201918). Article 62, 6 pages. 10.1145\/3240765.3243480"},{"key":"e_1_3_1_46_2","doi-asserted-by":"crossref","first-page":"597","DOI":"10.1109\/ASPDAC.2012.6165027","volume-title":"17th Asia and South Pacific Design Automation Conference","author":"Juan D. C.","year":"2012","unstructured":"D. C. Juan, Huapeng Zhou, D. Marculescu, and Xin Li. 2012. A learning-based autoregressive model for fast transient thermal analysis of chip-multiprocessors. In 17th Asia and South Pacific Design Automation Conference. 597\u2013602. 10.1109\/ASPDAC.2012.6165027"},{"key":"e_1_3_1_47_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2170568"},{"key":"e_1_3_1_48_2","first-page":"573","volume-title":"Proceedings of International Conference on Computer Design (ICCD\u201915)","author":"Kanduri A.","year":"2015","unstructured":"A. Kanduri, M. Haghbayan, A. Rahmani, P. Liljeberg, A. Jantsch, and H. Tenhunen. 2015. Dark silicon aware runtime mapping for many-core systems: A patterning approach. In Proceedings of International Conference on Computer Design (ICCD\u201915). 573\u2013580. 10.1109\/ICCD.2015.7357167"},{"key":"e_1_3_1_49_2","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-011-0703-4"},{"key":"e_1_3_1_50_2","first-page":"554","volume-title":"Proceedings of International Symposium on Computer Architecture (ISCA\u201915)","author":"Khudia Daya S.","year":"2015","unstructured":"Daya S. Khudia, Babak Zamirai, Mehrzad Samadi, and Scott Mahlke. 2015. Rumba: An online quality management system for approximate computing. In Proceedings of International Symposium on Computer Architecture (ISCA\u201915). 554\u2013566."},{"key":"e_1_3_1_51_2","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2018.3011040"},{"key":"e_1_3_1_52_2","doi-asserted-by":"crossref","first-page":"65","DOI":"10.1145\/3060403.3060406","volume-title":"Proceedings of the on Great Lakes Symposium on VLSI 2017 (GLSVLSI\u201917)","author":"Kinsy Michel A.","year":"2017","unstructured":"Michel A. Kinsy, Shreeya Khadka, and Mihailo Isakov. 2017. PreNoc: Neural network based predictive routing for network-on-chip architectures. In Proceedings of the on Great Lakes Symposium on VLSI 2017 (GLSVLSI\u201917). ACM, New York, NY, USA, 65\u201370. 10.1145\/3060403.3060406"},{"key":"e_1_3_1_53_2","doi-asserted-by":"crossref","first-page":"119","DOI":"10.1145\/2039370.2039392","volume-title":"Proceedings of IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS\u201911)","author":"Kobbe S.","year":"2011","unstructured":"S. Kobbe, L. Bauer, D. Lohmann, W. Schr\u00f6der-Preikschat, and J. Henkel. 2011. DistRM: Distributed resource management for on-chip many-core systems. In Proceedings of IEEE\/ACM\/IFIP International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS\u201911). 119\u2013128. 10.1145\/2039370.2039392"},{"key":"e_1_3_1_54_2","doi-asserted-by":"publisher","DOI":"10.1007\/s10825-004-7038-9"},{"key":"e_1_3_1_55_2","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.379"},{"key":"e_1_3_1_56_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.34"},{"key":"e_1_3_1_57_2","doi-asserted-by":"publisher","DOI":"10.1145\/2541228.2555312"},{"key":"e_1_3_1_58_2","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2013.08.006"},{"key":"e_1_3_1_59_2","first-page":"300","volume-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC\u201910)","author":"Micheli G. De","year":"2010","unstructured":"G. De Micheli, C. Seiculescu, S. Murali, L. Benini, F. Angiolini, and A. Pullini. 2010. Networks on chips: From research to products. In Proceedings of ACM\/IEEE Design Automation Conference (DAC\u201910). 300\u2013305. 10.1145\/1837274.1837352"},{"key":"e_1_3_1_60_2","first-page":"566","volume-title":"Proceedings of Design, Automation Test in Europe Conference Exhibition","author":"Modarressi M.","year":"2009","unstructured":"M. Modarressi, H. Sarbazi-Azad, and M. Arjomand. 2009. A hybrid packet-circuit switched on-chip network based on SDM. In Proceedings of Design, Automation Test in Europe Conference Exhibition. 566\u2013569. 10.1109\/DATE.2009.5090728"},{"key":"e_1_3_1_61_2","doi-asserted-by":"publisher","DOI":"10.1145\/1555815.1555781"},{"key":"e_1_3_1_62_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878263"},{"key":"e_1_3_1_63_2","doi-asserted-by":"crossref","first-page":"110","DOI":"10.1145\/1278480.1278509","volume-title":"2007 44th ACM\/IEEE Design Automation Conference","author":"Ogras U. Y.","year":"2007","unstructured":"U. Y. Ogras, R. Marculescu, P. Choudhary, and D. Marculescu. 2007. Voltage-frequency island partitioning for GALS-based networks-on-chip. In 2007 44th ACM\/IEEE Design Automation Conference. 110\u2013115."},{"key":"e_1_3_1_64_2","volume-title":"Routing Algorithms in Networks-on-Chip","author":"Palesi Maurizio","year":"2013","unstructured":"Maurizio Palesi and Masoud Daneshtalab. 2013. Routing Algorithms in Networks-on-Chip. Springer Publishing Company, Incorporated."},{"key":"e_1_3_1_65_2","doi-asserted-by":"crossref","first-page":"71","DOI":"10.1145\/1645213.1645230","volume-title":"Proceedings of the 2nd International Workshop on Network on Chip Architectures (NoCArc\u201909)","author":"Pande Partha Pratim","year":"2009","unstructured":"Partha Pratim Pande, Amlan Ganguly, Kevin Chang, and Christof Teuscher. 2009. Hybrid wireless network on chip: A new paradigm in multi-core design. In Proceedings of the 2nd International Workshop on Network on Chip Architectures (NoCArc\u201909). ACM, 71\u201376. 10.1145\/1645213.1645230"},{"key":"e_1_3_1_66_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.134"},{"key":"e_1_3_1_67_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.893649"},{"key":"e_1_3_1_68_2","doi-asserted-by":"crossref","first-page":"354","DOI":"10.7873\/DATE.2013.083","volume-title":"2013 Design, Automation Test in Europe Conference Exhibition (DATE\u201913)","author":"Qian Z.","year":"2013","unstructured":"Z. Qian, D. C. Juan, P. Bogdan, C. Y. Tsui, D. Marculescu, and R. Marculescu. 2013. SVR-NoC: A performance analysis tool for network-on-chips using learning-based support vector regression model. In 2013 Design, Automation Test in Europe Conference Exhibition (DATE\u201913). 354\u2013357. 10.7873\/DATE.2013.083"},{"key":"e_1_3_1_69_2","first-page":"468","volume-title":"Proceedings of IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS\u201920)","author":"Reza M. F.","year":"2020","unstructured":"M. F. Reza. 2020. Reinforcement learning based dynamic link configuration for energy-efficient NoC. In Proceedings of IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS\u201920). 468\u2013473."},{"key":"e_1_3_1_70_2","doi-asserted-by":"crossref","first-page":"29","DOI":"10.1145\/3477231.3490427","volume-title":"Proceedings of the 14th International Workshop on Network on Chip Architectures (NoCArc\u201921)","author":"Reza Md Farhadur","year":"2021","unstructured":"Md Farhadur Reza. 2021. Machine learning for design and optimization challenges in multi\/many-core network-on-chip. In Proceedings of the 14th International Workshop on Network on Chip Architectures (NoCArc\u201921). ACM, 29\u201334. 10.1145\/3477231.3490427"},{"key":"e_1_3_1_71_2","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3182500"},{"key":"e_1_3_1_72_2","first-page":"1","volume-title":"Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS\u201921)","author":"Reza Md Farhadur","year":"2021","unstructured":"Md Farhadur Reza and Tung Thanh Le. 2021. Reinforcement learning enabled routing for high-performance networks-on-chip. In Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS\u201921). 1\u20135. 10.1109\/ISCAS51556.2021.9401790"},{"key":"e_1_3_1_73_2","first-page":"1","volume-title":"Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS\u201918)","author":"Reza M. F.","year":"2018","unstructured":"M. F. Reza, T. T. Le, B. De, M. Bayoumi, and D. Zhao. 2018. Neuro-NoC: Energy optimization in heterogeneous many-core NoC using neural networks in dark silicon era. In Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS\u201918). 1\u20135. 10.1109\/ISCAS.2018.8351580"},{"key":"e_1_3_1_74_2","first-page":"260","volume-title":"Proceedings of 31st IEEE International System-on-Chip Conference (SOCC\u201918)","author":"Reza M. F.","year":"2018","unstructured":"M. F. Reza, D. Zhao, and M. Bayoumi. 2018. Power- thermal aware balanced task-resource co-allocation in heterogeneous many CPU-GPU cores NoC in dark silicon era. In Proceedings of 31st IEEE International System-on-Chip Conference (SOCC\u201918). 260\u2013265. 10.1109\/SOCC.2018.8618557"},{"key":"e_1_3_1_75_2","doi-asserted-by":"crossref","first-page":"581","DOI":"10.1016\/j.compeleceng.2018.04.019","article-title":"HotSpot-aware task-resource co-allocation for heterogeneous many-core networks-on-chip","volume":"68","author":"Reza M. F.","year":"2018","unstructured":"M. F. Reza, D. Zhao, Hongyi Wu, and M. Bayoumi. 2018. HotSpot-aware task-resource co-allocation for heterogeneous many-core networks-on-chip. Computers & Electrical Engineering 68, C (2018), 581\u2013602.","journal-title":"Computers & Electrical Engineering"},{"key":"e_1_3_1_76_2","unstructured":"David E. Rumelhart Geoffrey E. Hinton and Ronald J. Williams. 1988. Neurocomputing: Foundations of research. MIT Press Chapter Learning Representations by Back-propagating Errors 696\u2013699. http:\/\/dl.acm.org\/citation.cfm?id=65669.104451."},{"key":"e_1_3_1_77_2","doi-asserted-by":"publisher","DOI":"10.1155\/2012\/107821"},{"key":"e_1_3_1_78_2","volume-title":"Proceedings of ACM\/IEEE Design Automation Conference (DAC\u201914)","author":"Shafique Muhammad","year":"2014","unstructured":"Muhammad Shafique, Siddharth Garg, J\u00f6rg Henkel, and Diana Marculescu. 2014. The EDA challenges in the dark silicon era: Temperature, reliability, and variability perspectives. In Proceedings of ACM\/IEEE Design Automation Conference (DAC\u201914). Article 185, 6 pages. 10.1145\/2593069.2593229"},{"key":"e_1_3_1_79_2","first-page":"177","volume-title":"International Conference on Dependable Systems and Networks","author":"Srinivasan J.","year":"2004","unstructured":"J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers. 2004. The impact of technology scaling on lifetime reliability. In International Conference on Dependable Systems and Networks. 177\u2013186. 10.1109\/DSN.2004.1311888"},{"key":"e_1_3_1_80_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2013.90"},{"key":"e_1_3_1_81_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2002.997877"},{"key":"e_1_3_1_82_2","doi-asserted-by":"crossref","first-page":"1166","DOI":"10.23919\/DATE.2019.8714869","volume-title":"2019 Design, Automation Test in Europe Conference Exhibition (DATE\u201919)","author":"Wang K.","year":"2019","unstructured":"K. Wang, A. Louri, A. Karanth, and R. Bunescu. 2019. High-performance, energy-efficient, fault-tolerant network-on-chip design using reinforcement learning. In 2019 Design, Automation Test in Europe Conference Exhibition (DATE\u201919). 1166\u20131171. 10.23919\/DATE.2019.8714869"},{"key":"e_1_3_1_83_2","doi-asserted-by":"crossref","first-page":"589","DOI":"10.1145\/3307650.3322274","volume-title":"Proceedings of International Symposium on Computer Architecture","author":"Wang Ke","year":"2019","unstructured":"Ke Wang, Ahmed Louri, Avinash Karanth, and Razvan Bunescu. 2019. IntelliNoC: A holistic design framework for energy-efficient and reliable on-chip communication for manycores. In Proceedings of International Symposium on Computer Architecture. 589\u2013600. 10.1145\/3307650.3322274"},{"key":"e_1_3_1_84_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2897650"},{"key":"e_1_3_1_85_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416640"},{"key":"e_1_3_1_86_2","first-page":"1433","volume-title":"Proceedings of Design, Automation Test in Europe Conference Exhibition (DATE\u201916)","author":"Yao Y.","year":"2016","unstructured":"Y. Yao and Z. Lu. 2016. Memory-access aware DVFS for network-on-chip in CMPs. In Proceedings of Design, Automation Test in Europe Conference Exhibition (DATE\u201916). 1433\u20131436."},{"key":"e_1_3_1_87_2","volume-title":"International Workshop on AI-assisted Design for Architecture (AIDArc), Held in Conjunction with ISCA\u201918","author":"Yin Jieming","year":"2018","unstructured":"Jieming Yin, Yasuko Eckert, Shuai Che, Mark Oskin, and Gabriel H. Loh. 2018. Toward more efficient NoC arbitration: A deep reinforcement learning approach. In International Workshop on AI-assisted Design for Architecture (AIDArc), Held in Conjunction with ISCA\u201918."},{"key":"e_1_3_1_88_2","doi-asserted-by":"crossref","first-page":"55","DOI":"10.1109\/DAC18074.2021.9586301","volume-title":"2021 58th ACM\/IEEE Design Automation Conference (DAC\u201921)","author":"Zhou Yuan","year":"2021","unstructured":"Yuan Zhou, Hanyu Wang, Jieming Yin, and Zhiru Zhang. 2021. Distilling arbitration logic from traces using machine learning: A case study on NoC. In 2021 58th ACM\/IEEE Design Automation Conference (DAC\u201921). 55\u201360. 10.1109\/DAC18074.2021.9586301"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3591470","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3591470","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T22:48:47Z","timestamp":1750286927000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3591470"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,6,30]]},"references-count":87,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2023,7,31]]}},"alternative-id":["10.1145\/3591470"],"URL":"https:\/\/doi.org\/10.1145\/3591470","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"value":"1550-4832","type":"print"},{"value":"1550-4840","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,6,30]]},"assertion":[{"value":"2022-03-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-03-13","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-06-30","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}