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Surv."],"published-print":{"date-parts":[[2023,12,31]]},"abstract":"<jats:p>Effectively managing energy and power consumption is crucial to the success of the design of any computing system, helping mitigate the efficiency obstacles given by the downsizing of the systems while also being a valuable step towards achieving green and sustainable computing. The quality of energy and power management is strongly affected by the prompt availability of reliable and accurate information regarding the power consumption for the different parts composing the target monitored system. At the same time, effective energy and power management are even more critical within the field of devices at the edge, which exponentially proliferated within the past decade with the digital revolution brought by the Internet of things. This manuscript aims to provide a comprehensive conceptual framework to classify the different approaches to implementing run-time power monitors for edge devices that appeared in literature, leading the reader toward the solutions that best fit their application needs and the requirements and constraints of their target computing platforms. Run-time power monitors at the edge are analyzed according to both the power modeling and monitoring implementation aspects, identifying specific quality metrics for both in order to create a consistent and detailed taxonomy that encompasses the vast existing literature and provides a sound reference to the interested reader.<\/jats:p>","DOI":"10.1145\/3593044","type":"journal-article","created":{"date-parts":[[2023,4,18]],"date-time":"2023-04-18T12:41:05Z","timestamp":1681821665000},"page":"1-33","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":18,"title":["A Survey on Run-time Power Monitors at the Edge"],"prefix":"10.1145","volume":"55","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9951-062X","authenticated-orcid":false,"given":"Davide","family":"Zoni","sequence":"first","affiliation":[{"name":"Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Politecnico di Milano, Italy"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0254-3933","authenticated-orcid":false,"given":"Andrea","family":"Galimberti","sequence":"additional","affiliation":[{"name":"Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Politecnico di Milano, Italy"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8294-730X","authenticated-orcid":false,"given":"William","family":"Fornaciari","sequence":"additional","affiliation":[{"name":"Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Politecnico di Milano, Italy"}]}],"member":"320","published-online":{"date-parts":[[2023,7,17]]},"reference":[{"key":"e_1_3_1_2_2","first-page":"265","volume-title":"12th USENIX Symposium on Operating Systems Design and Implementation (OSDI 16)","author":"Abadi Mart\u00edn","year":"2016","unstructured":"Mart\u00edn Abadi, Paul Barham, Jianmin Chen, Zhifeng Chen, Andy Davis, Jeffrey Dean, Matthieu Devin, Sanjay Ghemawat, Geoffrey Irving, Michael Isard, Manjunath Kudlur, Josh Levenberg, Rajat Monga, Sherry Moore, Derek G. Murray, Benoit Steiner, Paul Tucker, Vijay Vasudevan, Pete Warden, Martin Wicke, Yuan Yu, and Xiaoqiang Zheng. 2016. TensorFlow: A system for large-scale machine learning. In 12th USENIX Symposium on Operating Systems Design and Implementation (OSDI 16). USENIX Association, Savannah, GA, 265\u2013283. https:\/\/www.usenix.org\/conference\/osdi16\/technical-sessions\/presentation\/abadi."},{"key":"e_1_3_1_3_2","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2009.7478379"},{"key":"e_1_3_1_4_2","doi-asserted-by":"crossref","first-page":"136","DOI":"10.1109\/SMC-IT.2017.31","volume-title":"2017 6th International Conference on Space Mission Challenges for Information Technology (SMC-IT)","author":"Andersson Jan","year":"2017","unstructured":"Jan Andersson, Magnus Hjorth, Fredrik Johansson, and Sandi Habinc. 2017. LEON processor devices for space missions: First 20 years of LEON in space. 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Patterson, Brian Richards, Colin Schmidt, Stephen Twigg, Huy Vo, and Andrew Waterman. 2016. The Rocket Chip Generator. Technical Report UCB\/EECS-2016-17. EECS Department, University of California, Berkeley. http:\/\/www2.eecs.berkeley.edu\/Pubs\/TechRpts\/2016\/EECS-2016-17.html."},{"key":"e_1_3_1_8_2","doi-asserted-by":"publisher","DOI":"10.1109\/CMPCON.1995.512368"},{"key":"e_1_3_1_9_2","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.154"},{"key":"e_1_3_1_10_2","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1145\/566726.566736","volume-title":"Proceedings of the 9th Workshop on ACM SIGOPS European Workshop: Beyond the PC: New Challenges for the Operating System (EW 9)","author":"Bellosa Frank","year":"2000","unstructured":"Frank Bellosa. 2000. The benefits of event: Driven energy accounting in power-sensitive systems. In Proceedings of the 9th Workshop on ACM SIGOPS European Workshop: Beyond the PC: New Challenges for the Operating System (EW 9). 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DOI:10.1145\/280756.280894"},{"key":"e_1_3_1_46_2","doi-asserted-by":"crossref","first-page":"209","DOI":"10.1109\/ICCAD.2017.8203780","volume-title":"2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","author":"Izraelevitz Adam","year":"2017","unstructured":"Adam Izraelevitz, Jack Koenig, Patrick Li, Richard Lin, Angie Wang, Albert Magyar, Donggyu Kim, Colin Schmidt, Chick Markley, Jim Lawson, and Jonathan Bachrach. 2017. Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations. In 2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). 209\u2013216. DOI:10.1109\/ICCAD.2017.8203780"},{"key":"e_1_3_1_47_2","doi-asserted-by":"crossref","first-page":"559","DOI":"10.1109\/ICCD.2005.34","volume-title":"2005 International Conference on Computer Design","author":"Jiang Hailin","year":"2005","unstructured":"Hailin Jiang, M. Marek-Sadowska, and S. R. Nassif. 2005. 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