{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,25]],"date-time":"2026-04-25T08:38:25Z","timestamp":1777106305051,"version":"3.51.4"},"reference-count":45,"publisher":"Association for Computing Machinery (ACM)","issue":"1","license":[{"start":{"date-parts":[[2023,11,14]],"date-time":"2023-11-14T00:00:00Z","timestamp":1699920000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["J. Emerg. Technol. Comput. Syst."],"published-print":{"date-parts":[[2024,1,31]]},"abstract":"<jats:p>Video analytics has a wide range of applications and has attracted much interest over the years. While it can be both computationally and energy-intensive, video analytics can greatly benefit from in\/near memory compute. The practice of moving compute closer to memory has continued to show improvements to performance and energy consumption and is seeing increasing adoption. Recent advancements in solid state drives (SSDs) have incorporated near memory Field Programmable Gate Arrays (FPGAs) with shared access to the drive\u2019s storage cells. These near memory FPGAs are capable of running operations required by video analytic pipelines such as object detection and template matching. These operations are typically executed using Convolutional Neural Networks (CNNs). A CNN is composed of multiple individually processed layers that perform various image processing tasks. Due to lack of resources, a layer may be partitioned into more manageable sub-layers. These sub-layers are then processed sequentially, however, some sub-layers can be processed simultaneously. Moreover, the storage cells within FPGA equipped SSDs are capable of being augmented with in-storage compute to accelerate CNN workloads and exploit the intra-parallelism within a CNN layer. To this end, we present our work, which leverages heterogeneous architectures to create an in\/near-storage acceleration solution for video analytics. We designed a NAND flash accelerator and an FPGA accelerator, then mapped and evaluated several CNN benchmarks. We show how to utilize FPGAs, local DRAMs, and in-memory SSD compute to accelerate CNN workloads. Our work also demonstrates how to remove unnecessary memory transfers to save latency and energy.<\/jats:p>","DOI":"10.1145\/3597496","type":"journal-article","created":{"date-parts":[[2023,6,17]],"date-time":"2023-06-17T09:13:40Z","timestamp":1686993220000},"page":"1-22","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":4,"title":["Fusing In-storage and Near-storage Acceleration of Convolutional Neural Networks"],"prefix":"10.1145","volume":"20","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2133-8425","authenticated-orcid":false,"given":"Ikenna","family":"Okafor","sequence":"first","affiliation":[{"name":"The Pennsylvania State University, Dept of Electrical Eng and Comp Sci, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3789-7790","authenticated-orcid":false,"given":"Akshay Krishna","family":"Ramanathan","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University, Dept of Electrical Eng and Comp Sci, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3324-2009","authenticated-orcid":false,"given":"Nagadastagiri Reddy","family":"Challapalle","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University, Dept of Electrical Eng and Comp Sci, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0005-4117-807X","authenticated-orcid":false,"given":"Zheyu","family":"Li","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University, Dept of Electrical Eng and Comp Sci, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6266-6068","authenticated-orcid":false,"given":"Vijaykrishnan","family":"Narayanan","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University, Dept of Electrical Eng and Comp Sci, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,11,14]]},"reference":[{"key":"e_1_3_1_2_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.21"},{"key":"e_1_3_1_3_2","first-page":"1","volume-title":"49th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO\u201916)","author":"Alwani Manoj","year":"2016","unstructured":"Manoj Alwani, Han Chen, Michael Ferdman, and Peter Milder. 2016. Fused-layer CNN accelerators. In 49th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO\u201916). IEEE, 1\u201312."},{"key":"e_1_3_1_4_2","first-page":"875","volume-title":"IEEE 38th International Conference on Distributed Computing Systems (ICDCS\u201918)","author":"Baek SungHa","year":"2018","unstructured":"SungHa Baek, Youngdon Jung, Aziz Mohaisen, Sungjin Lee, and DaeHun Nyang. 2018. SSD-Insider: Internal defense of solid-state drive against ransomware with perfect data recovery. In IEEE 38th International Conference on Distributed Computing Systems (ICDCS\u201918). 875\u2013884. DOI:10.1109\/ICDCS.2018.00089"},{"issue":"1","key":"e_1_3_1_5_2","doi-asserted-by":"crossref","first-page":"127","DOI":"10.1109\/JSSC.2016.2616357","article-title":"Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks","volume":"52","author":"Chen Yu-Hsin","year":"2016","unstructured":"Yu-Hsin Chen, Tushar Krishna, Joel S. Emer, and Vivienne Sze. 2016. Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks. IEEE J. Solid-state Circ. 52, 1 (2016), 127\u2013138.","journal-title":"IEEE J. Solid-state Circ."},{"key":"e_1_3_1_6_2","first-page":"1","volume-title":"54th ACM\/EDAC\/IEEE Design Automation Conference (DAC\u201917)","author":"Cheng Ming","year":"2017","unstructured":"Ming Cheng, Lixue Xia, Zhenhua Zhu, Yi Cai, Yuan Xie, Yu Wang, and Huazhong Yang. 2017. TIME: A training-in-memory architecture for memristor-based deep neural networks. In 54th ACM\/EDAC\/IEEE Design Automation Conference (DAC\u201917). IEEE, 1\u20136."},{"key":"e_1_3_1_7_2","first-page":"27","volume-title":"ACM\/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA\u201916)","author":"Chi P.","year":"2016","unstructured":"P. Chi, S. Li, C. Xu, T. Zhang, J. Zhao, Y. Liu, Y. Wang, and Y. Xie. 2016. PRIME: A novel processing-in-memory architecture for neural network computation in ReRAM-based main memory. In ACM\/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA\u201916). 27\u201339."},{"issue":"3","key":"e_1_3_1_8_2","doi-asserted-by":"crossref","first-page":"27","DOI":"10.1145\/3007787.3001140","article-title":"PRIME: A novel processing-in-memory architecture for neural network computation in ReRAM-based main memory","volume":"44","author":"Chi Ping","year":"2016","unstructured":"Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, and Yuan Xie. 2016. PRIME: A novel processing-in-memory architecture for neural network computation in ReRAM-based main memory. ACM SIGARCH Comput. Archit. News 44, 3 (2016), 27\u201339.","journal-title":"ACM SIGARCH Comput. Archit. News"},{"key":"e_1_3_1_9_2","article-title":"IEDM ferroelectric FET, hafnium oxide round up","author":"Corporation Intel","year":"2021","unstructured":"Intel Corporation. 2021. IEDM ferroelectric FET, hafnium oxide round up. Retrieved from https:\/\/www.eenewsanalog.com\/news\/iedm-ferroelectric-fet-hafnium-oxide-round\/page\/0\/1.","journal-title":"R"},{"key":"e_1_3_1_10_2","article-title":"R-FCN: Object detection via region-based fully convolutional networks","volume":"29","author":"Dai Jifeng","year":"2016","unstructured":"Jifeng Dai, Yi Li, Kaiming He, and Jian Sun. 2016. R-FCN: Object detection via region-based fully convolutional networks. Adv. Neural Inf. Process. Syst. 29 (2016).","journal-title":"Adv. Neural Inf. Process. Syst."},{"key":"e_1_3_1_11_2","first-page":"383","volume-title":"ACM\/IEEE 45th Annual International Symposium on Computer Architecture (ISCA\u201918)","author":"Eckert Charles","year":"2018","unstructured":"Charles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan, Ravi Iyer, Dennis Sylvester, David Blaaauw, and Reetuparna Das. 2018. Neural cache: Bit-serial in-cache acceleration of deep neural networks. In ACM\/IEEE 45th Annual International Symposium on Computer Architecture (ISCA\u201918). IEEE, 383\u2013396."},{"key":"e_1_3_1_12_2","first-page":"260","volume-title":"IEEE International Solid-State Circuits Conference (ISSCC\u201922)","author":"Fick Laura","year":"2022","unstructured":"Laura Fick, Skylar Skrzyniarz, Malav Parikh, Michael B. Henry, and David Fick. 2022. Analog matrix processor for edge AI real-time video analytics. In IEEE International Solid-State Circuits Conference (ISSCC\u201922). 260\u2013262. DOI:10.1109\/ISSCC42614.2022.9731773"},{"key":"e_1_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614710"},{"key":"e_1_3_1_14_2","first-page":"1","article-title":"IBM PureData System for analytics architecture","author":"Francisco Phil","year":"2014","unstructured":"Phil Francisco. 2014. IBM PureData System for analytics architecture. IBM Redbooks (2014), 1\u201316.","journal-title":"IBM Redbooks"},{"issue":"2","key":"e_1_3_1_15_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3296957.3173171","article-title":"In-memory data parallel processor","volume":"53","author":"Fujiki Daichi","year":"2018","unstructured":"Daichi Fujiki, Scott Mahlke, and Reetuparna Das. 2018. In-memory data parallel processor. ACM SIGPLAN Not. 53, 2 (2018), 1\u201314.","journal-title":"ACM SIGPLAN Not."},{"key":"e_1_3_1_16_2","doi-asserted-by":"crossref","first-page":"397","DOI":"10.1145\/3307650.3322257","volume-title":"46th International Symposium on Computer Architecture","author":"Fujiki Daichi","year":"2019","unstructured":"Daichi Fujiki, Scott Mahlke, and Reetuparna Das. 2019. Duality cache for data parallel acceleration. In 46th International Symposium on Computer Architecture. 397\u2013410."},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1145\/3422575.3422790"},{"key":"e_1_3_1_18_2","unstructured":"Prabhat K. Gupta. 2015. Xeon+ fpga platform for the data center. In Fourth Workshop on the Intersections of Computer Architecture and Reconfigurable Logic Vol. 119. 2."},{"key":"e_1_3_1_19_2","article-title":"MobileNets: Efficient convolutional neural networks for mobile vision applications","author":"Howard Andrew G.","year":"2017","unstructured":"Andrew G. Howard, Menglong Zhu, Bo Chen, Dmitry Kalenichenko, Weijun Wang, Tobias Weyand, Marco Andreetto, and Hartwig Adam. 2017. MobileNets: Efficient convolutional neural networks for mobile vision applications. arXiv preprint arXiv:1704.04861 (2017).","journal-title":"arXiv preprint arXiv:1704.04861"},{"key":"e_1_3_1_20_2","first-page":"802","volume-title":"ACM\/IEEE 46th Annual International Symposium on Computer Architecture (ISCA\u201919)","author":"Imani Mohsen","year":"2019","unstructured":"Mohsen Imani, Saransh Gupta, Yeseong Kim, and Tajana Rosing. 2019. FloatPIM: In-memory acceleration of deep neural network training with high precision. In ACM\/IEEE 46th Annual International Symposium on Computer Architecture (ISCA\u201919). IEEE, 802\u2013815."},{"key":"e_1_3_1_21_2","first-page":"1","volume-title":"44th Annual International Symposium on Computer Architecture","author":"Jouppi Norman P.","year":"2017","unstructured":"Norman P. Jouppi, Cliff Young, Nishant Patil, David Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia, Nan Boden, Al Borchers, et\u00a0al. 2017. In-datacenter performance analysis of a tensor processing unit. In 44th Annual International Symposium on Computer Architecture. 1\u201312."},{"key":"e_1_3_1_22_2","doi-asserted-by":"crossref","unstructured":"Minsu Kim Muqing Liu Luke R. Everson and Chris H. Kim. 2022. An embedded nand flash-based compute-in-memory array demonstrated in a standard logic process. IEEE Journal of Solid-State Circuits 57 2 (2022) 625\u2013638. 10.1109\/JSSC.2021.3098671","DOI":"10.1109\/JSSC.2021.3098671"},{"issue":"12","key":"e_1_3_1_23_2","doi-asserted-by":"crossref","first-page":"1706","DOI":"10.14778\/3137765.3137776","article-title":"ExtraV: Boosting graph processing near storage with a coherent accelerator","volume":"10","author":"Lee Jinho","year":"2017","unstructured":"Jinho Lee, Heesu Kim, Sungjoo Yoo, Kiyoung Choi, H. Peter Hofstee, Gi-Joon Nam, Mark R. Nutter, and Damir Jamsek. 2017. ExtraV: Boosting graph processing near storage with a coherent accelerator. Proc. VLDB Endow. 10, 12 (2017), 1706\u20131717.","journal-title":"Proc. VLDB Endow."},{"key":"e_1_3_1_24_2","first-page":"288","volume-title":"50th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO\u201917)","author":"Li Shuangchen","year":"2017","unstructured":"Shuangchen Li, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, and Yuan Xie. 2017. DRISA: A DRAM-based reconfigurable in-situ accelerator. In 50th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO\u201917). 288\u2013301."},{"issue":"1","key":"e_1_3_1_25_2","doi-asserted-by":"crossref","first-page":"63","DOI":"10.1109\/LCA.2019.2908374","article-title":"A unified framework for training, mapping and simulation of ReRAM-based convolutional neural network acceleration","volume":"18","author":"Liu He","year":"2019","unstructured":"He Liu, Jianhui Han, and Youhui Zhang. 2019. A unified framework for training, mapping and simulation of ReRAM-based convolutional neural network acceleration. IEEE Comput. Archit. Lett. 18, 1 (2019), 63\u201366.","journal-title":"IEEE Comput. Archit. Lett."},{"key":"e_1_3_1_26_2","first-page":"21","volume-title":"European Conference on Computer Vision","author":"Liu Wei","year":"2016","unstructured":"Wei Liu, Dragomir Anguelov, Dumitru Erhan, Christian Szegedy, Scott Reed, Cheng-Yang Fu, and Alexander C. Berg. 2016. SSD: Single shot multibox detector. In European Conference on Computer Vision. Springer, 21\u201337."},{"key":"e_1_3_1_27_2","first-page":"1","volume-title":"IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED\u201919)","author":"Liu Xiao","year":"2019","unstructured":"Xiao Liu, Mingxuan Zhou, Tajana S. Rosing, and Jishen Zhao. 2019. HR 3 AM: A heat resilient design for RRAM-based neuromorphic computing. In IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED\u201919). IEEE, 1\u20136."},{"key":"e_1_3_1_28_2","volume-title":"ML Systems Workshop at NIPS\u201917","author":"Lo D.","year":"2017","unstructured":"D. Lo, et\u00a0al. 2017. Accelerating persistent neural networks at datacenter scale. In ML Systems Workshop at NIPS\u201917."},{"issue":"1","key":"e_1_3_1_29_2","doi-asserted-by":"crossref","first-page":"73","DOI":"10.1109\/TC.2016.2574353","article-title":"DaDianNao: A neural network supercomputer","volume":"66","author":"Luo Tao","year":"2016","unstructured":"Tao Luo, Shaoli Liu, Ling Li, Yuqing Wang, Shijin Zhang, Tianshi Chen, Zhiwei Xu, Olivier Temam, and Yunji Chen. 2016. DaDianNao: A neural network supercomputer. IEEE Trans. Comput. 66, 1 (2016), 73\u201388.","journal-title":"IEEE Trans. Comput."},{"key":"e_1_3_1_30_2","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358320"},{"key":"e_1_3_1_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2905242"},{"key":"e_1_3_1_32_2","first-page":"75","volume-title":"14th International Symposium on Systems Synthesis","author":"Panda Preeti Ranjan","year":"2001","unstructured":"Preeti Ranjan Panda. 2001. SystemC: A modeling platform supporting multiple design abstractions. In 14th International Symposium on Systems Synthesis. 75\u201380."},{"key":"e_1_3_1_33_2","first-page":"141","volume-title":"26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS\u201916)","author":"Pouyan Peyman","year":"2016","unstructured":"Peyman Pouyan, Esteve Amat, Said Hamdioui, and Antonio Rubio. 2016. RRAM variability and its mitigation schemes. In 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS\u201916). IEEE, 141\u2013146."},{"key":"e_1_3_1_34_2","article-title":"YOLOv3: An incremental improvement","author":"Redmon Joseph","year":"2018","unstructured":"Joseph Redmon and Ali Farhadi. 2018. YOLOv3: An incremental improvement. arXiv preprint arXiv:1804.02767 (2018).","journal-title":"arXiv preprint arXiv:1804.02767"},{"issue":"1","key":"e_1_3_1_35_2","article-title":"Transaction level modeling in SystemC","volume":"1","author":"Rose Adam","year":"2005","unstructured":"Adam Rose, Stuart Swan, John Pierce, Jean-Michel Fernandez, et\u00a0al. 2005. Transaction level modeling in SystemC. Open Syst.C Initiat. 1, 1.297 (2005).","journal-title":"Open Syst.C Initiat."},{"key":"e_1_3_1_36_2","doi-asserted-by":"publisher","DOI":"10.1145\/3431920.3439298"},{"key":"e_1_3_1_37_2","volume-title":"SamsungSSD","year":"2020","unstructured":"Samsung. 2020. SamsungSSD. Retrieved from https:\/\/www.xilinx.com\/applications\/data-center\/computational-storage\/smartssd.html."},{"issue":"2","key":"e_1_3_1_38_2","doi-asserted-by":"crossref","first-page":"127","DOI":"10.1109\/LCA.2015.2434872","article-title":"Fast bulk bitwise AND and OR in DRAM","volume":"14","author":"Seshadri Vivek","year":"2015","unstructured":"Vivek Seshadri, Kevin Hsieh, Amirali Boroum, Donghyuk Lee, Michael A. Kozuch, Onur Mutlu, Phillip B. Gibbons, and Todd C. Mowry. 2015. Fast bulk bitwise AND and OR in DRAM. IEEE Comput. Archit. Lett. 14, 2 (2015), 127\u2013131.","journal-title":"IEEE Comput. Archit. Lett."},{"key":"e_1_3_1_39_2","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"e_1_3_1_40_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.12"},{"issue":"3","key":"e_1_3_1_41_2","doi-asserted-by":"crossref","first-page":"14","DOI":"10.1145\/3007787.3001139","article-title":"ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars","volume":"44","author":"Shafiee Ali","year":"2016","unstructured":"Ali Shafiee, Anirban Nag, Naveen Muralimanohar, Rajeev Balasubramonian, John Paul Strachan, Miao Hu, R. Stanley Williams, and Vivek Srikumar. 2016. ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars. ACM SIGARCH Comput. Archit. News 44, 3 (2016), 14\u201326.","journal-title":"ACM SIGARCH Comput. Archit. News"},{"key":"e_1_3_1_42_2","first-page":"1677","volume-title":"IEEE Conference on Computer Vision and Pattern Recognition Workshops","author":"Sun Baohua","year":"2018","unstructured":"Baohua Sun, Lin Yang, Patrick Dong, Wenhan Zhang, Jason Dong, and Charles Young. 2018. Ultra power-efficient CNN domain specific accelerator with 9.3 tops\/watt for mobile and embedded applications. In IEEE Conference on Computer Vision and Pattern Recognition Workshops. 1677\u20131685."},{"key":"e_1_3_1_43_2","first-page":"160","volume-title":"IFIP\/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC\u201919)","author":"Vieira Joao","year":"2019","unstructured":"Joao Vieira, Edouard Giacomin, Yasir Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, and Pierre-Emmanuel Gaillardon. 2019. A product engine for energy-efficient execution of binary neural networks using resistive memories. In IFIP\/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC\u201919). IEEE, 160\u2013165."},{"key":"e_1_3_1_44_2","first-page":"165","volume-title":"IEEE Asia Pacific Conference on Circuits and Systems (APCCAS\u201920)","author":"Wen Jiayu","year":"2020","unstructured":"Jiayu Wen, Yufei Ma, and Zhongfeng Wang. 2020. An Efficient FPGA accelerator optimized for high throughput sparse CNN inference. In IEEE Asia Pacific Conference on Circuits and Systems (APCCAS\u201920). IEEE, 165\u2013168."},{"key":"e_1_3_1_45_2","first-page":"1449","volume-title":"Design, Automation Test in Europe Conference Exhibition (DATE\u201916)","author":"Yitbarek Salessawi Ferede","year":"2016","unstructured":"Salessawi Ferede Yitbarek, Tao Yang, Reetuparna Das, and Todd Austin. 2016. Exploring specialized near-memory processing for data intensive operations. In Design, Automation Test in Europe Conference Exhibition (DATE\u201916). 1449\u20131452."},{"key":"e_1_3_1_46_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642198"}],"container-title":["ACM Journal on Emerging Technologies in Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3597496","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3597496","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T17:48:45Z","timestamp":1750182525000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3597496"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,11,14]]},"references-count":45,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2024,1,31]]}},"alternative-id":["10.1145\/3597496"],"URL":"https:\/\/doi.org\/10.1145\/3597496","relation":{},"ISSN":["1550-4832","1550-4840"],"issn-type":[{"value":"1550-4832","type":"print"},{"value":"1550-4840","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,11,14]]},"assertion":[{"value":"2022-03-28","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-03-31","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-11-14","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}