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Further, as SoC design moves toward three-dimensional (3D) architectures, the core's power density increases leading to unacceptable high peak chip temperatures. In this article, we consider the optimization problem of dynamic power management (DPM) in manycore SoCs for an allowable performance penalty (say, 5%) and admissible peak chip temperature. We employ a machine learning\u2013 (ML) based DPM policy, which selects the voltage\/frequency levels for different cluster of cores as a function of the application workload features such as core computation and inter-core traffic, and so on. We propose a novel learning-to-search (L2S) framework to automatically identify an optimized sequence of DPM decisions from a large combinatorial space for joint energy-thermal optimization for one or more given applications. The optimized DPM decisions are given to a supervised learning algorithm to train a DPM policy, which mimics the corresponding decision-making behavior. Our experiments on two different manycore architectures designed using wireless interconnect and monolithic 3D demonstrate that principles behind the L2S framework are applicable for more than one configuration. Moreover, L2S-based DPM policies achieve up to 30% energy-delay product savings and reduce the peak chip temperature by up to 17 \u00b0C compared to the state-of-the-art ML methods for an allowable performance overhead of only 5%.<\/jats:p>","DOI":"10.1145\/3603501","type":"journal-article","created":{"date-parts":[[2023,6,6]],"date-time":"2023-06-06T19:08:11Z","timestamp":1686078491000},"page":"1-21","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Dynamic Power Management in Large Manycore Systems: A Learning-to-Search Framework"],"prefix":"10.1145","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9517-1280","authenticated-orcid":false,"given":"Gaurav","family":"Narang","sequence":"first","affiliation":[{"name":"Washington State University, Pullman, WA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0280-6820","authenticated-orcid":false,"given":"Aryan","family":"Deshwal","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, WA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1175-2983","authenticated-orcid":false,"given":"Raid","family":"Ayoub","sequence":"additional","affiliation":[{"name":"Intel Research Labs, Hillsboro, OR"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5593-9694","authenticated-orcid":false,"given":"Michael","family":"Kishinevsky","sequence":"additional","affiliation":[{"name":"Intel Research Labs, Hillsboro, OR"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3848-5301","authenticated-orcid":false,"given":"Janardhan","family":"Rao Doppa","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, WA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5930-8531","authenticated-orcid":false,"given":"Partha Pratim","family":"Pande","sequence":"additional","affiliation":[{"name":"Washington State University, Pullman, WA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,9,8]]},"reference":[{"key":"e_1_3_1_2_2","first-page":"368","volume-title":"Proceedings of the International Symposium on Low Power Electronics and Design","author":"Aalsaud A.","year":"2016","unstructured":"A. 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