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JISM"},{"name":"NSF","award":["2008365, 2132918"],"award-info":[{"award-number":["2008365, 2132918"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Des. Autom. Electron. Syst."],"published-print":{"date-parts":[[2024,1,31]]},"abstract":"<jats:p>Ferroelectric Field Effect Transistors (FeFETs) have spurred increasing interest in both memories and computing applications, thanks to their CMOS compatibility, low-power operation, and high scalability. However, new security threats to the FeFET-based memories also arise. A major threat is the power analysis side-channel attack (P-SCA), which exploits the power traces of the memory access to obtain data information. There have been several effective efforts on resistive nonvolatile memories (NVMs), but they fail to meet the requirements for secure FeFET-based memories due to the different capacitive FeFETs load. Directly applying these existing countermeasures to the P-SCA protection for FeFETs induces huge challenges, especially for the balance between power side-channel resistance and corresponding overheads.<\/jats:p>\n          <jats:p>\n            To address this issue, we leverage the unique features of FeFETs and propose\n            <jats:italic>ProtFe<\/jats:italic>\n            , namely the protection methods for FeFET-based memories, including the pipelined multi-step write strategy (\n            <jats:italic>PiMWrite<\/jats:italic>\n            ) and the split array design (\n            <jats:italic>SpA<\/jats:italic>\n            ).\n            <jats:italic>PiMWrite<\/jats:italic>\n            is proposed for general FeFET-based memories, and inserts specially designed intermediate states to mitigate information leakage with pipelined steps to reduce overheads.\n            <jats:italic>SpA<\/jats:italic>\n            is proposed for custom FeFET-based memories, and simultaneously writes two split portions of the array with shared minimized peripherals to go beyond the balance between security and overheads. Simulation results show that\n            <jats:italic>PiMWrite<\/jats:italic>\n            expands the search space of a single power trace to 21\u00d7 and involves nearly zero hardware penalties.\n            <jats:italic>SpA<\/jats:italic>\n            presents 33\u00d7 search space improvement with negligible latency, 0.6% area, and only 7.1% energy overhead.\n            <jats:italic>ProtFe<\/jats:italic>\n            achieves improved balance between security and overheads, compared with the state-of-the-art works.\n          <\/jats:p>","DOI":"10.1145\/3604589","type":"journal-article","created":{"date-parts":[[2023,6,17]],"date-time":"2023-06-17T08:40:11Z","timestamp":1686991211000},"page":"1-18","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories"],"prefix":"10.1145","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8366-335X","authenticated-orcid":false,"given":"Taixin","family":"Li","sequence":"first","affiliation":[{"name":"Tsinghua University, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0001-4658-0106","authenticated-orcid":false,"given":"Boran","family":"Sun","sequence":"additional","affiliation":[{"name":"Tsinghua University, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2527-4246","authenticated-orcid":false,"given":"Hongtao","family":"Zhong","sequence":"additional","affiliation":[{"name":"Tsinghua University, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6393-8635","authenticated-orcid":false,"given":"Yixin","family":"Xu","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6266-6068","authenticated-orcid":false,"given":"Vijaykrishnan","family":"Narayanan","sequence":"additional","affiliation":[{"name":"The Pennsylvania State University, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9977-529X","authenticated-orcid":false,"given":"Liang","family":"Shi","sequence":"additional","affiliation":[{"name":"East China Normal University, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-3860-1311","authenticated-orcid":false,"given":"Tianyi","family":"Wang","sequence":"additional","affiliation":[{"name":"Daimler Greater China Ltd., China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-1483-4899","authenticated-orcid":false,"given":"Yao","family":"Yu","sequence":"additional","affiliation":[{"name":"Daimler Greater China Ltd., China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4672-8676","authenticated-orcid":false,"given":"Thomas","family":"K\u00e4mpfe","sequence":"additional","affiliation":[{"name":"Fraunhofer IPMS, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3628-3431","authenticated-orcid":false,"given":"Kai","family":"Ni","sequence":"additional","affiliation":[{"name":"Rochester Institute of Technology, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2421-353X","authenticated-orcid":false,"given":"Huazhong","family":"Yang","sequence":"additional","affiliation":[{"name":"Tsinghua University, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8051-3345","authenticated-orcid":false,"given":"Xueqing","family":"Li","sequence":"additional","affiliation":[{"name":"Tsinghua University, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2023,11,15]]},"reference":[{"key":"e_1_3_1_2_2","volume-title":"2018 IEEE International Electron Devices Meeting (IEDM)","author":"Arnaud F.","year":"2018","unstructured":"F. Arnaud, P. Zuliani, J. P. Reynard, A. Gandolfo, F. Disegni, P. Mattavelli, E. Gomiero, G. Samanni, C. Jahan, R. Berthelon, et\u00a0al. 2018. Truly innovative 28nm FDSOI technology for automotive micro-controller applications embedding 16MB phase change memory. In 2018 IEEE International Electron Devices Meeting (IEDM). IEEE, 18\u20134."},{"issue":"6","key":"e_1_3_1_3_2","first-page":"805","article-title":"Physics-based circuit-compatible SPICE model for ferroelectric transistors","volume":"37","author":"Aziz Ahmedullah","year":"2016","unstructured":"Ahmedullah Aziz, Swapnadip Ghosh, Suman Datta, and Sumeet Kumar Gupta. 2016. Physics-based circuit-compatible SPICE model for ferroelectric transistors. IEEE Electron Device Letters 37, 6 (2016), 805\u2013808.","journal-title":"IEEE Electron Device Letters"},{"issue":"11","key":"e_1_3_1_4_2","doi-asserted-by":"crossref","first-page":"1637","DOI":"10.1109\/LED.2020.3028339","article-title":"Highly scaled, high endurance,  \\(\\Omega\\) -gate, nanowire ferroelectric FET memory transistors","volume":"41","author":"Bae Jong-Ho","year":"2020","unstructured":"Jong-Ho Bae, Daewoong Kwon, Namho Jeon, Suraj Cheema, Ava Jiang Tan, Chenming Hu, and Sayeef Salahuddin. 2020. Highly scaled, high endurance, \\(\\Omega\\) -gate, nanowire ferroelectric FET memory transistors. IEEE Electron Device Letters 41, 11 (2020), 1637\u20131640.","journal-title":"IEEE Electron Device Letters"},{"key":"e_1_3_1_5_2","first-page":"232","volume-title":"International Workshop on Cryptographic Hardware and Embedded Systems","author":"Bucci Marco","year":"2006","unstructured":"Marco Bucci, Luca Giancane, Raimondo Luzzi, and Alessandro Trifiletti. 2006. Three-phase dual-rail pre-charge logic. In International Workshop on Cryptographic Hardware and Embedded Systems. Springer, 232\u2013241."},{"key":"e_1_3_1_6_2","doi-asserted-by":"crossref","first-page":"326","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830250","volume-title":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","author":"Chand Umesh","year":"2022","unstructured":"Umesh Chand, Mohamed M. Sabry Aly, Manohar Lal, Chen Chun-Kuei, Sonu Hooda, Shih-Hao Tsai, Zihang Fang, Hasita Veluri, and Aaron Voon-Yew Thean. 2022. Sub-10nm ultra-thin zno channel FET with record-high 561 \\(\\mu\\) A\/ \\(\\mu\\) m I ON at V DS 1V, High \\(\\mu\\) -84 cm 2\/Vs and1T-1RRAM memory cell demonstration memory implications for energy-efficient deep-learning computing. In 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). IEEE, 326\u2013327."},{"key":"e_1_3_1_7_2","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1016\/j.sse.2016.07.006","article-title":"A review of emerging non-volatile memory (NVM) technologies and applications","volume":"125","author":"Chen An","year":"2016","unstructured":"An Chen. 2016. A review of emerging non-volatile memory (NVM) technologies and applications. Solid-State Electronics 125 (2016), 25\u201338.","journal-title":"Solid-State Electronics"},{"key":"e_1_3_1_8_2","first-page":"1","volume-title":"2020 IEEE Symposium on VLSI Technology","author":"Deng Shan","year":"2020","unstructured":"Shan Deng, Guodong Yin, Wriddhi Chakraborty, Sourav Dutta, Suman Datta, Xueqing Li, and Kai Ni. 2020. A comprehensive model for ferroelectric FET capturing the key behaviors: Scalability, variation, stochasticity, and accumulation. In 2020 IEEE Symposium on VLSI Technology. IEEE, 1\u20132."},{"key":"e_1_3_1_9_2","doi-asserted-by":"crossref","first-page":"634","DOI":"10.3389\/fnins.2020.00634","article-title":"Supervised learning in all fefet-based spiking neural network: Opportunities and challenges","volume":"14","author":"Dutta Sourav","year":"2020","unstructured":"Sourav Dutta, Clemens Schafer, Jorge Gomez, Kai Ni, Siddharth Joshi, and Suman Datta. 2020. Supervised learning in all fefet-based spiking neural network: Opportunities and challenges. Frontiers in Neuroscience 14 (2020), 634.","journal-title":"Frontiers in Neuroscience"},{"key":"e_1_3_1_10_2","volume-title":"2020 IEEE International Electron Devices Meeting (IEDM)","author":"Dutta S.","year":"2020","unstructured":"S. Dutta, H. Ye, W. Chakraborty, Y.-C. Luo, M. San Jose, B. Grisafe, A. Khanna, I. Lightcap, S. Shinde, S. Yu, et\u00a0al. 2020. Monolithic 3D integration of high endurance multi-bit ferroelectric FET for accelerating compute-in-memory. In 2020 IEEE International Electron Devices Meeting (IEDM). IEEE, 36\u20134."},{"key":"e_1_3_1_11_2","first-page":"1","volume-title":"2020 IEEE\/ACM International Conference On Computer Aided Design (ICCAD)","author":"Gattu Navyata","year":"2020","unstructured":"Navyata Gattu, Mohammad Nasim Imtiaz Khan, Asmit De, and Swaroop Ghosh. 2020. Power side channel attack analysis and detection. In 2020 IEEE\/ACM International Conference On Computer Aided Design (ICCAD). IEEE, 1\u20137."},{"key":"e_1_3_1_12_2","first-page":"1","volume-title":"Annual Design Automation Conference","author":"George Sumitha","year":"2016","unstructured":"Sumitha George, Kaisheng Ma, Ahmedullah Aziz, Xueqing Li, Asif Khan, Sayeef Salahuddin, Meng-Fan Chang, Suman Datta, John Sampson, Sumeet Gupta, et\u00a0al. 2016. Nonvolatile memory design based on ferroelectric FETs. In Annual Design Automation Conference. 1\u20136."},{"key":"e_1_3_1_13_2","volume-title":"2021 IEEE International Electron Devices Meeting (IEDM)","author":"Gong Tiancheng","year":"2021","unstructured":"Tiancheng Gong, Qiao Hu, Danian Dong, Haijun Jiang, Jianguo Yang, Xiaoxin Xu, Xiaoming Chen, Qing Luo, Qi Liu, Steve S. Chung, et\u00a0al. 2021. A 128kb stochastic computing chip based on RRAM flicker noise with high noise density and nearly zero autocorrelation on 28-nm CMOS Platform. In 2021 IEEE International Electron Devices Meeting (IEDM). IEEE, 12\u20135."},{"key":"e_1_3_1_14_2","doi-asserted-by":"crossref","first-page":"459","DOI":"10.1109\/IEDM.2005.1609379","volume-title":"IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.","author":"Hosomi M.","year":"2005","unstructured":"M. Hosomi, H. Yamagishi, T. Yamamoto, K. Bessho, Y. Higo, K. Yamane, H. Yamada, M. Shoji, H. Hachino, C. Fukumoto, et\u00a0al. 2005. A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM. In IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest. IEEE, 459\u2013462."},{"key":"e_1_3_1_15_2","doi-asserted-by":"crossref","first-page":"141","DOI":"10.1109\/DFT.2016.7684086","volume-title":"2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","author":"Iyengar Anirudh","year":"2016","unstructured":"Anirudh Iyengar, Swaroop Ghosh, Nitin Rathi, and Helia Naeimi. 2016. Side channel attacks on STTRAM and low-overhead countermeasures. In 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). IEEE, 141\u2013146."},{"key":"e_1_3_1_16_2","first-page":"1","volume-title":"2021 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED)","author":"Kazemi Arman","year":"2021","unstructured":"Arman Kazemi, Mohammad Mehdi Sharifi, Zhuowen Zou, Michael Niemier, X. Sharon Hu, and Mohsen Imani. 2021. Mimhd: Accurate and efficient hyperdimensional inference using multi-bit in-memory computing. In 2021 IEEE\/ACM International Symposium on Low Power Electronics and Design (ISLPED). IEEE, 1\u20136."},{"issue":"4","key":"e_1_3_1_17_2","doi-asserted-by":"crossref","first-page":"38","DOI":"10.3390\/jlpea11040038","article-title":"Comprehensive study of side-channel attack on emerging non-volatile memories","volume":"11","author":"Khan Mohammad Nasim Imtiaz","year":"2021","unstructured":"Mohammad Nasim Imtiaz Khan, Shivam Bhasin, Bo Liu, Alex Yuan, Anupam Chattopadhyay, and Swaroop Ghosh. 2021. Comprehensive study of side-channel attack on emerging non-volatile memories. Journal of Low Power Electronics and Applications 11, 4 (2021), 38.","journal-title":"Journal of Low Power Electronics and Applications"},{"key":"e_1_3_1_18_2","first-page":"33","volume-title":"2017 IEEE International Conference on Computer Design (ICCD)","author":"Khan Mohammad Nasim Imtiaz","year":"2017","unstructured":"Mohammad Nasim Imtiaz Khan, Shivam Bhasin, Alex Yuan, Anupam Chattopadhyay, and Swaroop Ghosh. 2017. Side-channel attack on STTRAM based cache for cryptographic application. In 2017 IEEE International Conference on Computer Design (ICCD). IEEE, 33\u201340."},{"key":"e_1_3_1_19_2","first-page":"2.1.1\u20132.1.4","volume-title":"2021 IEEE International Electron Devices Meeting (IEDM)","author":"Kim D. S.","year":"2021","unstructured":"D. S. Kim, J. H. Bak, S. P. Ko, W. C. Lim, H. C. Shin, J. H. Lee, J. H. Park, J. H. Jeong, J. M. Lee, T. Kai, et\u00a0al. 2021. 28nm CIS-compatible embedded STT-MRAM for frame buffer memory. In 2021 IEEE International Electron Devices Meeting (IEDM). IEEE, 2.1.1\u20132.1.4."},{"issue":"3","key":"e_1_3_1_20_2","doi-asserted-by":"crossref","first-page":"39","DOI":"10.1109\/MDAT.2019.2902094","article-title":"Design of 2T\/cell and 3T\/cell nonvolatile memories with emerging ferroelectric FETs","volume":"36","author":"Li Xueqing","year":"2019","unstructured":"Xueqing Li, Juejian Wu, Kai Ni, Sumitha George, Kaisheng Ma, John Sampson, Sumeet Kumar Gupta, Yongpan Liu, Huazhong Yang, Suman Datta, et\u00a0al. 2019. Design of 2T\/cell and 3T\/cell nonvolatile memories with emerging ferroelectric FETs. IEEE Design & Test 36, 3 (2019), 39\u201345.","journal-title":"IEEE Design & Test"},{"key":"e_1_3_1_21_2","volume-title":"2019 IEEE International Electron Devices Meeting (IEDM)","author":"Luo Jin","year":"2019","unstructured":"Jin Luo, Liutao Yu, Tianyi Liu, Mengxuan Yang, Zhiyuan Fu, Zhongxin Liang, Liang Chen, Cheng Chen, Shuhan Liu, Si Wu, et\u00a0al. 2019. Capacitor-less stochastic leaky-FeFET neuron of both excitatory and inhibitory connections for SNN with reduced hardware cost. In 2019 IEEE International Electron Devices Meeting (IEDM). IEEE, 6\u20134."},{"issue":"8","key":"e_1_3_1_22_2","doi-asserted-by":"crossref","first-page":"1518","DOI":"10.1109\/TVLSI.2021.3087734","article-title":"SecNVM: Power side-channel elimination using on-chip capacitors for highly secure emerging NVM","volume":"29","author":"Nagarajan Karthikeyan","year":"2021","unstructured":"Karthikeyan Nagarajan, Farid Uddin Ahmed, Mohammad Nasim Imtiaz Khan, Asmit De, Masud H. Chowdhury, and Swaroop Ghosh. 2021. SecNVM: Power side-channel elimination using on-chip capacitors for highly secure emerging NVM. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29, 8 (2021), 1518\u20131528.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"e_1_3_1_23_2","first-page":"131","volume-title":"2018 IEEE Symposium on VLSI Technology","author":"Ni Kai","year":"2018","unstructured":"Kai Ni, Matthew Jerry, Jeffrey A. Smith, and Suman Datta. 2018. A circuit compatible accurate compact model for ferroelectric-FETs. In 2018 IEEE Symposium on VLSI Technology. IEEE, 131\u2013132."},{"issue":"11","key":"e_1_3_1_24_2","doi-asserted-by":"crossref","first-page":"1656","DOI":"10.1109\/LED.2018.2872347","article-title":"Write disturb in ferroelectric FETs and its implication for 1T-FeFET AND memory arrays","volume":"39","author":"Ni Kai","year":"2018","unstructured":"Kai Ni, Xueqing Li, Jeffrey A. Smith, Matthew Jerry, and Suman Datta. 2018. Write disturb in ferroelectric FETs and its implication for 1T-FeFET AND memory arrays. IEEE Electron Device Letters 39, 11 (2018), 1656\u20131659.","journal-title":"IEEE Electron Device Letters"},{"issue":"6","key":"e_1_3_1_25_2","doi-asserted-by":"crossref","first-page":"2461","DOI":"10.1109\/TED.2018.2829122","article-title":"Critical role of interlayer in  \\(Hf_{0.5}Zr_{0.5}O_2\\)  ferroelectric FET nonvolatile memory performance","volume":"65","author":"Ni Kai","year":"2018","unstructured":"Kai Ni, Pankaj Sharma, Jianchi Zhang, Matthew Jerry, Jeffery A. Smith, Kandabara Tapily, Robert Clark, Souvik Mahapatra, and Suman Datta. 2018. Critical role of interlayer in \\(Hf_{0.5}Zr_{0.5}O_2\\) ferroelectric FET nonvolatile memory performance. IEEE Transactions on Electron Devices 65, 6 (2018), 2461\u20132469.","journal-title":"IEEE Transactions on Electron Devices"},{"issue":"11","key":"e_1_3_1_26_2","doi-asserted-by":"crossref","first-page":"521","DOI":"10.1038\/s41928-019-0321-3","article-title":"Ferroelectric ternary content-addressable memory for one-shot learning","volume":"2","author":"Ni Kai","year":"2019","unstructured":"Kai Ni, Xunzhao Yin, Ann Franchesca Laguna, Siddharth Joshi, Stefan D\u00fcnkel, Martin Trentzsch, Johannes M\u00fcller, Sven Beyer, Michael Niemier, Xiaobo Sharon Hu, et\u00a0al. 2019. Ferroelectric ternary content-addressable memory for one-shot learning. Nature Electronics 2, 11 (2019), 521\u2013529.","journal-title":"Nature Electronics"},{"key":"e_1_3_1_27_2","volume-title":"53rd Annual Design Automation Conference","author":"Poremba Matthew","year":"2016","unstructured":"Matthew Poremba, Tao Zhang, and Yuan Xie. 2016. Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision. In 53rd Annual Design Automation Conference."},{"key":"e_1_3_1_28_2","first-page":"1","volume-title":"International Symposium on Low Power Electronics and Design","author":"Reis Dayane","year":"2018","unstructured":"Dayane Reis, Michael Niemier, and X. Sharon Hu. 2018. Computing in memory with FeFETs. In International Symposium on Low Power Electronics and Design. 1\u20136."},{"issue":"3","key":"e_1_3_1_29_2","doi-asserted-by":"crossref","first-page":"359","DOI":"10.1109\/LED.2018.2797887","article-title":"1T non-volatile memory design using sub-10nm ferroelectric FETs","volume":"39","author":"Sharma Ankit","year":"2018","unstructured":"Ankit Sharma and Kaushik Roy. 2018. 1T non-volatile memory design using sub-10nm ferroelectric FETs. IEEE Electron Device Letters 39, 3 (2018), 359\u2013362.","journal-title":"IEEE Electron Device Letters"},{"key":"e_1_3_1_30_2","volume-title":"2020 IEEE International Electron Devices Meeting (IEDM)","author":"Sharma Abhishek A.","year":"2020","unstructured":"Abhishek A. Sharma, Brian Doyle, Hui Jae Yoo, I.-Cheng Tung, Jack Kavalieros, Matthew V. Metz, Miriam Reshotko, Prashant Majhi, Tobias Brown-Heft, Yu-Jin Chen, et\u00a0al. 2020. High speed memory operation in channel-last, back-gated ferroelectric transistors. In 2020 IEEE International Electron Devices Meeting (IEDM). IEEE, 18\u20135."},{"key":"e_1_3_1_31_2","doi-asserted-by":"crossref","first-page":"188","DOI":"10.1109\/ICSC48311.2020.9182771","volume-title":"2020 6th International Conference on Signal Processing and Communication (ICSC)","author":"Singh Kirmender","year":"2020","unstructured":"Kirmender Singh and Sajal Khanna. 2020. Split memory based memory architecture with single-ended high speed sensing circuit to improve cache memory performance. In 2020 6th International Conference on Signal Processing and Communication (ICSC). IEEE, 188\u2013193."},{"issue":"4","key":"e_1_3_1_32_2","doi-asserted-by":"crossref","first-page":"449","DOI":"10.1109\/TC.2005.61","article-title":"Design and analysis of dual-rail circuits for security applications","volume":"54","author":"Sokolov Danil","year":"2005","unstructured":"Danil Sokolov, Julian Murphy, Alexander Bystrov, and Alexandre Yakovlev. 2005. Design and analysis of dual-rail circuits for security applications. IEEE Trans. Comput. 54, 4 (2005), 449\u2013460.","journal-title":"IEEE Trans. Comput."},{"issue":"6","key":"e_1_3_1_33_2","article-title":"Felix: A ferroelectric fet based low power mixed-signal in-memory architecture for dnn acceleration","volume":"21","author":"Soliman Taha","year":"2022","unstructured":"Taha Soliman, Nellie Laleni, Tobias Kirchner, Franz M\u00fcller, Ashish Shrivastava, Thomas K\u00e4mpfe, Andre Guntoro, and Norbert Wehn. 2022. Felix: A ferroelectric fet based low power mixed-signal in-memory architecture for dnn acceleration. ACM Transactions on Embedded Computing Systems (TECS) 21, 6 (2022), 25.","journal-title":"ACM Transactions on Embedded Computing Systems (TECS)"},{"key":"e_1_3_1_34_2","volume-title":"2018 IEEE International Electron Devices Meeting (IEDM)","author":"Song Z. T.","year":"2018","unstructured":"Z. T. Song, D. L. Cai, X. Li, L. Wang, Y. F. Chen, H. P. Chen, Q. Wang, Y. P. Zhan, and M. H. Ji. 2018. High endurance phase change memory chip implemented based on carbon-doped Ge 2 Sb 2 Te 5 in 40 nm node for embedded application. In 2018 IEEE International Electron Devices Meeting (IEDM). IEEE, 27\u20135."},{"key":"e_1_3_1_35_2","doi-asserted-by":"crossref","first-page":"445","DOI":"10.1109\/TELSKS.2001.955816","volume-title":"5th International Conference on Telecommunications in Modern Satellite, Cable and Broadcasting Service. (TELSIKS 2001). Proceedings of Papers (Cat. No. 01EX517)","volume":"2","author":"Stojcev M. K.","year":"2001","unstructured":"M. K. Stojcev and M. D. Krstic. 2001. Parity error detection in embedded computer system. In 5th International Conference on Telecommunications in Modern Satellite, Cable and Broadcasting Service. (TELSIKS 2001). Proceedings of Papers (Cat. No. 01EX517), Vol. 2. IEEE, 445\u2013450."},{"key":"e_1_3_1_36_2","first-page":"403","volume-title":"28th European Solid-State Circuits Conference","author":"Tiri Kris","year":"2002","unstructured":"Kris Tiri, Moonmoon Akmal, and Ingrid Verbauwhede. 2002. A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards. In 28th European Solid-State Circuits Conference. IEEE, 403\u2013406."},{"key":"e_1_3_1_37_2","doi-asserted-by":"crossref","first-page":"246","DOI":"10.1109\/DATE.2004.1268856","volume-title":"Design, Automation and Test in Europe Conference and Exhibition","volume":"1","author":"Tiri Kris","year":"2004","unstructured":"Kris Tiri and Ingrid Verbauwhede. 2004. A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation. In Design, Automation and Test in Europe Conference and Exhibition, Vol. 1. IEEE, 246\u2013251."},{"key":"e_1_3_1_38_2","volume-title":"2016 IEEE International Electron Devices Meeting (IEDM)","author":"Trentzsch Martin","year":"2016","unstructured":"Martin Trentzsch, S. Flachowsky, R. Richter, J. Paul, B. Reimer, D. Utess, S. Jansen, H. Mulaosmanovic, S. M\u00fcller, S. Slesazeck, et\u00a0al. 2016. A 28nm HKMG super low power embedded NVM technology based on ferroelectric FETs. In 2016 IEEE International Electron Devices Meeting (IEDM). IEEE, 11\u20135."},{"issue":"7","key":"e_1_3_1_39_2","doi-asserted-by":"crossref","first-page":"074003","DOI":"10.1088\/0022-3727\/46\/7\/074003","article-title":"Low-power non-volatile spintronic memory: STT-RAM and beyond","volume":"46","author":"Wang K. L.","year":"2013","unstructured":"K. L. Wang, J. G. Alzate, and P. Khalili Amiri. 2013. Low-power non-volatile spintronic memory: STT-RAM and beyond. Journal of Physics D: Applied Physics 46, 7 (2013), 074003.","journal-title":"Journal of Physics D: Applied Physics"},{"key":"e_1_3_1_40_2","first-page":"1","volume-title":"56th Annual Design Automation Conference 2019","author":"Wu Juejian","year":"2019","unstructured":"Juejian Wu, Hongtao Zhong, Kai Ni, Yongpan Liu, Huazhong Yang, and Xueqing Li. 2019. A 3T\/cell practical embedded nonvolatile memory supporting symmetric read and write access based on ferroelectric FETs. In 56th Annual Design Automation Conference 2019. 1\u20136."},{"issue":"8","key":"e_1_3_1_41_2","doi-asserted-by":"crossref","first-page":"499","DOI":"10.1109\/T-ED.1974.17955","article-title":"A new ferroelectric memory device, metal-ferroelectric-semiconductor transistor","volume":"21","author":"Wu Shu-Yau","year":"1974","unstructured":"Shu-Yau Wu. 1974. A new ferroelectric memory device, metal-ferroelectric-semiconductor transistor. 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