{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,4]],"date-time":"2026-06-04T03:25:07Z","timestamp":1780543507470,"version":"3.54.1"},"publisher-location":"New York, NY, USA","reference-count":45,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,8,7]],"date-time":"2023-08-07T00:00:00Z","timestamp":1691366400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"European High-Performance Computing Joint Undertaking (JU)","award":["956702"],"award-info":[{"award-number":["956702"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,8,7]]},"DOI":"10.1145\/3605573.3605586","type":"proceedings-article","created":{"date-parts":[[2023,9,13]],"date-time":"2023-09-13T16:21:16Z","timestamp":1694622076000},"page":"828-838","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":11,"title":["JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3409-8651","authenticated-orcid":false,"given":"Jing","family":"Chen","sequence":"first","affiliation":[{"name":"Chalmers University of Technology, Sweden"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9783-8357","authenticated-orcid":false,"given":"Madhavan","family":"Manivannan","sequence":"additional","affiliation":[{"name":"Chalmers University of Technology, Sweden"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9878-4509","authenticated-orcid":false,"given":"Bhavishya","family":"Goel","sequence":"additional","affiliation":[{"name":"Chalmers University of Technology, Sweden"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7583-6609","authenticated-orcid":false,"given":"Miquel","family":"Peric\u00e0s","sequence":"additional","affiliation":[{"name":"Chalmers University of Technology, Sweden"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2023,9,13]]},"reference":[{"key":"e_1_3_2_1_1_1","unstructured":"2014. Documentation of StarPU. https:\/\/files.inria.fr\/starpu\/doc\/starpu.pdf."},{"key":"e_1_3_2_1_2_1","unstructured":"2015. ODROID XU4. https:\/\/magazine.odroid.com\/wp-content\/uploads\/odroid-xu4-user-manual.pdf."},{"key":"e_1_3_2_1_3_1","unstructured":"2017. Jetson TX2 Module. https:\/\/developer.nvidia.com\/embedded\/jetson-tx2."},{"key":"e_1_3_2_1_4_1","unstructured":"2018. XiTAO Runtime. https:\/\/github.com\/CHART-Team\/xitao.git."},{"key":"e_1_3_2_1_5_1","unstructured":"2019. DDR5\/4\/3\/2: How Memory Density and Speed Increased with each Generation of DDR. https:\/\/blogs.synopsys.com\/vip-central\/2019\/02\/27\/ddr5-4-3-2-how-memory-density-and-speed-increased-with-each-generation-of-ddr\/."},{"key":"e_1_3_2_1_6_1","unstructured":"2020. ARM BIG.LITTLE. https:\/\/www.arm.com\/why-arm\/technologies\/big-little."},{"key":"e_1_3_2_1_7_1","unstructured":"2020. Biomarker Discovery. https:\/\/legato-project.eu\/use-cases\/healthcare."},{"key":"e_1_3_2_1_8_1","volume-title":"Apple A16 Bionic. https:\/\/en.wikipedia.org\/wiki\/Apple_A16","unstructured":"2022. Apple A16 Bionic. https:\/\/en.wikipedia.org\/wiki\/Apple_A16."},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/IGSC48788.2019.8957174"},{"key":"e_1_3_2_1_10_1","volume-title":"CATA: Criticality Aware Task Acceleration for Multicore Processors. In 2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS).","author":"Castillo E.","unstructured":"E. Castillo, M. Moreto, M. Casas, L. Alvarez, E. Vallejo, K. Chronaki, R. Badia, J.\u00a0L. Bosque, R. Beivide, E. Ayguade, J. Labarta, and M. Valero. 2016. CATA: Criticality Aware Task Acceleration for Multicore Processors. In 2016 IEEE International Parallel and Distributed Processing Symposium (IPDPS)."},{"key":"e_1_3_2_1_11_1","volume-title":"ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes. ACM Trans. Archit. Code Optim. (mar","author":"Chen Jing","year":"2022","unstructured":"Jing Chen, Madhavan Manivannan, Mustafa Abduljabbar, and Miquel Peric\u00e0s. 2022. ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes. ACM Trans. Archit. Code Optim. (mar 2022)."},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"crossref","unstructured":"Jing Chen Madhavan Manivannan Bhavishya Goel Mustafa Abduljabbar and Miquel Peric\u00e0s. 2022. STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures. In 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD).","DOI":"10.1109\/SBAC-PAD55451.2022.00043"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2008.4636091"},{"key":"e_1_3_2_1_14_1","doi-asserted-by":"publisher","DOI":"10.3390\/en13092409"},{"key":"e_1_3_2_1_15_1","unstructured":"Sanjeev Das Jan Werner Manos Antonakakis Michalis Polychronakis and Fabian Monrose. 2019. SoK: The Challenges Pitfalls and Perils of Using Hardware Performance Counters for Security. In 2019 IEEE S&P."},{"key":"e_1_3_2_1_16_1","doi-asserted-by":"publisher","DOI":"10.1145\/1998582.1998590"},{"key":"e_1_3_2_1_17_1","volume-title":"CoScale: Coordinating CPU and Memory System DVFS in Server Systems. In 2012 45th Annual IEEE\/ACM International Symposium on Microarchitecture.","author":"Deng Qingyuan","year":"2012","unstructured":"Qingyuan Deng, David Meisner, Abhishek Bhattacharjee, Thomas\u00a0F. Wenisch, and Ricardo Bianchini. 2012. CoScale: Coordinating CPU and Memory System DVFS in Server Systems. In 2012 45th Annual IEEE\/ACM International Symposium on Microarchitecture."},{"key":"e_1_3_2_1_18_1","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950392"},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2009.64"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2009.64"},{"key":"e_1_3_2_1_21_1","volume-title":"Energy Efficiency Modeling of Parallel Applications. In SC18: International Conference for High Performance Computing, Networking, Storage and Analysis.","author":"Endrei Mark","year":"2018","unstructured":"Mark Endrei, Chao Jin, Minh\u00a0Ngoc Dinh, David Abramson, Heidi Poxon, Luiz DeRose, and Bronis\u00a0R. de Supinski. 2018. Energy Efficiency Modeling of Parallel Applications. In SC18: International Conference for High Performance Computing, Networking, Storage and Analysis."},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1145\/277650.277725"},{"key":"e_1_3_2_1_23_1","volume-title":"Measurement, Modeling, and Characterization for Energy-efficient Computing","author":"Goel Bhavishya","unstructured":"Bhavishya Goel. 2016. Measurement, Modeling, and Characterization for Energy-efficient Computing. Chalmers University of Technology."},{"key":"e_1_3_2_1_24_1","unstructured":"Houzeaux Guillaume and Vazquez Mariano. [n.d.]. Alya Application. https:\/\/www.bsc.es\/research-development\/research-areas\/engineering-simulations\/alya-high-performance-computational."},{"key":"e_1_3_2_1_25_1","volume-title":"SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile Processors. In 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA).","author":"Haj-Yahya Jawad","year":"2020","unstructured":"Jawad Haj-Yahya, Mohammed Alser, Jeremie Kim, A.\u00a0Giray Ya\u011fl\u0131k\u00e7\u0131, Nandita Vijaykumar, Efraim Rotem, and Onur Mutlu. 2020. SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile Processors. In 2020 ACM\/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)."},{"key":"e_1_3_2_1_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2020.3031911"},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283790"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"crossref","unstructured":"Simon Holmbacka and J\u00f6rg Keller. 2017. Workload Type-Aware Scheduling on big.LITTLE Platforms. In Algorithms and Architectures for Parallel Processing.","DOI":"10.1007\/978-3-319-65482-9_1"},{"key":"e_1_3_2_1_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.30"},{"key":"e_1_3_2_1_30_1","doi-asserted-by":"publisher","DOI":"10.1145\/2854038.2854047"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"crossref","unstructured":"Tipp Moseley Neil Vachharajani and William Jalby. 2011. Hardware Performance Monitoring for the Rest of Us: A Position and Survey. In Network and Parallel Computing.","DOI":"10.1007\/978-3-642-24403-2_23"},{"key":"e_1_3_2_1_32_1","volume-title":"Emerging Computing: From Devices to Systems","author":"Mutlu Onur","unstructured":"Onur Mutlu, Saugata Ghose, Juan G\u00f3mez-Luna, and Rachata Ausavarungnirun. 2023. A modern primer on processing in memory. In Emerging Computing: From Devices to Systems. Springer, 171\u2013243."},{"key":"e_1_3_2_1_33_1","volume-title":"Combining Dynamic Concurrency Throttling with Voltage and Frequency Scaling on Task-Based Programming Models. In 50th International Conference on Parallel Processing(ICPP","author":"Mu\u00f1oz Antoni Navarro","year":"2021","unstructured":"Antoni Navarro Mu\u00f1oz, Arthur F.\u00a0Lorenzon, Eduard Ayguad\u00e9\u00a0Parra, and Vicen\u00e7 Beltran\u00a0Querol. 2021. Combining Dynamic Concurrency Throttling with Voltage and Frequency Scaling on Task-Based Programming Models. In 50th International Conference on Parallel Processing(ICPP 2021)."},{"key":"e_1_3_2_1_34_1","unstructured":"OpenMP Architecture Review Board. 2018. OpenMP Application Program Interface. Version 5.0."},{"key":"e_1_3_2_1_35_1","volume-title":"A scheduling selection process for energy\u2010efficient task execution on DVFS processors. Concurrency and Computation: Practice and Experience 31 (10","author":"Rauber Thomas","year":"2018","unstructured":"Thomas Rauber and Gudula R\u00fcnger. 2018. A scheduling selection process for energy\u2010efficient task execution on DVFS processors. Concurrency and Computation: Practice and Experience 31 (10 2018)."},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/TMSCS.2017.2755619"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1145\/2925426.2926260"},{"key":"e_1_3_2_1_38_1","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541971"},{"key":"e_1_3_2_1_39_1","volume-title":"Alder Lake Architecture. In 2021 IEEE Hot Chips 33 Symposium (HCS).","author":"Rotem Efraim","year":"2021","unstructured":"Efraim Rotem, Yuli Mandelblat, Vadim Basin, Eli Weissmann, Arik Gihon, Rajshree Chabukswar, Russ Fenger, and Monica Gupta. 2021. Alder Lake Architecture. In 2021 IEEE Hot Chips 33 Symposium (HCS)."},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3013062"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"publisher","DOI":"10.1145\/2701310.2701311"},{"key":"e_1_3_2_1_42_1","volume-title":"Very deep convolutional networks for large-scale image recognition. arXiv preprint arXiv:1409.1556","author":"Simonyan Karen","year":"2014","unstructured":"Karen Simonyan and Andrew Zisserman. 2014. Very deep convolutional networks for large-scale image recognition. arXiv preprint arXiv:1409.1556 (2014)."},{"key":"e_1_3_2_1_43_1","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-016-1680-4"},{"key":"e_1_3_2_1_44_1","volume-title":"Asymmetry-Aware Work-Stealing Runtimes. In 2016 ACM\/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA). 40\u201352","author":"Torng Christopher","year":"2016","unstructured":"Christopher Torng, Moyang Wang, and Christopher Batten. 2016. Asymmetry-Aware Work-Stealing Runtimes. In 2016 ACM\/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA). 40\u201352."},{"key":"e_1_3_2_1_45_1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2016.311"}],"event":{"name":"ICPP 2023: 52nd International Conference on Parallel Processing","location":"Salt Lake City UT USA","acronym":"ICPP 2023"},"container-title":["Proceedings of the 52nd International Conference on Parallel Processing"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3605573.3605586","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3605573.3605586","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T17:49:04Z","timestamp":1750182544000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3605573.3605586"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,8,7]]},"references-count":45,"alternative-id":["10.1145\/3605573.3605586","10.1145\/3605573"],"URL":"https:\/\/doi.org\/10.1145\/3605573.3605586","relation":{},"subject":[],"published":{"date-parts":[[2023,8,7]]},"assertion":[{"value":"2023-09-13","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}