{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,6]],"date-time":"2026-06-06T01:15:26Z","timestamp":1780708526458,"version":"3.54.1"},"reference-count":109,"publisher":"Association for Computing Machinery (ACM)","issue":"6","license":[{"start":{"date-parts":[[2024,9,11]],"date-time":"2024-09-11T00:00:00Z","timestamp":1726012800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key R&D Program of China","doi-asserted-by":"crossref","award":["2022YFB4401700"],"award-info":[{"award-number":["2022YFB4401700"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Nature Science Foundation of Shanghai","award":["22ZR1442000, 23ZR1442300"],"award-info":[{"award-number":["22ZR1442000, 23ZR1442300"]}]},{"name":"ShanghaiTech Startup Funding"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2024,11,30]]},"abstract":"<jats:p>\n            Persistent memory (pmem) products bring the persistence domain up to the memory level. Intel recently introduced the eADR feature that guarantees to flush data buffered in CPU cache to pmem on a power outage, thereby making the CPU cache a\n            <jats:italic>transient persistence domain<\/jats:italic>\n            . Researchers have explored how to enable the\n            <jats:italic>atomic durability<\/jats:italic>\n            for applications\u2019 in-pmem data. In this article, we exploit the eADR-supported CPU cache to do so. A modified cache line, until written back to pmem, is a natural redo log copy of the in-pmem data. However, a write-back due to cache replacement or eADR on a crash overwrites the original copy. We accordingly developed Hercules, a hardware logging design for the transaction-level atomic durability, with supportive components installed in CPU cache, memory controller (MC), and pmem. When a transaction commits, Hercules\n            <jats:italic>commits on-chip<\/jats:italic>\n            its data staying in cache lines. For cache lines evicted before the commit, Hercules asks the MC to redirect and persist them into in-pmem log entries and\n            <jats:italic>commits<\/jats:italic>\n            them\n            <jats:italic>off-chip<\/jats:italic>\n            upon committing the transaction. Hercules lazily conducts pmem writes only for cache replacements at runtime. On a crash, Hercules saves metadata and data for active transactions into pmem for recovery. Experiments show that, by using CPU cache for both buffering and logging, Hercules yields much higher throughput and incurs significantly fewer pmem writes than state-of-the-art designs.\n          <\/jats:p>","DOI":"10.1145\/3607473","type":"journal-article","created":{"date-parts":[[2023,7,6]],"date-time":"2023-07-06T12:10:05Z","timestamp":1688645405000},"page":"1-34","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":1,"title":["Hercules: Enabling Atomic Durability for Persistent Memory with Transient Persistence Domain"],"prefix":"10.1145","volume":"23","author":[{"ORCID":"https:\/\/orcid.org\/0009-0002-1640-5777","authenticated-orcid":false,"given":"Chongnan","family":"Ye","sequence":"first","affiliation":[{"name":"School of Information Science and Technology, ShanghaiTech University, China and Shanghai Engineering Research Center of Energy Efficient and Custom AI IC, Shanghai, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0279-8381","authenticated-orcid":false,"given":"Meng","family":"Chen","sequence":"additional","affiliation":[{"name":"School of Information Science and Technology, ShanghaiTech University, China and Shanghai Engineering Research Center of Energy Efficient and Custom AI IC, Shanghai, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5570-0018","authenticated-orcid":false,"given":"Qisheng","family":"Jiang","sequence":"additional","affiliation":[{"name":"School of Information Science and Technology, ShanghaiTech University, China and Shanghai Engineering Research Center of Energy Efficient and Custom AI IC, Shanghai, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9069-2650","authenticated-orcid":false,"given":"Chundong","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Information Science and Technology, ShanghaiTech University, China and Shanghai Engineering Research Center of Energy Efficient and Custom AI IC, Shanghai, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"320","published-online":{"date-parts":[[2024,9,11]]},"reference":[{"key":"e_1_3_1_2_2","article-title":"SK Hynix Developed the World\u2019s Highest Density 16GB NVDIMM","author":"Hynix SK","year":"2014","unstructured":"SK Hynix. 2014. SK Hynix Developed the World\u2019s Highest Density 16GB NVDIMM. Retrieved from https:\/\/news.skhynix.com\/sk-hynix-developed-the-worlds-highest-density-16gb-nvdimm\/. (21 October2014). Accessed: 06-15-2022.","journal-title":"https:\/\/news.skhynix.com\/sk-hynix-developed-the-worlds-highest-density-16gb-nvdimm\/"},{"key":"e_1_3_1_3_2","article-title":"3D XPoint \\(^{\\text {TM}}\\) : A breakthrough in non-volatile memory technology","unstructured":"Intel. 3D XPoint \\(^{\\text {TM}}\\) : A breakthrough in non-volatile memory technology. Retrieved from https:\/\/www.intel.com\/content\/www\/us\/en\/architecture-and-technology\/intel-micron-3d-xpoint-webcast.html. Accessed: 04-22-2022.","journal-title":"https:\/\/www.intel.com\/content\/www\/us\/en\/architecture-and-technology\/intel-micron-3d-xpoint-webcast.html"},{"key":"e_1_3_1_4_2","article-title":"NVDIMM: Persistent Memory Performance","year":"2017","unstructured":"Micron. 2017. NVDIMM: Persistent Memory Performance. Retrieved from https:\/\/media-www.micron.com\/-\/media\/client\/global\/documents\/products\/product-flyer\/nvdimm_flyer.pdf?rev=0c295086bb4c43729b89f369219259bc. (21 December2017). Accessed: 06-15-2022.","journal-title":"https:\/\/media-www.micron.com\/-\/media\/client\/global\/documents\/products\/product-flyer\/nvdimm_flyer.pdf?rev=0c295086bb4c43729b89f369219259bc"},{"key":"e_1_3_1_5_2","article-title":"Dell EMC NVDIMM-N Persistent Memory: user guide","year":"2021","unstructured":"Dell. 2021. Dell EMC NVDIMM-N Persistent Memory: user guide. Retrieved from https:\/\/dl.dell.com\/topicspdf\/nvdimm_n_user_guide_en-us.pdf. (15 February2021). Accessed: 06-15-2022.","journal-title":"https:\/\/dl.dell.com\/topicspdf\/nvdimm_n_user_guide_en-us.pdf"},{"key":"e_1_3_1_6_2","article-title":"HPE NVDIMMs","author":"Enterprise Hewlett Packard","year":"2021","unstructured":"Hewlett Packard Enterprise. 2021. HPE NVDIMMs. Retrieved from https:\/\/www.hpe.com\/psnow\/doc\/c04939369.html. (15 November2021). Accessed: 06-15-2022.","journal-title":"https:\/\/www.hpe.com\/psnow\/doc\/c04939369.html"},{"key":"e_1_3_1_7_2","article-title":"Intel\u00ae OptaneTM Memory\u2014Responsive Memory, Accelerated Performance","year":"2022","unstructured":"Intel. 2022. Intel\u00ae OptaneTM Memory\u2014Responsive Memory, Accelerated Performance. Retrieved from https:\/\/www.intel.com\/content\/www\/us\/en\/products\/details\/memory-storage\/optane-memory.html. (15 July2022). Accessed: 07-13-2022.","journal-title":"https:\/\/www.intel.com\/content\/www\/us\/en\/products\/details\/memory-storage\/optane-memory.html"},{"key":"e_1_3_1_8_2","article-title":"Everspin Releases Highest Density MRAM Products to Create Fastest And Most Reliable Non-Volatile Storage Class Memory","year":"2016","unstructured":"Everspin. 2016. Everspin Releases Highest Density MRAM Products to Create Fastest And Most Reliable Non-Volatile Storage Class Memory. Retrieved from https:\/\/www.everspin.com\/sites\/default\/files\/Everspin%20Releases%20Highest%20Density%20MRAM%20Products%20FINAL%20041216.pdf. (13 April2016). Accessed: 07-10-2022.","journal-title":"https:\/\/www.everspin.com\/sites\/default\/files\/Everspin%20Releases%20Highest%20Density%20MRAM%20Products%20FINAL%20041216.pdf"},{"key":"e_1_3_1_9_2","article-title":"Intel\u00ae 64 and IA-32 architectures software developer manuals","unstructured":"Intel. Intel\u00ae 64 and IA-32 architectures software developer manuals. Retrieved from https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/intel-sdm.html. Accessed: 05-12-2022.","journal-title":"https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/intel-sdm.html"},{"key":"e_1_3_1_10_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4842-4932-1"},{"key":"e_1_3_1_11_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-79205-2"},{"key":"e_1_3_1_12_2","doi-asserted-by":"publisher","DOI":"10.14778\/3436905.3436921"},{"key":"e_1_3_1_13_2","doi-asserted-by":"publisher","DOI":"10.1145\/3453483.3454027"},{"key":"e_1_3_1_14_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00070"},{"key":"e_1_3_1_15_2","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124539"},{"key":"e_1_3_1_16_2","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358321"},{"key":"e_1_3_1_17_2","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480118"},{"key":"e_1_3_1_18_2","article-title":"eADR: New Opportunities for Persistent Memory Applications","year":"2021","unstructured":"Intel. 2021. eADR: New Opportunities for Persistent Memory Applications. Retrieved from https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/eadr-new-opportunities-for-persistent-memory-applications.html. (15 January2021). Accessed: 07-15-2022.","journal-title":"https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/eadr-new-opportunities-for-persistent-memory-applications.html"},{"key":"e_1_3_1_19_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00019"},{"key":"e_1_3_1_20_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00022"},{"key":"e_1_3_1_21_2","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540744"},{"key":"e_1_3_1_22_2","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669117"},{"key":"e_1_3_1_23_2","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736023"},{"key":"e_1_3_1_24_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.101"},{"key":"e_1_3_1_25_2","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694352"},{"key":"e_1_3_1_26_2","doi-asserted-by":"publisher","DOI":"10.1145\/3243906"},{"key":"e_1_3_1_27_2","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378515"},{"key":"e_1_3_1_28_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00086"},{"key":"e_1_3_1_29_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974684"},{"key":"e_1_3_1_30_2","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062272"},{"key":"e_1_3_1_31_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00052"},{"key":"e_1_3_1_32_2","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830802"},{"key":"e_1_3_1_33_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446055"},{"key":"e_1_3_1_34_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.50"},{"key":"e_1_3_1_35_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00048"},{"key":"e_1_3_1_36_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00049"},{"key":"e_1_3_1_37_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00037"},{"key":"e_1_3_1_38_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00055"},{"key":"e_1_3_1_39_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00057"},{"key":"e_1_3_1_40_2","article-title":"The gem5 simulator","unstructured":"Gem5. The gem5 simulator. Retrieved from https:\/\/www.gem5.org\/. Accessed: 01-30-2022.","journal-title":"https:\/\/www.gem5.org\/"},{"key":"e_1_3_1_41_2","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"e_1_3_1_42_2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.24"},{"key":"e_1_3_1_43_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749753"},{"key":"e_1_3_1_44_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.66"},{"key":"e_1_3_1_45_2","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593220"},{"key":"e_1_3_1_46_2","doi-asserted-by":"publisher","DOI":"10.5555\/2691365.2691426"},{"key":"e_1_3_1_47_2","doi-asserted-by":"publisher","DOI":"10.5555\/3199700.3199736"},{"key":"e_1_3_1_48_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2017.110"},{"key":"e_1_3_1_49_2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2779151"},{"key":"e_1_3_1_50_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056056"},{"key":"e_1_3_1_51_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.52"},{"key":"e_1_3_1_52_2","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322271"},{"key":"e_1_3_1_53_2","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358328"},{"key":"e_1_3_1_54_2","article-title":"Advanced Memory\u2014DDR4 NVDIMM","author":"Technologies SMART Modular","year":"2022","unstructured":"SMART Modular Technologies. 2022. Advanced Memory\u2014DDR4 NVDIMM. Retrieved from https:\/\/www.smartm.com\/api\/download\/fetch\/17. (20 January2022). Accessed: 06-15-2022.","journal-title":"https:\/\/www.smartm.com\/api\/download\/fetch\/17"},{"key":"e_1_3_1_55_2","first-page":"167","volume-title":"Proceedings of the 13th USENIX Conference on File and Storage Technologies (FAST\u201915)","author":"Yang Jun","year":"2015","unstructured":"Jun Yang, Qingsong Wei, Cheng Chen, Chundong Wang, Khai Leong Yong, and Bingsheng He. 2015. NV-Tree: Reducing consistency cost for NVM-based single level systems. In Proceedings of the 13th USENIX Conference on File and Storage Technologies (FAST\u201915). USENIX Association, 167\u2013181. Retrieved from https:\/\/www.usenix.org\/conference\/fast15\/technical-sessions\/presentation\/yang."},{"key":"e_1_3_1_56_2","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950379"},{"key":"e_1_3_1_57_2","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541957"},{"key":"e_1_3_1_58_2","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950380"},{"key":"e_1_3_1_59_2","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037714"},{"key":"e_1_3_1_60_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00049"},{"key":"e_1_3_1_61_2","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378483"},{"key":"e_1_3_1_62_2","doi-asserted-by":"publisher","DOI":"10.5555\/3386691.3386708"},{"key":"e_1_3_1_63_2","doi-asserted-by":"publisher","DOI":"10.1145\/3465402"},{"key":"e_1_3_1_64_2","doi-asserted-by":"publisher","DOI":"10.1145\/3124680.3124729"},{"key":"e_1_3_1_65_2","doi-asserted-by":"publisher","DOI":"10.1145\/3559009.3569676"},{"key":"e_1_3_1_66_2","doi-asserted-by":"publisher","DOI":"10.1145\/2150976.2151018"},{"key":"e_1_3_1_67_2","article-title":"Restricted Transactional Memory Overview","year":"2023","unstructured":"Intel. 2023. Restricted Transactional Memory Overview. Retrieved from https:\/\/www.intel.com\/content\/www\/us\/en\/develop\/documentation\/cpp-compiler-developer-guide-and-reference\/top\/compiler-reference\/intrinsics\/intrinsics-for-avx2\/intrinsics-for-tsx\/intrinsics-for-restrict-transactional-mem-ops\/restricted-transactional-memory-overview.html. (09 March2023). Accessed: 03-09-2023.","journal-title":"https:\/\/www.intel.com\/content\/www\/us\/en\/develop\/documentation\/cpp-compiler-developer-guide-and-reference\/top\/compiler-reference\/intrinsics\/intrinsics-for-avx2\/intrinsics-for-tsx\/intrinsics-for-restrict-transactional-mem-ops\/restricted-transactional-memory-overview.html"},{"key":"e_1_3_1_68_2","first-page":"17","volume-title":"Proceedings of the 20th USENIX Conference on File and Storage Technologies, FAST 2022","author":"Yi Jifei","year":"2022","unstructured":"Jifei Yi, Mingkai Dong, Fangnuo Wu, and Haibo Chen. 2022. HTMFS: Strong consistency comes for free with hardware transactional memory in persistent memory file systems. In Proceedings of the 20th USENIX Conference on File and Storage Technologies, FAST 2022. Dean Hildebrand and Donald E. Porter (Eds.), USENIX Association, 17\u201334. Retrieved from https:\/\/www.usenix.org\/conference\/fast22\/presentation\/yi-htmfs."},{"key":"e_1_3_1_69_2","doi-asserted-by":"publisher","DOI":"10.5555\/2591272.2591280"},{"key":"e_1_3_1_70_2","doi-asserted-by":"publisher","DOI":"10.1145\/3470496.3527425"},{"key":"e_1_3_1_71_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00021"},{"key":"e_1_3_1_72_2","doi-asserted-by":"publisher","DOI":"10.1145\/2851504"},{"key":"e_1_3_1_73_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2000.898054"},{"key":"e_1_3_1_74_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237033"},{"key":"e_1_3_1_75_2","doi-asserted-by":"publisher","DOI":"10.1145\/1787275.1787314"},{"key":"e_1_3_1_76_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2015.83"},{"key":"e_1_3_1_77_2","doi-asserted-by":"publisher","DOI":"10.5555\/2855046"},{"key":"e_1_3_1_78_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00024"},{"key":"e_1_3_1_79_2","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00004"},{"key":"e_1_3_1_80_2","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155671"},{"key":"e_1_3_1_81_2","doi-asserted-by":"publisher","DOI":"10.1145\/3037697.3037701"},{"key":"e_1_3_1_82_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00035"},{"key":"e_1_3_1_83_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00033"},{"key":"e_1_3_1_84_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00055"},{"key":"e_1_3_1_85_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00050"},{"key":"e_1_3_1_86_2","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.24"},{"key":"e_1_3_1_87_2","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080240"},{"key":"e_1_3_1_88_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00021"},{"key":"e_1_3_1_89_2","article-title":"Write buffer","author":"contributors. Wikipedia","year":"2023","unstructured":"Wikipedia contributors.2023. Write buffer. Retrieved from https:\/\/en.wikipedia.org\/w\/index.php?title=Write_buffer&oldid=1067314254. (1 March2023). Accessed: 03-01-2023.","journal-title":"https:\/\/en.wikipedia.org\/w\/index.php?title=Write_buffer&oldid=1067314254"},{"key":"e_1_3_1_90_2","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2008.54"},{"key":"e_1_3_1_91_2","doi-asserted-by":"publisher","DOI":"10.1145\/514191.514219"},{"key":"e_1_3_1_92_2","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00087"},{"key":"e_1_3_1_93_2","doi-asserted-by":"publisher","DOI":"10.1145\/3319535.3354252"},{"key":"e_1_3_1_94_2","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2017.32"},{"key":"e_1_3_1_95_2","article-title":"Introduction to Cache Allocation Technology in the Intel\u00ae Xeon\u00ae Processor E5 v4 Family","year":"2023","unstructured":"Intel. 2023. Introduction to Cache Allocation Technology in the Intel\u00ae Xeon\u00ae Processor E5 v4 Family. Retrieved from https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/introduction-to-cache-allocation-technology.html. (04 March2023). Accessed: 03-04-2023.","journal-title":"https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/articles\/technical\/introduction-to-cache-allocation-technology.html"},{"key":"e_1_3_1_96_2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-96983-1_43"},{"key":"e_1_3_1_97_2","doi-asserted-by":"publisher","DOI":"10.1145\/2063384.2063436"},{"key":"e_1_3_1_98_2","doi-asserted-by":"publisher","DOI":"10.1145\/3465402"},{"key":"e_1_3_1_99_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00020"},{"key":"e_1_3_1_100_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00062"},{"key":"e_1_3_1_101_2","first-page":"323","volume-title":"Proceedings of the 14th USENIX Conference on File and Storage Technologies (FAST 16)","author":"Xu Jian","year":"2016","unstructured":"Jian Xu and Steven Swanson. 2016. NOVA: A log-structured file system for hybrid volatile\/non-volatile main memories. In Proceedings of the 14th USENIX Conference on File and Storage Technologies (FAST 16). USENIX Association, 323\u2013338."},{"key":"e_1_3_1_102_2","doi-asserted-by":"publisher","DOI":"10.1145\/3341301.3359631"},{"key":"e_1_3_1_103_2","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000074"},{"key":"e_1_3_1_104_2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00026"},{"key":"e_1_3_1_105_2","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2014.6983056"},{"key":"e_1_3_1_106_2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2960485"},{"key":"e_1_3_1_107_2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.847907"},{"key":"e_1_3_1_108_2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2007.911072"},{"key":"e_1_3_1_109_2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00073"},{"key":"e_1_3_1_110_2","doi-asserted-by":"publisher","DOI":"10.1145\/1807128.1807152"}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3607473","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3607473","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T16:37:35Z","timestamp":1750178255000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3607473"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,9,11]]},"references-count":109,"journal-issue":{"issue":"6","published-print":{"date-parts":[[2024,11,30]]}},"alternative-id":["10.1145\/3607473"],"URL":"https:\/\/doi.org\/10.1145\/3607473","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"value":"1539-9087","type":"print"},{"value":"1558-3465","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,9,11]]},"assertion":[{"value":"2022-12-10","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-06-19","order":2,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2024-09-11","order":3,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}