{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T15:18:55Z","timestamp":1759331935933,"version":"3.41.0"},"reference-count":106,"publisher":"Association for Computing Machinery (ACM)","issue":"5","license":[{"start":{"date-parts":[[2023,9,26]],"date-time":"2023-09-26T00:00:00Z","timestamp":1695686400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2023,9,30]]},"abstract":"<jats:p>Dataflow process networks (DPNs) provide a convenient model of computation that is often used to model system behavior in model-based designs. With fixed sets of nodes, they are also used as dataflow graphs as an intermediate program representation by compilers to uncover instruction-level parallelism of sequential programs. Many recent processor architectures, which are still von Neumann architectures, also use dataflow computing to increase their exploitation of instruction-level parallelism by exposing their datapaths so that the compiler can take care of the allocation of processing units (PUs), the execution schedules of instructions on the PUs, and the communication of intermediate values between PUs. If the communication paths are buffered, these architectures can be abstracted into a DPN architecture whose PUs and interconnection network are DPN nodes.<\/jats:p>\n          <jats:p>In this article, we introduce a DPN abstraction of hybrid dataflow\/von Neumann architectures and consider the mapping of the nodes of a given dataflow graph to the PUs of such a DPN architecture such that there are no conflicts due to the mapping of different nodes to the same PU. We express the allocation and scheduling constraints in terms of propositional logic for the original dataflow graph and for a modified version of the dataflow graph that simplifies the constraints by introducing levels using copy nodes, such that all nodes receive inputs only from nodes of the previous level. We also formulate equisatisfiable SMT constraints using integer variables to reason directly about the parallel runtime. On this basis, we further present alternative SAT constraints that explicitly encode concurrency, and discuss variants of the constraints for a better understanding of the same.<\/jats:p>","DOI":"10.1145\/3607869","type":"journal-article","created":{"date-parts":[[2023,7,8]],"date-time":"2023-07-08T11:32:27Z","timestamp":1688815947000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Consistency Constraints for Mapping Dataflow Graphs to Hybrid Dataflow\/von Neumann Architectures"],"prefix":"10.1145","volume":"22","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1305-7132","authenticated-orcid":false,"given":"Klaus","family":"Schneider","sequence":"first","affiliation":[{"name":"RPTU Kaiserslautern-Landau, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7866-5983","authenticated-orcid":false,"given":"Anoop","family":"Bhagyanath","sequence":"additional","affiliation":[{"name":"RPTU Kaiserslautern-Landau, Germany"}]}],"member":"320","published-online":{"date-parts":[[2023,9,26]]},"reference":[{"issue":"2","key":"e_1_3_1_2_2","doi-asserted-by":"crossref","first-page":"15","DOI":"10.1109\/MC.1982.1653938","article-title":"Data flow languages","volume":"15","author":"Ackerman W.","year":"1982","unstructured":"W. Ackerman. 1982. Data flow languages. IEEE Computer 15, 2 (1982), 15\u201325.","journal-title":"IEEE Computer"},{"issue":"2","key":"e_1_3_1_3_2","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1109\/MC.1982.1653937","article-title":"Data flow systems","volume":"15","author":"Agerwala T.","year":"1982","unstructured":"T. Agerwala and K. P. Arvind. 1982. Data flow systems. IEEE Computer 15, 2 (1982), 10\u201313.","journal-title":"IEEE Computer"},{"key":"e_1_3_1_4_2","first-page":"302","volume-title":"Proceedings of the Parallel and Distributed Processing Techniques and Applications","author":"Anapalli S. R.","year":"2009","unstructured":"S. R. Anapalli, K. C. Chakilam, and T. W. O\u2019Neil. 2009. Static scheduling for cyclo-static data flow graphs. In Proceedings of the Parallel and Distributed Processing Techniques and Applications. H. R. Arabnia (Ed.), CSREA Press, Las Vegas, Nevada, 302\u2013306."},{"key":"e_1_3_1_5_2","first-page":"115","volume-title":"Proceedings of the Application of Concurrency to System Design.","author":"Anders M.","year":"2018","unstructured":"M. Anders, A. Bhagyanath, and K. Schneider. 2018. On memory optimal code generation for exposed datapath architectures with buffered processing units. In Proceedings of the Application of Concurrency to System Design.T. Chatain and R. Grosu (Eds.), IEEE Computer Society, Bratislava, Slovakia, 115\u2013124."},{"key":"e_1_3_1_6_2","first-page":"541","volume-title":"Proceedings of the Conference on CONPAR 88","year":"1988","unstructured":"Arvind, D. E. Culler, and K. Ekanadham. 1988. The price of asynchronous parallelism: An analysis of dataflow architectures. In Proceedings of the Conference on CONPAR 88. British Computer Society, Manchester, England, UK, 541\u2013555."},{"issue":"3","key":"e_1_3_1_7_2","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1177\/109434208800200303","article-title":"Assessing the benefits of fine-grain parallelism in dataflow programs","volume":"2","year":"1988","unstructured":"Arvind, D. E. Culler, and G. K. Maa. 1988. Assessing the benefits of fine-grain parallelism in dataflow programs. International Journal of Supercomuter Applications 2, 3 (1988), 10\u201336.","journal-title":"International Journal of Supercomuter Applications"},{"issue":"8","key":"e_1_3_1_8_2","doi-asserted-by":"crossref","first-page":"613","DOI":"10.1145\/359576.359579","article-title":"Can programming be liberated from the von neumann style?","volume":"21","author":"Backus J.","year":"1978","unstructured":"J. Backus. 1978. Can programming be liberated from the von neumann style? Communications of the ACM 21, 8 (1978), 613\u2013641.","journal-title":"Communications of the ACM"},{"key":"e_1_3_1_9_2","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4613-1389-2","volume-title":"Software Synthesis from Dataflow Graphs","author":"Battacharyya S. S.","year":"1996","unstructured":"S. S. Battacharyya, P. K. Murthy, and E. A. Lee. 1996. Software Synthesis from Dataflow Graphs. Kluwer Adacemic Publishers."},{"issue":"1","key":"e_1_3_1_10_2","doi-asserted-by":"crossref","first-page":"64","DOI":"10.1109\/JPROC.2002.805826","article-title":"The synchronous languages twelve years later","volume":"91","author":"Benveniste A.","year":"2003","unstructured":"A. Benveniste, P. Caspi, S. Edwards, N. Halbwachs, P. Le Guernic, and R. de Simone. 2003. The synchronous languages twelve years later. Proc. IEEE 91, 1 (2003), 64\u201383.","journal-title":"Proc. IEEE"},{"issue":"2","key":"e_1_3_1_11_2","doi-asserted-by":"crossref","first-page":"103","DOI":"10.1016\/0167-6423(91)90001-E","article-title":"Synchronous programming with events and relations: The SIGNAL language and its semantics","volume":"16","author":"Benveniste A.","year":"1991","unstructured":"A. Benveniste, P. Le Guernic, and C. Jacquemot. 1991. Synchronous programming with events and relations: The SIGNAL language and its semantics. Science of Computer Programming 16, 2 (1991), 103\u2013149.","journal-title":"Science of Computer Programming"},{"key":"e_1_3_1_12_2","volume-title":"Code Generation for Synchronous Control Asynchronous Dataflow Architectures","author":"Bhagyanath A.","year":"2020","unstructured":"A. Bhagyanath. 2020. Code Generation for Synchronous Control Asynchronous Dataflow Architectures. Ph. D. Dissertation. Department of Computer Science, University of Kaiserslautern, Germany. PhD."},{"key":"e_1_3_1_13_2","first-page":"77","volume-title":"Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen","author":"Bhagyanath A.","year":"2016","unstructured":"A. Bhagyanath, T. Jain, and K. Schneider. 2016. Towards code generation for the synchronous control asynchronous dataflow (SCAD) architectures. In Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen. R. Wimmer (Ed.), University of Freiburg, Freiburg, Germany, 77\u201388."},{"key":"e_1_3_1_14_2","first-page":"143","volume-title":"Proceedings of the Formal Methods and Models for Codesign","author":"Bhagyanath A.","year":"2016","unstructured":"A. Bhagyanath and K. Schneider. 2016. Optimal compilation for exposed datapath architectures with buffered processing units by SAT solvers. In Proceedings of the Formal Methods and Models for Codesign. E. Leonard and K. Schneider (Eds.), IEEE Computer Society, Kanpur, India, 143\u2013152."},{"key":"e_1_3_1_15_2","first-page":"1","volume-title":"Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation","author":"Bhagyanath A.","year":"2017","unstructured":"A. Bhagyanath and K. Schneider. 2017. Exploring different execution paradigms in exposed datapath architectures with buffered processing units. In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation. Y. N. Patt and S. K. Nandy (Eds.), IEEE Computer Society, Pythagorion, Greece, 1\u201310."},{"key":"e_1_3_1_16_2","first-page":"106","volume-title":"Proceedings of the Application of Concurrency to System Design","author":"Bhagyanath A.","year":"2017","unstructured":"A. Bhagyanath and K. Schneider. 2017. Exploring the potential of instruction-level parallelism of exposed datapath architectures with buffered processing units. In Proceedings of the Application of Concurrency to System Design. A. Legay and K. Schneider (Eds.), IEEE Computer Society, Zaragoza, Spain, 106\u2013115."},{"key":"e_1_3_1_17_2","first-page":"18","volume-title":"Proceedings of the International Symposium on Embedded Multicore\/Many-core Systems-on-Chip","author":"Bhagyanath A.","year":"2022","unstructured":"A. Bhagyanath and K. Schneider. 2022. Buffer allocation for exposed datapath architectures. In Proceedings of the International Symposium on Embedded Multicore\/Many-core Systems-on-Chip. IEEE Computer Society, Penang, Malaysia, 18\u201325."},{"key":"e_1_3_1_18_2","volume-title":"Proceedings of the Computer Architectures and Platforms at Computer Software and Applications Conference","author":"Bhagyanath A.","year":"2023","unstructured":"A. Bhagyanath and K. Schneider. 2023. Program balancing in compilation for buffered hybrid dataflow processors. In Proceedings of the Computer Architectures and Platforms at Computer Software and Applications Conference. IEEE Computer Society, Torino, Italy."},{"key":"e_1_3_1_19_2","doi-asserted-by":"crossref","first-page":"905","DOI":"10.1007\/978-1-4614-6859-2_28","volume-title":"Proceedings of the Handbook of Signal Processing Systems","author":"Bhattacharyya S. S.","year":"2013","unstructured":"S. S. Bhattacharyya, E. F. Deprettere, and B. D. Theelen. 2013. Dynamic dataflow graphs. In Proceedings of the Handbook of Signal Processing Systems. Springer, 905\u2013944."},{"issue":"2","key":"e_1_3_1_20_2","doi-asserted-by":"crossref","first-page":"397","DOI":"10.1109\/78.485935","article-title":"Cyclo-static dataflow","volume":"44","author":"Bilsen G.","year":"1996","unstructured":"G. Bilsen, M. Engels, R. Lauwereins, and J. Peperstraete. 1996. Cyclo-static dataflow. IEEE Transactions on Signal Processing 44, 2 (1996), 397\u2013408.","journal-title":"IEEE Transactions on Signal Processing"},{"issue":"6","key":"e_1_3_1_21_2","doi-asserted-by":"crossref","first-page":"26","DOI":"10.1109\/MSP.2009.934110","article-title":"A survey of multicore processors","volume":"26","author":"Blake G.","year":"2009","unstructured":"G. Blake, R. G. Dreslinski, and T. Mudge. 2009. A survey of multicore processors. IEEE Signal Processing Magazine 26, 6 (2009), 26\u201337.","journal-title":"IEEE Signal Processing Magazine"},{"key":"e_1_3_1_22_2","doi-asserted-by":"crossref","first-page":"69","DOI":"10.1016\/0304-3975(88)90019-9","article-title":"On the intersection of stacks and queues","volume":"58","author":"Brandenburg F. J.","year":"1988","unstructured":"F. J. Brandenburg. 1988. On the intersection of stacks and queues. Theoretical Computer Science 58 (1988), 69\u201380.","journal-title":"Theoretical Computer Science"},{"key":"e_1_3_1_23_2","volume-title":"Scheduling Dynamic Dataflow Graphs with Bounded Memory Using the Token Flow Model","author":"Buck J. T.","year":"1993","unstructured":"J. T. Buck. 1993. Scheduling Dynamic Dataflow Graphs with Bounded Memory Using the Token Flow Model. Ph. D. Dissertation. University of California, Berkeley, California. PhD."},{"key":"e_1_3_1_24_2","first-page":"508","volume-title":"Proceedings of the Asilomar Conference on Signals, Systems, and Computers","author":"Buck J. T.","year":"1994","unstructured":"J. T. Buck. 1994. Static scheduling and code generation from dynamic dataflow graphs with integer-valued control streams. In Proceedings of the Asilomar Conference on Signals, Systems, and Computers. IEEE Computer Society, Pacific Grove, CA, 508\u2013513."},{"key":"e_1_3_1_25_2","first-page":"267","volume-title":"Proceedings of the Advanced Topics in Dataflow Computing and Multithreading.","author":"Buck J.","year":"1995","unstructured":"J. Buck and E. A. Lee. 1995. The token flow model. In Proceedings of the Advanced Topics in Dataflow Computing and Multithreading.L. Bic, G. R. Gao, and J.-L. Gaudiot (Eds.), IEEE Computer Society, Hamilton Island, Queensland, Australia, 267\u2013290."},{"issue":"12","key":"e_1_3_1_26_2","doi-asserted-by":"crossref","first-page":"1515","DOI":"10.1109\/TC.1987.5009501","article-title":"Incorporating dataflow ideas into von neumann processors for parallel execution","volume":"36","author":"Buehrer R.","year":"1987","unstructured":"R. Buehrer and K. Ekanadham. 1987. Incorporating dataflow ideas into von neumann processors for parallel execution. IEEE Transactions on Computers (T-C) 36, 12 (1987), 1515\u20131522.","journal-title":"IEEE Transactions on Computers (T-C)"},{"issue":"7","key":"e_1_3_1_27_2","doi-asserted-by":"crossref","first-page":"44","DOI":"10.1109\/MC.2004.65","article-title":"Scaling to the end of silicon with EDGE architectures","volume":"37","author":"Burger D.","year":"2004","unstructured":"D. Burger, S. W. Keckler, K. S. McKinley, M. Dahlin, L. K. John, C. Lin, C. R. Moore, J. Burrill, R. G. McDonald, and W. Yoder. 2004. Scaling to the end of silicon with EDGE architectures. IEEE Computer 37, 7 (2004), 44\u201355.","journal-title":"IEEE Computer"},{"key":"e_1_3_1_28_2","first-page":"178","volume-title":"Proceedings of the Principles of Programming Languages","author":"Caspi P.","year":"1987","unstructured":"P. Caspi, N. Halbwachs, D. Pilaud, and J. A. Plaice. 1987. LUSTRE: A declarative language for programming synchronous systems. In Proceedings of the Principles of Programming Languages. ACM, Munich, Germany, 178\u2013188."},{"key":"e_1_3_1_29_2","doi-asserted-by":"crossref","first-page":"171","DOI":"10.1016\/0304-3975(91)90053-5","article-title":"QRT FIFO automata, breadth-first grammars and their relations","volume":"85","author":"Cherubini A.","year":"1991","unstructured":"A. Cherubini, C. Citrini, S. Crespi Reghizzi, and D. Mandrioli. 1991. QRT FIFO automata, breadth-first grammars and their relations. Theoretical Computer Science 85 (1991), 171\u2013203.","journal-title":"Theoretical Computer Science"},{"key":"e_1_3_1_30_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2699875","article-title":"Upward planarity testing in practice: SAT formulations and comparative study","volume":"20","author":"Chimani M.","year":"2015","unstructured":"M. Chimani and R. Zeranski. 2015. Upward planarity testing in practice: SAT formulations and comparative study. ACM Journal of Experimental Algorithmics 20 (2015), 1\u201327.","journal-title":"ACM Journal of Experimental Algorithmics"},{"key":"e_1_3_1_31_2","doi-asserted-by":"crossref","first-page":"130","DOI":"10.1109\/GLSV.1994.289981","volume-title":"Proceedings of the Great Lakes Symposium on VLSI","author":"Corporaal H.","year":"1994","unstructured":"H. Corporaal. 1994. Design of transport triggered architectures. In Proceedings of the Great Lakes Symposium on VLSI. IEEE Computer Society, Notre Dame, IN, 130\u2013135."},{"issue":"12","key":"e_1_3_1_32_2","doi-asserted-by":"crossref","first-page":"949","DOI":"10.1016\/S1383-7621(98)00046-0","article-title":"TTAs: Missing the ILP complexity wall","volume":"45","author":"Corporaal H.","year":"1999","unstructured":"H. Corporaal. 1999. TTAs: Missing the ILP complexity wall. Journal of Systems Architecture 45, 12\u201313 (1999), 949\u2013973.","journal-title":"Journal of Systems Architecture"},{"issue":"4","key":"e_1_3_1_33_2","doi-asserted-by":"crossref","first-page":"401","DOI":"10.1023\/A:1007511206083","article-title":"Computation in the context of transport triggered architectures","volume":"28","author":"Corporaal H.","year":"2000","unstructured":"H. Corporaal, J. Janssen, and M. Arnold. 2000. Computation in the context of transport triggered architectures. International Journal of Parallel Programming 28, 4 (2000), 401\u2013427.","journal-title":"International Journal of Parallel Programming"},{"issue":"1","key":"e_1_3_1_34_2","doi-asserted-by":"crossref","first-page":"438","DOI":"10.1017\/S1471068418000170","article-title":"Optimal scheduling for exposed datapath architectures with buffered processing units by ASP","volume":"18","author":"Dahlem M.","year":"2018","unstructured":"M. Dahlem, A. Bhagyanath, and K. Schneider. 2018. Optimal scheduling for exposed datapath architectures with buffered processing units by ASP. Theory and Practice of Logic Programming 18, 1 (2018), 438\u2013451.","journal-title":"Theory and Practice of Logic Programming"},{"key":"e_1_3_1_35_2","first-page":"210","volume-title":"Proceedings of the International Symposium on Computer Architecture","author":"Davis A. L.","year":"1978","unstructured":"A. L. Davis. 1978. The architecture and system method of DDM1: A recursively structured data driven machine. In Proceedings of the International Symposium on Computer Architecture. ACM, Palo Alto, CA, 210\u2013215."},{"key":"e_1_3_1_36_2","doi-asserted-by":"crossref","first-page":"362","DOI":"10.1007\/3-540-06859-7_145","volume-title":"Proceedings of the Programming Symposium.","author":"Dennis J. B.","year":"1974","unstructured":"J. B. Dennis. 1974. First version of a data-flow procedure language. In Proceedings of the Programming Symposium.B. Robinet (Ed.), LNCS, Vol. 19, Springer, Paris, France, 362\u2013376."},{"issue":"11","key":"e_1_3_1_37_2","doi-asserted-by":"crossref","first-page":"48","DOI":"10.1109\/MC.1980.1653418","article-title":"Data flow supercomputers","volume":"13","author":"Dennis J. B.","year":"1980","unstructured":"J. B. Dennis. 1980. Data flow supercomputers. IEEE Computer 13, 11 (1980), 48\u201356.","journal-title":"IEEE Computer"},{"key":"e_1_3_1_38_2","first-page":"126","volume-title":"Proceedings of the International Symposium on Computer Architecture","author":"Dennis J. B.","year":"1975","unstructured":"J. B. Dennis and D. P. Misunas. 1975. A preliminary architecture for a basic dataflow processor. In Proceedings of the International Symposium on Computer Architecture. W. K. King and O. Garcia (Eds.), ACM, Houston, TX, 126\u2013132."},{"key":"e_1_3_1_39_2","doi-asserted-by":"crossref","unstructured":"V. Dujmovi\u0107 D. Eppstein R. Hickingbotham P. Morin and D. R. Wood. 2022. Stack-number is not bounded by queue-number. Combinatorica 42 2 (2022) 151\u2013164.","DOI":"10.1007\/s00493-021-4585-7"},{"key":"e_1_3_1_40_2","first-page":"503","volume-title":"Proceedings of the Asilomar Conference on Signals, Systems and Computers","author":"Engels M.","year":"1994","unstructured":"M. Engels, G. Bilsen, R. Lauwereins, and J. Peperstraete. 1994. Cyclo-static dataflow: Model and implementation. In Proceedings of the Asilomar Conference on Signals, Systems and Computers. IEEE Computer Society, Pacific Grove, California, 503\u2013507."},{"key":"e_1_3_1_41_2","first-page":"3255","volume-title":"Proceedings of the International Conference on Acoustics, Speech and Signal Processing","author":"Engels M.","year":"1995","unstructured":"M. Engels, G. Bilsen, R. Lauwereins, and J. Peperstraete. 1995. Cyclo-static dataflow. In Proceedings of the International Conference on Acoustics, Speech and Signal Processing. IEEE Computer Society, Detroit, Michigan, 3255\u20133258."},{"issue":"2","key":"e_1_3_1_42_2","doi-asserted-by":"crossref","first-page":"58","DOI":"10.1109\/MC.1982.1653942","article-title":"A second opinion of data flow machines and languages","volume":"15","author":"Gajski D. D.","year":"1982","unstructured":"D. D. Gajski, D. A. Padua, D. J. Kuck, and R. H. Kuhn. 1982. A second opinion of data flow machines and languages. IEEE Computer 15, 2 (1982), 58\u201369.","journal-title":"IEEE Computer"},{"key":"e_1_3_1_43_2","doi-asserted-by":"crossref","first-page":"109","DOI":"10.1007\/BF01108622","article-title":"Upward planarity testing","volume":"12","author":"Garg A.","year":"1995","unstructured":"A. Garg and R. Tamassia. 1995. Upward planarity testing. Order 12 (1995), 109\u2013133.","journal-title":"Order"},{"issue":"2","key":"e_1_3_1_44_2","doi-asserted-by":"crossref","first-page":"163","DOI":"10.1007\/s11227-005-0290-3","article-title":"The AMIDAR class of reconfigurable processors","volume":"32","author":"Gatzka S.","year":"2005","unstructured":"S. Gatzka and C. Hochberger. 2005. The AMIDAR class of reconfigurable processors. The Journal of Supercomputing 32, 2 (2005), 163\u2013181.","journal-title":"The Journal of Supercomputing"},{"key":"e_1_3_1_45_2","doi-asserted-by":"crossref","first-page":"257","DOI":"10.1007\/3-540-18317-5_15","volume-title":"Proceedings of the Functional Programming Languages and Computer Architecture","volume":"274","author":"Gautier T.","year":"1987","unstructured":"T. Gautier, P. Le Guernic, and L. Besnard. 1987. SIGNAL, a declarative language for synchronous programming of real-time systems. In Proceedings of the Functional Programming Languages and Computer Architecture, G. Kahn (Ed.), LNCS, Vol. 274, Springer, Portland, Oregon, 257\u2013277."},{"issue":"5","key":"e_1_3_1_46_2","doi-asserted-by":"crossref","first-page":"38","DOI":"10.1109\/MM.2012.51","article-title":"DySER: Unifying functionality and parallelism specialization for energy-efficient computing","volume":"33","author":"Govindaraju V.","year":"2012","unstructured":"V. Govindaraju, C.-H. Ho, T. Nowatzki, J. Chhugani, N. Satish, K. Sankaralingam, and C. Kim. 2012. DySER: Unifying functionality and parallelism specialization for energy-efficient computing. IEEE Micro 33, 5 (2012), 38\u201351.","journal-title":"IEEE Micro"},{"issue":"3","key":"e_1_3_1_47_2","doi-asserted-by":"crossref","first-page":"36","DOI":"10.1145\/74926.74930","article-title":"The epsilon dataflow processor","volume":"17","author":"Grafe V. G.","year":"1989","unstructured":"V. G. Grafe, G. S. Davidson, J. E. Hoch, and V. P. Holmes. 1989. The epsilon dataflow processor. ACM SIGARCH Computer Architecture News 17, 3 (1989), 36\u201345.","journal-title":"ACM SIGARCH Computer Architecture News"},{"issue":"1","key":"e_1_3_1_48_2","doi-asserted-by":"crossref","first-page":"34","DOI":"10.1145\/2465.2468","article-title":"The manchester prototype dataflow computer","volume":"28","author":"Gurd J. R.","year":"1985","unstructured":"J. R. Gurd, C. C. Kirkham, and I. Watson. 1985. The manchester prototype dataflow computer. Communications of the ACM 28, 1 (1985), 34\u201352.","journal-title":"Communications of the ACM"},{"issue":"9","key":"e_1_3_1_49_2","doi-asserted-by":"crossref","first-page":"1305","DOI":"10.1109\/5.97300","article-title":"The synchronous dataflow programming language LUSTRE","volume":"79","author":"Halbwachs N.","year":"1991","unstructured":"N. Halbwachs, P. Caspi, P. Raymond, and D. Pilaud. 1991. The synchronous dataflow programming language LUSTRE. Proc. IEEE 79, 9 (1991), 1305\u20131320.","journal-title":"Proc. IEEE"},{"issue":"3","key":"e_1_3_1_50_2","doi-asserted-by":"crossref","first-page":"398","DOI":"10.1137\/0405031","article-title":"Comparing queues and stacks as mechanisms for laying out graphs","volume":"5","author":"Heath L. S.","year":"1992","unstructured":"L. S. Heath, F. T Leighton, and A. L. Rosenberg. 1992. Comparing queues and stacks as mechanisms for laying out graphs. SIAM Journal on Discrete Mathematics 5, 3 (1992), 398\u2013412.","journal-title":"SIAM Journal on Discrete Mathematics"},{"key":"e_1_3_1_51_2","doi-asserted-by":"crossref","first-page":"300","DOI":"10.1007\/BFb0021813","volume-title":"Proceedings of the Graph Drawing.","author":"Heath L. S.","year":"1996","unstructured":"L. S. Heath and S. V. Pemmaraju. 1996. Recognizing leveled-planar DAGs in linear time. In Proceedings of the Graph Drawing.F. J. Brandenburg (Ed.), LNCS, Vol. 1027, Springer, Passau, Germany, 300\u2013311."},{"issue":"4","key":"e_1_3_1_52_2","first-page":"599","article-title":"Stack and queue layouts of posets","volume":"10","author":"Heath L. S.","year":"1997","unstructured":"L. S. Heath and S. V. Pemmaraju. 1997. Stack and queue layouts of posets. SIAM Journal on Computing 10, 4 (1997), 599\u2013625.","journal-title":"SIAM Journal on Computing"},{"issue":"5","key":"e_1_3_1_53_2","doi-asserted-by":"crossref","first-page":"1588","DOI":"10.1137\/S0097539795291550","article-title":"Stack and queue layouts of directed acyclic graphs: Part II","volume":"28","author":"Heath L. S.","year":"1999","unstructured":"L. S. Heath and S. V. Pemmaraju. 1999. Stack and queue layouts of directed acyclic graphs: Part II. SIAM Journal on Computing 28, 5 (1999), 1588\u20131626.","journal-title":"SIAM Journal on Computing"},{"issue":"4","key":"e_1_3_1_54_2","doi-asserted-by":"crossref","first-page":"1510","DOI":"10.1137\/S0097539795280287","article-title":"Stack and queue layouts of directed acyclic graphs: Part I","volume":"28","author":"Heath L. S.","year":"1999","unstructured":"L. S. Heath, S. V. Pemmaraju, and A. N. Trenk. 1999. Stack and queue layouts of directed acyclic graphs: Part I. SIAM Journal on Computing 28, 4 (1999), 1510\u20131539.","journal-title":"SIAM Journal on Computing"},{"issue":"5","key":"e_1_3_1_55_2","doi-asserted-by":"crossref","first-page":"927","DOI":"10.1137\/0221055","article-title":"Comparing queues and stacks as machines for laying out graphs","volume":"21","author":"Heath L. S.","year":"1992","unstructured":"L. S. Heath and A. L. Rosenberg. 1992. Comparing queues and stacks as machines for laying out graphs. SIAM Journal on Computing 21, 5 (1992), 927\u2013958.","journal-title":"SIAM Journal on Computing"},{"issue":"12","key":"e_1_3_1_56_2","doi-asserted-by":"crossref","first-page":"1805","DOI":"10.1109\/32.9065","article-title":"Dataflow computing models, languages, and machines for intelligence computations","volume":"14","author":"Herath Y.","year":"1988","unstructured":"Y. Herath, Y. Yamaguchi, N. Saito, and T. Yuba. 1988. Dataflow computing models, languages, and machines for intelligence computations. IEEE Transactions on Software Engineering 14, 12 (1988), 1805\u20131828.","journal-title":"IEEE Transactions on Software Engineering"},{"key":"e_1_3_1_57_2","doi-asserted-by":"crossref","first-page":"435","DOI":"10.1007\/3-540-57877-3_29","volume-title":"Proceedings of the Compiler Construction.","author":"Hoogerbrugge J.","year":"1994","unstructured":"J. Hoogerbrugge and H. Corporaal. 1994. Transport-triggering vs. operation-triggering. In Proceedings of the Compiler Construction. P. Fritzson (Ed.), LNCS, Vol. 786, Springer, Edinburgh, UK, 435\u2013449."},{"key":"e_1_3_1_58_2","first-page":"131","volume-title":"Proceedings of the International Symposium on Computer Architecture.","author":"Iannucci R. A.","year":"1988","unstructured":"R. A. Iannucci. 1988. Towards a dataflow\/von neumann hybrid architecture. In Proceedings of the International Symposium on Computer Architecture.H. Siegel (Ed.), IEEE Computer Society, Honolulu, Hawaii, 131\u2013140."},{"issue":"1","key":"e_1_3_1_59_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1013208.1013209","article-title":"Advances in dataflow programming languages","volume":"36","author":"Johnston W. M.","year":"2004","unstructured":"W. M. Johnston, J. R. P. Hanna, and R. J. Millar. 2004. Advances in dataflow programming languages. ACM Computing Surveys 36, 1 (2004), 1\u201334.","journal-title":"ACM Computing Surveys"},{"key":"e_1_3_1_60_2","first-page":"83","volume-title":"Proceedings of the International Parallel and Distributed Processing Symposium Workshops","author":"J\u00e4\u00e4skel\u00e4inen P.","year":"2018","unstructured":"P. J\u00e4\u00e4skel\u00e4inen, A. Tervo, G. P. Vay\u00e1, T. Viitanen, N. Behmann, and H. Blume. 2018. Transport-triggered soft cores. In Proceedings of the International Parallel and Distributed Processing Symposium Workshops. IEEE Computer Society, Vancouver, BC, Canada, 83\u201390."},{"key":"e_1_3_1_61_2","doi-asserted-by":"crossref","first-page":"224","DOI":"10.1007\/3-540-37623-2_17","volume-title":"Proceedings of the Graph Drawing.","author":"J\u00fcnger M.","year":"1998","unstructured":"M. J\u00fcnger, S. Leipert, and P. Mutzel. 1998. Level planarity testing in linear time. In Proceedings of the Graph Drawing.S. H. Whitesides (Ed.), LNCS, Vol. 1547, Springer, Montr\u00e9al, Canada, 224\u2013237."},{"key":"e_1_3_1_62_2","first-page":"471","volume-title":"Proceedings of the Information Processing.","author":"Kahn G.","year":"1974","unstructured":"G. Kahn. 1974. The semantics of a simple language for parallel programming. In Proceedings of the Information Processing.J. L. Rosenfeld (Ed.), North-Holland, Stockholm, Sweden, 471\u2013475."},{"key":"e_1_3_1_63_2","first-page":"993","volume-title":"Proceedings of the Information Processing.","author":"Kahn G.","year":"1977","unstructured":"G. Kahn and D. B. MacQueen. 1977. Coroutines and networks of parallel processes. In Proceedings of the Information Processing.B. Gilchrist (Ed.), North-Holland, Toronto, Canada, 993\u2013998."},{"issue":"6","key":"e_1_3_1_64_2","doi-asserted-by":"crossref","first-page":"1390","DOI":"10.1137\/0114108","article-title":"Properties of a model for parallel computations: Determinacy, termination, queueing","volume":"14","author":"Karp R. M.","year":"1966","unstructured":"R. M. Karp and R. E. Miller. 1966. Properties of a model for parallel computations: Determinacy, termination, queueing. SIAM Journal on Applied Mathematics 14, 6 (1966), 1390\u20131411.","journal-title":"SIAM Journal on Applied Mathematics"},{"issue":"9","key":"e_1_3_1_65_2","doi-asserted-by":"crossref","first-page":"1321","DOI":"10.1109\/5.97301","article-title":"Programming real-time applications with SIGNAL","volume":"79","author":"Guernic P. Le","year":"1991","unstructured":"P. Le Guernic, T. Gauthier, M. Le Borgne, and C. Le Maire. 1991. Programming real-time applications with SIGNAL. Proc. IEEE 79, 9 (1991), 1321\u20131336.","journal-title":"Proc. IEEE"},{"issue":"2","key":"e_1_3_1_66_2","doi-asserted-by":"crossref","first-page":"223","DOI":"10.1109\/71.89067","article-title":"Consistency in dataflow graphs","volume":"2","author":"Lee E. A.","year":"1991","unstructured":"E. A. Lee. 1991. Consistency in dataflow graphs. IEEE Transactions on Parallel and Distributed Systems 2, 2 (1991), 223\u2013235.","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"issue":"1","key":"e_1_3_1_67_2","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1109\/TC.1987.5009446","article-title":"Static scheduling of synchronous data flow programs for digital signal processing","volume":"36","author":"Lee E. A.","year":"1987","unstructured":"E. A. Lee and D. G. Messerschmitt. 1987. Static scheduling of synchronous data flow programs for digital signal processing. IEEE Transactions on Computers (T-C) 36, 1 (1987), 24\u201335.","journal-title":"IEEE Transactions on Computers (T-C)"},{"issue":"9","key":"e_1_3_1_68_2","doi-asserted-by":"crossref","first-page":"1235","DOI":"10.1109\/PROC.1987.13876","article-title":"Synchronous data flow","volume":"75","author":"Lee E. A.","year":"1987","unstructured":"E. A. Lee and D. G. Messerschmitt. 1987. Synchronous data flow. Proc. IEEE 75, 9 (1987), 1235\u20131245.","journal-title":"Proc. IEEE"},{"issue":"5","key":"e_1_3_1_69_2","doi-asserted-by":"crossref","first-page":"773","DOI":"10.1109\/5.381846","article-title":"Dataflow process networks","volume":"83","author":"Lee E. A.","year":"1995","unstructured":"E. A. Lee and T. Parks. 1995. Dataflow process networks. Proc. IEEE 83, 5 (1995), 773\u2013801.","journal-title":"Proc. IEEE"},{"issue":"1","key":"e_1_3_1_70_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1016\/0304-3975(77)90053-6","article-title":"Fully abstract models of typed  \\(\\lambda\\) -calculi","volume":"4","author":"Milner R.","year":"1977","unstructured":"R. Milner. 1977. Fully abstract models of typed \\(\\lambda\\) -calculi. Theoretical Computer Science 4, 1 (1977), 1\u201322.","journal-title":"Theoretical Computer Science"},{"key":"e_1_3_1_71_2","volume-title":"Dataflow Supercomputing Essentials \u2013 Algorithms, Applications and Implementations","author":"Milutinovic V.","year":"2017","unstructured":"V. Milutinovic, M. Kotlar, M. Stojanovic, I. Dundic, N. Trifunovic, and Z. Babovic. 2017. Dataflow Supercomputing Essentials \u2013 Algorithms, Applications and Implementations. Springer."},{"key":"e_1_3_1_72_2","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-319-16229-4","volume-title":"Guide to Dataflow Supercomputing \u2013 Basic Concepts, Case Studies, and a Detailed Example","author":"Milutinovic V.","year":"2015","unstructured":"V. Milutinovic, J. Salom, N. Trifunovic, and R. Giorgi. 2015. Guide to Dataflow Supercomputing \u2013 Basic Concepts, Case Studies, and a Detailed Example. Springer."},{"key":"e_1_3_1_73_2","first-page":"262","volume-title":"Proceedings of the International Symposium on Computer Architecture","author":"Nikhil R. S.","year":"1989","unstructured":"R. S. Nikhil. 1989. Can dataflow subsume von neumann computing?. In Proceedings of the International Symposium on Computer Architecture. IEEE Computer Society, Jerusalem, Israel, 262\u2013272."},{"key":"e_1_3_1_74_2","first-page":"82","volume-title":"Proceedings of the International Symposium on Computer Architecture","author":"Papadopoulos G.","year":"1990","unstructured":"G. Papadopoulos and D. Culler. 1990. Monsoon: An explicit token-store architecture. In Proceedings of the International Symposium on Computer Architecture. J.-L. Baer and L. Snyder (Eds.), IEEE Computer Society, Seattle, Washington, 82\u201391."},{"key":"e_1_3_1_75_2","volume-title":"Exploring the Powers of Stacks and Queues Via Graph Layouts","author":"Pemmaraju S. V.","year":"1992","unstructured":"S. V. Pemmaraju. 1992. Exploring the Powers of Stacks and Queues Via Graph Layouts. Ph. D. Dissertation. Virigina Polytechnic Institute and State University, Blacksburg, VA. PhD."},{"issue":"3","key":"e_1_3_1_76_2","doi-asserted-by":"crossref","first-page":"223","DOI":"10.1016\/0304-3975(77)90044-5","article-title":"LCF considered as a programming language","volume":"5","author":"Plotkin G. D.","year":"1977","unstructured":"G. D. Plotkin. 1977. LCF considered as a programming language. Theoretical Computer Science 5, 3 (1977), 223\u2013255.","journal-title":"Theoretical Computer Science"},{"key":"e_1_3_1_77_2","first-page":"128","volume-title":"Proceedings of the International Symposium on Computer Architecture","author":"Rixner S.","year":"2000","unstructured":"S. Rixner, W. J. Dally, U. J. Kapasi, P. R. Mattson, and J. D. Owens. 2000. Memory access scheduling. In Proceedings of the International Symposium on Computer Architecture. ACM, Vancouver, British Columbia, Canada, 128\u2013138."},{"key":"e_1_3_1_78_2","first-page":"1","volume-title":"Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen.","author":"Roob J.","year":"2023","unstructured":"J. Roob, A. Bhagyanath, and K. Schneider. 2023. Towards buffers as a scalable alternative to registers for processor-local memory. In Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen.VDE, Freiburg, Germany, 1\u201312."},{"issue":"2","key":"e_1_3_1_79_2","doi-asserted-by":"crossref","first-page":"138","DOI":"10.1109\/TC.1977.5009292","article-title":"A data flow multiprocessor","volume":"26","author":"Rumbaugh J.","year":"1977","unstructured":"J. Rumbaugh. 1977. A data flow multiprocessor. IEEE Transactions on Computers (T-C) 26, 2 (1977), 138\u2013146.","journal-title":"IEEE Transactions on Computers (T-C)"},{"issue":"1","key":"e_1_3_1_80_2","doi-asserted-by":"crossref","first-page":"62","DOI":"10.1145\/980152.980156","article-title":"TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP","volume":"1","author":"Sankaralingam K.","year":"2004","unstructured":"K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, N. Ranganathan, D. Burger, S. W. Keckler, R. G. Mcdonald, and C. R. Moore. 2004. TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP. ACM Transactions on Architecture and Code Optimization 1, 1 (2004), 62\u201393.","journal-title":"ACM Transactions on Architecture and Code Optimization"},{"key":"e_1_3_1_81_2","doi-asserted-by":"crossref","first-page":"312","DOI":"10.1007\/BFb0029534","volume-title":"Proceedings of the Lambda-Calculus and Computer Science Theory.","author":"Sazonov V. Y.","year":"1975","unstructured":"V. Y. Sazonov. 1975. Sequentially and parallely computable functionals. In Proceedings of the Lambda-Calculus and Computer Science Theory.C. B\u00f6hm (Ed.), LNCS, Vol. 37, Springer, Rome, Italy, 312\u2013318."},{"key":"e_1_3_1_82_2","first-page":"517","volume-title":"Proceedings of the Mathematical Foundations of Computer Science","author":"Sazonov V. Y.","year":"1976","unstructured":"V. Y. Sazonov. 1976. Degrees of parallelism in computations. In Proceedings of the Mathematical Foundations of Computer ScienceA. Mazurkiewicz (Ed.), LNCS, Vol. 45, Springer, Gdansk, Poland, 517\u2013523."},{"key":"e_1_3_1_83_2","doi-asserted-by":"crossref","first-page":"192","DOI":"10.1007\/BF01876321","article-title":"Expressibility of functions in D. Scott\u2019s LCF language","volume":"15","author":"Sazonov V. Y.","year":"1976","unstructured":"V. Y. Sazonov. 1976. Expressibility of functions in D. Scott\u2019s LCF language. Algebra and Logic 15 (1976), 192\u2013206.","journal-title":"Algebra and Logic"},{"key":"e_1_3_1_84_2","first-page":"66","volume-title":"Proceedings of the Formal Methods and Models for Codesign.","author":"Schneider K.","year":"2021","unstructured":"K. Schneider. 2021. Translating structured sequential programs to dataflow graphs. In Proceedings of the Formal Methods and Models for Codesign.I. Saha and L. Zhang (Eds.), ACM, Beijing, China, 66\u201377."},{"key":"e_1_3_1_85_2","first-page":"133","volume-title":"Proceedings of the Languages, Compilers, and Tools for Embedded Systems.","author":"Schneider K.","year":"2022","unstructured":"K. Schneider, A. Bhagyanath, and J. Roob. 2022. Code generation criteria for buffered exposed datapath architectures from dataflow graphs. In Proceedings of the Languages, Compilers, and Tools for Embedded Systems.T. Grosser and K. Lee (Eds.), ACM, San Diego, CA, 133\u2013145. 10.1145\/3519941.3535076"},{"key":"e_1_3_1_86_2","first-page":"45","volume-title":"Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen.","author":"Schneider K.","year":"2022","unstructured":"K. Schneider, A. Bhagyanath, and J. Roob. 2022. Virtual buffers for exposed datapath architectures. In Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen.J. Brandt (Ed.), VDE, Virtual Event, 45\u201355."},{"key":"e_1_3_1_87_2","volume-title":"Data Flow Computing \u2013 Theory and Practice","author":"Sharp J. A.","year":"1992","unstructured":"J. A. Sharp (Ed.). 1992. Data Flow Computing \u2013 Theory and Practice. Ablex Publishing."},{"key":"e_1_3_1_88_2","volume-title":"The WaveScalar Architecture","author":"Swanson S.","year":"2006","unstructured":"S. Swanson. 2006. The WaveScalar Architecture. Ph. D. Dissertation. University of Washington. PhD."},{"key":"e_1_3_1_89_2","first-page":"291","volume-title":"Proceedings of the Microarchitecture.","author":"Swanson S.","year":"2003","unstructured":"S. Swanson, K. Michelson, A. Schwerin, and M. Oskin. 2003. WaveScalar. In Proceedings of the Microarchitecture.IEEE Computer Society, San Diego, California, 291\u2013302."},{"issue":"2","key":"e_1_3_1_90_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1233307.1233308","article-title":"The WaveScalar architecture","volume":"25","author":"Swanson S.","year":"2007","unstructured":"S. Swanson, A. Schwerin, M. Mercaldi, A. Petersen, A. Putnam, K. Michelson, M. Oskin, and S. J. Eggers. 2007. The WaveScalar architecture. ACM Transactions on Computer Systems 25, 2 (2007), 1\u201354.","journal-title":"ACM Transactions on Computer Systems"},{"key":"e_1_3_1_91_2","doi-asserted-by":"crossref","first-page":"386","DOI":"10.4064\/fm-16-1-386-389","article-title":"Sur l\u2019extension de l\u2019ordre partiel","volume":"16","author":"Szpilrajn E.","year":"1930","unstructured":"E. Szpilrajn. 1930. Sur l\u2019extension de l\u2019ordre partiel. Fundamenta Mathematicae 16 (1930), 386\u2013389.","journal-title":"Fundamenta Mathematicae"},{"key":"e_1_3_1_92_2","volume-title":"Design Decisions in the Implementation of a RAW Architecture Workstation","author":"Taylor M. B.","year":"1999","unstructured":"M. B. Taylor. 1999. Design Decisions in the Implementation of a RAW Architecture Workstation. Master\u2019s thesis. Department of Electrical Engineering and Computer Science, MIT, Cambridge, MA. Master."},{"issue":"2","key":"e_1_3_1_93_2","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1109\/MM.2002.997877","article-title":"The RAW microprocessor: A computational fabric for software circuits and general-purpose programs","volume":"22","author":"Taylor M. B.","year":"2002","unstructured":"M. B. Taylor, J. S. Kim, J. E. Miller, D. Wentzlaff, F. Ghodrat, B. Greenwald, H. Hoffmann, P. Johnson, J. W. Lee, W. Lee, A. Ma, A. Saraf, M. Seneski, N. Shnidman, V. Strumpen, M. I. Frank, S. P. Amarasinghe, and A. Agarwal. 2002. The RAW microprocessor: A computational fabric for software circuits and general-purpose programs. IEEE Micro 22, 2 (2002), 25\u201335.","journal-title":"IEEE Micro"},{"key":"e_1_3_1_94_2","first-page":"411","volume-title":"Mathematical Foundations of Computer Science.","author":"Trakhtenbrot M. B.","year":"1975","unstructured":"M. B. Trakhtenbrot. 1975. On representation of sequential and parallel functions. In Mathematical Foundations of Computer Science.J. Be\u010dv\u00e1\u0159 (Ed.), LNCS, Vol. 32, Springer, Mari\u00e1nsk\u00e9 L\u00e1zn\u011b, Poland, 411\u2013417."},{"key":"e_1_3_1_95_2","first-page":"137","volume-title":"Proceedings of the Mathematical Foundations of Computer Science.","author":"Trakhtenbrot M. B.","year":"1976","unstructured":"M. B. Trakhtenbrot. 1976. Recursive program schemes and computable functionals. In Proceedings of the Mathematical Foundations of Computer Science.A. Mazurkiewicz (Ed.), LNCS, Vol. 45, Springer, Gdansk, Poland, 137\u2013152."},{"issue":"2","key":"e_1_3_1_96_2","doi-asserted-by":"crossref","first-page":"225","DOI":"10.1016\/0304-3975(76)90034-7","article-title":"Relationships between classes of monotonic functions","volume":"2","author":"Trakhtenbrot M. B.","year":"1976","unstructured":"M. B. Trakhtenbrot. 1976. Relationships between classes of monotonic functions. Theoretical Computer Science 2, 2 (1976), 225\u2013247.","journal-title":"Theoretical Computer Science"},{"key":"e_1_3_1_97_2","first-page":"150","volume-title":"Proceedings of the International Conference on Computer Design","author":"Traub K. R.","year":"1991","unstructured":"K. R. Traub, G. M. Papadopoulos, M. J. Beckerle, J. E. Hicks, and J. Young. 1991. Overview of the monsoon project. In Proceedings of the International Conference on Computer Design. IEEE Computer Society, Cambridge, Massachusetts, 150\u2013155."},{"key":"e_1_3_1_98_2","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-322-94688-1","volume-title":"Datenflu\u00dfrechner","author":"Ungerer T.","year":"1993","unstructured":"T. Ungerer. 1993. Datenflu\u00dfrechner. Teubner."},{"issue":"4","key":"e_1_3_1_99_2","doi-asserted-by":"crossref","first-page":"365","DOI":"10.1145\/27633.28055","article-title":"Dataflow machine architecture","volume":"18","author":"Veen A. H.","year":"1986","unstructured":"A. H. Veen. 1986. Dataflow machine architecture. ACM Computing Surveys 18, 4 (1986), 365\u2013396.","journal-title":"ACM Computing Surveys"},{"issue":"1","key":"e_1_3_1_100_2","doi-asserted-by":"crossref","first-page":"57","DOI":"10.1007\/BF02234250","article-title":"\u00dcber einen automaten mit pufferspeicherung","volume":"5","author":"Vollmar R.","year":"1970","unstructured":"R. Vollmar. 1970. \u00dcber einen automaten mit pufferspeicherung. Computing 5, 1 (1970), 57\u201370.","journal-title":"Computing"},{"key":"e_1_3_1_101_2","doi-asserted-by":"crossref","DOI":"10.5479\/sil.538961.39088011475779","volume-title":"First Draft of a Report on the EDVAC","author":"Neumann J. von","year":"1945","unstructured":"J. von Neumann. 1945. First Draft of a Report on the EDVAC. Technical Report. Moore School of Electrical Engineering, University of Pennsylvania."},{"issue":"4","key":"e_1_3_1_102_2","doi-asserted-by":"crossref","first-page":"27","DOI":"10.1109\/85.238389","article-title":"First draft of a report on the EDVAC","volume":"15","author":"Neumann J. von","year":"1993","unstructured":"J. von Neumann. 1993. First draft of a report on the EDVAC. IEEE Annals of the History of Computing 15, 4 (1993), 27\u201375.","journal-title":"IEEE Annals of the History of Computing"},{"issue":"9","key":"e_1_3_1_103_2","doi-asserted-by":"crossref","first-page":"86","DOI":"10.1109\/2.612254","article-title":"Baring it all to software: RAW machines","volume":"30","author":"Waingold E.","year":"1997","unstructured":"E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, J. Babb, S. Amarasinghe, and A. Agarwal. 1997. Baring it all to software: RAW machines. IEEE Computer 30, 9 (1997), 86\u201393.","journal-title":"IEEE Computer"},{"issue":"2","key":"e_1_3_1_104_2","doi-asserted-by":"crossref","first-page":"51","DOI":"10.1109\/MC.1982.1653941","article-title":"A practical data flow computer","volume":"15","author":"Watson I.","year":"1982","unstructured":"I. Watson and J. R. Gurd. 1982. A practical data flow computer. IEEE Computer 15, 2 (1982), 51\u201357.","journal-title":"IEEE Computer"},{"issue":"6","key":"e_1_3_1_105_2","doi-asserted-by":"crossref","first-page":"1489","DOI":"10.1109\/TPDS.2013.125","article-title":"Hybrid dataflow\/von-neumann architectures","volume":"25","author":"Yazdanpanah F.","year":"2014","unstructured":"F. Yazdanpanah, C. Alvarez-Martinez, D. Jimenez-Gonzalez, and Y. Etsion. 2014. Hybrid dataflow\/von-neumann architectures. IEEE Transactions on Parallel and Distributed Systems 25, 6 (2014), 1489\u20131509.","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"key":"e_1_3_1_106_2","first-page":"578","volume-title":"Proceedings of the Fall Joint Computer Conference on Exploring Technology: Today and Tomorrow","author":"Yuba T.","year":"1987","unstructured":"T. Yuba, K. Hiraki, T. Shimada, S. Sekiguchi, and K. Nishida. 1987. The SIGMA-1 dataflow computer. In Proceedings of the Fall Joint Computer Conference on Exploring Technology: Today and Tomorrow. S. A. Szygenda (Ed.), ACM, Chicago, IL, 578\u2013585."},{"key":"e_1_3_1_107_2","first-page":"305","volume-title":"Proceedings of the International Symposium on Low Power Electronics and Design","author":"Zyuban V.","year":"1998","unstructured":"V. Zyuban and P. Kogge. 1998. The energy complexity of register files. In Proceedings of the International Symposium on Low Power Electronics and Design. IEEE Computer Society, Monterey, CA, 305\u2013310."}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3607869","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3607869","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T16:37:06Z","timestamp":1750178226000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3607869"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,9,26]]},"references-count":106,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2023,9,30]]}},"alternative-id":["10.1145\/3607869"],"URL":"https:\/\/doi.org\/10.1145\/3607869","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2023,9,26]]},"assertion":[{"value":"2022-10-26","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-07-03","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-09-26","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}