{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:09:20Z","timestamp":1750219760222,"version":"3.41.0"},"reference-count":46,"publisher":"Association for Computing Machinery (ACM)","issue":"3","license":[{"start":{"date-parts":[[2024,5,13]],"date-time":"2024-05-13T00:00:00Z","timestamp":1715558400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"crossref","award":["HR00112190099"],"award-info":[{"award-number":["HR00112190099"]}],"id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/100000005","name":"Department of Defense","doi-asserted-by":"crossref","award":["FA8702-15-D-0002"],"award-info":[{"award-number":["FA8702-15-D-0002"]}],"id":[{"id":"10.13039\/100000005","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/100019827","name":"Meta Platforms Inc","doi-asserted-by":"crossref","id":[{"id":"10.13039\/100019827","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":["ACM Trans. Embed. Comput. Syst."],"published-print":{"date-parts":[[2024,5,31]]},"abstract":"<jats:p>Interest in deploying deep neural network (DNN) inference on edge devices has resulted in an explosion of the number and types of hardware platforms that machine learning (ML) libraries must support. High-level programming interfaces, such as TensorFlow, can be readily ported across different devices; however, maintaining performance when porting the low-level implementation is more nuanced. High-performance inference implementations require an effective mapping of the high-level interface to the target hardware platform. Commonly, this mapping may use optimizing compilers to generate code at compile time or high-performance vendor libraries that have been specialized to the target platform. Both approaches rely on expert knowledge across levels to produce an efficient mapping. This makes supporting new architectures difficult and time-consuming.<\/jats:p>\n          <jats:p>\n            In this work, we present a DNN library framework, SMaLL, that is easily extensible to new architectures. The framework uses a unified loop structure and shared, cache-friendly data format across all intermediate layers, eliminating the time and memory overheads incurred by data transformation between layers. Each layer is implemented by specifying its dimensions and a\n            <jats:italic>kernel<\/jats:italic>\n            , the key computing operation of that layer. The unified loop structure and kernel abstraction allows the reuse of code across layers and computing platforms. New architectures only require a few hundred lines in the kernel to be redesigned. To show the benefits of our approach, we have developed software that supports a range of layer types and computing platforms; this software is easily extensible for rapidly instantiating high-performance DNN libraries.\n          <\/jats:p>\n          <jats:p>An evaluation of the portability of our framework is shown by instantiating end-to-end networks from the MLPerf:tiny benchmark suite on five ARM platforms and one x86 platform (an AMD Zen 2). We also show that the end-to-end performance is comparable to or better than ML frameworks such as TensorFlow, TVM, and LibTorch.<\/jats:p>","DOI":"10.1145\/3607870","type":"journal-article","created":{"date-parts":[[2023,7,12]],"date-time":"2023-07-12T11:43:39Z","timestamp":1689162219000},"page":"1-25","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":0,"title":["SMaLL: Software for Rapidly Instantiating Machine Learning Libraries"],"prefix":"10.1145","volume":"23","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2416-3651","authenticated-orcid":false,"given":"Upasana","family":"Sridhar","sequence":"first","affiliation":[{"name":"ECE, Carnegie Mellon University, Pittsburgh, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-0421-4462","authenticated-orcid":false,"given":"Nicholai","family":"Tukanov","sequence":"additional","affiliation":[{"name":"ECE, Carnegie Mellon University, Pittsburgh, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3588-5606","authenticated-orcid":false,"given":"Elliott","family":"Binder","sequence":"additional","affiliation":[{"name":"ECE, Carnegie Mellon University, Pittsburgh, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5179-8249","authenticated-orcid":false,"given":"Tze Meng","family":"Low","sequence":"additional","affiliation":[{"name":"ECE, Carnegie Mellon University, Pittsburgh, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1868-5178","authenticated-orcid":false,"given":"Scott","family":"McMillan","sequence":"additional","affiliation":[{"name":"Software Engineering Institute, Carnegie Mellon University, Pittsburgh, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6059-0490","authenticated-orcid":false,"given":"Martin D.","family":"Schatz","sequence":"additional","affiliation":[{"name":"Meta, Menlo Park, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"320","published-online":{"date-parts":[[2024,5,13]]},"reference":[{"key":"e_1_3_3_2_2","article-title":"A matrix math facility for Power ISA(TM) processors","volume":"2104","author":"Moreira Jos\u00e9 E.","year":"2021","unstructured":"Jos\u00e9 E. Moreira, Kit Barton, Steven Battle, Peter Bergner, Ramon Bertran, Puneeth Bhat, Pedro Caldeira, David Edelsohn, Gordon C. Fossum, Brad Frey, Nemanja Ivanovic, Chip Kerchner, Vincent Lim, Shakti Kapoor, Tulio Machado Filho, Silvia Melitta Mueller, Brett Olsson, Satish Sadasivam, Baptiste Saleil, Bill Schmidt, Rajalakshmi Srinivasaraghavan, Shricharan Srivatsan, Brian W. Thompto, Andreas Wagner, and Nelson Wu. 2021. A matrix math facility for Power ISA(TM) processors. CoRR abs\/2104.03142 (2021).","journal-title":"CoRR"},{"key":"e_1_3_3_3_2","first-page":"1173","volume-title":"IEEE International Parallel and Distributed Processing Symposium (IPDPS\u201922)","author":"Tukanov Nicholai","year":"2022","unstructured":"Nicholai Tukanov, Rajalakshmi Srinivasaraghavan, Jos\u00e9 E. Moreira, and Tze Meng Low. 2022. Modeling matrix engines for portability and performance. In IEEE International Parallel and Distributed Processing Symposium (IPDPS\u201922). IEEE, 1173\u20131183."},{"key":"e_1_3_3_4_2","unstructured":"Nvidia Corporation. 2020. NVIDIA A100 Tensor Core GPU Architecture. Nvidia Corporation. Retrieved from https:\/\/images.nvidia.com\/aem-dam\/en-zz\/Solutions\/data-center\/nvidia-ampere-architecture-whitepaper.pdf"},{"key":"e_1_3_3_5_2","article-title":"Survey of machine learning accelerators","volume":"2009","author":"Reuther Albert","year":"2020","unstructured":"Albert Reuther, Peter Michaleas, Michael Jones, Vijay Gadepally, Siddharth Samsi, and Jeremy Kepner. 2020. Survey of machine learning accelerators. CoRR abs\/2009.00993 (2020).","journal-title":"CoRR"},{"key":"e_1_3_3_6_2","unstructured":"Mart\u00edn Abadi Ashish Agarwal Paul Barham Eugene Brevdo Zhifeng Chen Craig Citro Greg S. Corrado Andy Davis Jeffrey Dean Matthieu Devin Sanjay Ghemawat Ian Goodfellow Andrew Harp Geoffrey Irving Michael Isard Yangqing Jia Rafal Jozefowicz Lukasz Kaiser Manjunath Kudlur Josh Levenberg Dandelion Man\u00e9 Rajat Monga Sherry Moore Derek Murray Chris Olah Mike Schuster Jonathon Shlens Benoit Steiner Ilya Sutskever Kunal Talwar Paul Tucker Vincent Vanhoucke Vijay Vasudevan Fernanda Vi\u00e9gas Oriol Vinyals Pete Warden Martin Wattenberg Martin Wicke Yuan Yu and Xiaoqiang Zheng. 2015. TensorFlow: Large-scale Machine Learning on Heterogeneous Systems. Retrieved from https:\/\/www.tensorflow.org\/"},{"key":"e_1_3_3_7_2","first-page":"8024","volume-title":"Advances in Neural Information Processing Systems 32","author":"Paszke Adam","year":"2019","unstructured":"Adam Paszke, Sam Gross, Francisco Massa, Adam Lerer, James Bradbury, Gregory Chanan, Trevor Killeen, Zeming Lin, Natalia Gimelshein, Luca Antiga, Alban Desmaison, Andreas Kopf, Edward Yang, Zachary DeVito, Martin Raison, Alykhan Tejani, Sasank Chilamkurthy, Benoit Steiner, Lu Fang, Junjie Bai, and Soumith Chintala. 2019. PyTorch: An imperative style, high-performance deep learning library. In Advances in Neural Information Processing Systems 32, H. Wallach, H. Larochelle, A. Beygelzimer, F. d\u2019 Alch\u00e9-Buc, E. Fox, and R. Garnett (Eds.). Curran Associates, Inc., 8024\u20138035. Retrieved from http:\/\/papers.neurips.cc\/paper\/9015-pytorch-an-imperative-style-high-performance-deep-learning-library.pdf"},{"key":"e_1_3_3_8_2","unstructured":"Intel\u00ae oneAPI Deep Neural Network Library. 2016\u20132022. Retrieved from https:\/\/www.intel.com\/content\/www\/us\/en\/developer\/tools\/oneapi\/onednn.html"},{"key":"e_1_3_3_9_2","unstructured":"Liangzhen Lai Naveen Suda and Vikas Chandra. 2018. CMSIS-NN: Efficient Neural Network Kernels for Arm Cortex-M CPUs. arxiv:cs.NE\/1801.06601."},{"key":"e_1_3_3_10_2","volume-title":"10th International Workshop on Frontiers in Handwriting Recognition","author":"Chellapilla Kumar","year":"2006","unstructured":"Kumar Chellapilla, Sidd Puri, and Patrice Simard. 2006. High performance convolutional neural networks for document processing. In 10th International Workshop on Frontiers in Handwriting Recognition, Guy Lorette (Ed.). Universit\u00e9 de Rennes 1, Suvisoft, La Baule (France). Retrieved from: https:\/\/hal.inria.fr\/inria-00112631"},{"key":"e_1_3_3_11_2","doi-asserted-by":"crossref","first-page":"102806","DOI":"10.1016\/j.sysarc.2022.102806","article-title":"Reformulating the direct convolution for high-performance deep learning inference on ARM processors","volume":"135","author":"Barrachina Sergio","year":"2023","unstructured":"Sergio Barrachina, Adri\u00e1n Castell\u00f3, Manuel F. Dolz, Tze Meng Low, H\u00e9ctor Mart\u00ednez, Enrique S. Quintana-Ort\u00ed, Upasana Sridhar, and Andr\u00e9s E. Tom\u00e1s. 2023. Reformulating the direct convolution for high-performance deep learning inference on ARM processors. J. Syst. Archit. 135 (2023), 102806.","journal-title":"J. Syst. Archit."},{"key":"e_1_3_3_12_2","unstructured":"Tianqi Chen Thierry Moreau Ziheng Jiang Lianmin Zheng Eddie Yan Meghan Cowan Haichen Shen Leyuan Wang Yuwei Hu Luis Ceze Carlos Guestrin and Arvind Krishnamurthy. 2018. TVM: An Automated End-to-End Optimizing Compiler for Deep Learning. arxiv:cs.LG\/1802.04799."},{"key":"e_1_3_3_13_2","unstructured":"Chris Leary and Todd Wang. 2017. XLA: TensorFlow compiled. Retrieved from https:\/\/developers.googleblog.com\/2017\/03\/xla-tensorflow-compiled.html."},{"key":"e_1_3_3_14_2","article-title":"Glow: Graph lowering compiler techniques for neural networks","author":"Rotem Nadav","year":"2018","unstructured":"Nadav Rotem, Jordan Fix, Saleem Abdulrasool, Garret Catron, Summer Deng, Roman Dzhabarov, Nick Gibson, James Hegeman, Meghan Lele, Roman Levenstein, Jack Montgomery, Bert Maher, Satish Nadathur, Jakob Olesen, Jongsoo Park, Artem Rakhov, Misha Smelyanskiy, and Man Wang. 2018. Glow: Graph lowering compiler techniques for neural networks. arXiv preprint arXiv:1805.00907 (2018).","journal-title":"arXiv preprint arXiv:1805.00907"},{"key":"e_1_3_3_15_2","doi-asserted-by":"publisher","DOI":"10.1145\/2764454"},{"key":"e_1_3_3_16_2","doi-asserted-by":"publisher","DOI":"10.1145\/355841.355848"},{"key":"e_1_3_3_17_2","doi-asserted-by":"publisher","DOI":"10.1145\/42288.42291"},{"issue":"1","key":"e_1_3_3_18_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/77626.79170","article-title":"A set of level 3 basic linear algebra subprograms","volume":"16","author":"Dongarra Jack J.","year":"1990","unstructured":"Jack J. Dongarra, Jeremy Du Croz, Sven Hammarling, and Iain Duff. 1990. A set of level 3 basic linear algebra subprograms. ACM Trans. Math. Softw. 16, 1 (Mar. 1990), 1\u201317.","journal-title":"ACM Trans. Math. Softw."},{"key":"e_1_3_3_19_2","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1356052.1356053","article-title":"Anatomy of high-performance matrix multiplication","author":"Goto Kazushige","year":"2008","unstructured":"Kazushige Goto and Robert A. Van De Geijn. 2008. Anatomy of high-performance matrix multiplication. ACM Trans. Math. Softw. 34, 3 (2008), 1\u201325.","journal-title":"ACM Trans. Math. Softw."},{"key":"e_1_3_3_20_2","volume-title":"BLAS Based on Block Data Structures","author":"Henry Greg","year":"1992","unstructured":"Greg Henry. 1992. BLAS Based on Block Data Structures. Cornell University Technical Report."},{"key":"e_1_3_3_21_2","doi-asserted-by":"publisher","DOI":"10.1145\/2755561"},{"key":"e_1_3_3_22_2","doi-asserted-by":"publisher","DOI":"10.1145\/2925987"},{"key":"e_1_3_3_23_2","volume-title":"International Conference on Learning Representations","author":"Simonyan Karen","year":"2015","unstructured":"Karen Simonyan and Andrew Zisserman. 2015. Very deep convolutional networks for large-scale image recognition. In International Conference on Learning Representations."},{"key":"e_1_3_3_24_2","article-title":"Deep residual learning for image recognition","volume":"1512","author":"He Kaiming","year":"2015","unstructured":"Kaiming He, Xiangyu Zhang, Shaoqing Ren, and Jian Sun. 2015. Deep residual learning for image recognition. CoRR abs\/1512.03385 (2015).","journal-title":"CoRR"},{"key":"e_1_3_3_25_2","first-page":"1","volume-title":"IEEE Conference on Computer Vision and Pattern Recognition (CVPR\u201915)","author":"Szegedy Christian","year":"2015","unstructured":"Christian Szegedy, Wei Liu, Yangqing Jia, Pierre Sermanet, Scott Reed, Dragomir Anguelov, Dumitru Erhan, Vincent Vanhoucke, and Andrew Rabinovich. 2015. Going deeper with convolutions. In IEEE Conference on Computer Vision and Pattern Recognition (CVPR\u201915). 1\u20139. DOI:10.1109\/CVPR.2015.7298594"},{"key":"e_1_3_3_26_2","first-page":"5776","volume-title":"International Conference on Machine Learning","author":"Zhang Jiyuan","year":"2018","unstructured":"Jiyuan Zhang, Franz Franchetti, and Tze Meng Low. 2018. High performance zero-memory overhead direct convolutions. In International Conference on Machine Learning. PMLR, 5776\u20135785."},{"key":"e_1_3_3_27_2","doi-asserted-by":"publisher","DOI":"10.1145\/2925987"},{"key":"e_1_3_3_28_2","unstructured":"Robert Triggs. Qualcomm Snapdragon 888 deep dive: Everything you need to know. Retrieved from https:\/\/www.androidauthority.com\/qualcomm-snapdragon-888-1179156\/"},{"key":"e_1_3_3_29_2","unstructured":"Qualcomm Corporation. 2020. Snapdragon 888 Specifications. Qualcomm Corporation. Retrieved from https:\/\/www.qualcomm.com\/products\/application\/smartphones\/snapdragon-8-series-mobile-platforms\/snapdragon-888-5g-mobile-platform"},{"key":"e_1_3_3_30_2","unstructured":"Arduino. 2022. Arduino IDE Version 2.0.3. Retrieved from https:\/\/www.arduino.cc\/en\/software"},{"key":"e_1_3_3_31_2","unstructured":"Intel\u00ae Intrinsics Guide. 2023. Retrieved from https:\/\/www.intel.com\/content\/www\/us\/en\/docs\/intrinsics-guide\/index.html"},{"key":"e_1_3_3_32_2","unstructured":"TensorFlow Lite | ML for Mobile and Edge Devices. 2023. Retrieved from https:\/\/www.tensorflow.org\/lite\/"},{"key":"e_1_3_3_33_2","article-title":"Learning to optimize tensor programs","volume":"31","author":"Chen Tianqi","year":"2018","unstructured":"Tianqi Chen, Lianmin Zheng, Eddie Yan, Ziheng Jiang, Thierry Moreau, Luis Ceze, Carlos Guestrin, and Arvind Krishnamurthy. 2018. Learning to optimize tensor programs. Adv. Neural Inf. Process. Syst. 31 (2018).","journal-title":"Adv. Neural Inf. Process. Syst."},{"key":"e_1_3_3_34_2","unstructured":"Qualcomm Corporation. 2023. Snapdragon Neural Processing Engine SDK. Qualcomm Corporation. Retrieved from https:\/\/developer.qualcomm.com\/sites\/default\/files\/docs\/snpe\/overview.html"},{"key":"e_1_3_3_35_2","unstructured":"Arduino. 2020. Arduino Command Line Interface 0.30. Retrieved from https:\/\/arduino.github.io\/arduino-cli\/0.30\/"},{"key":"e_1_3_3_36_2","article-title":"MLPerf tiny benchmark","author":"Banbury Colby","year":"2021","unstructured":"Colby Banbury, Vijay Janapa Reddi, Peter Torelli, Jeremy Holleman, Nat Jeffries, Csaba Kiraly, Pietro Montino, David Kanter, Sebastian Ahmed, Danilo Pau, Urmish Thakker, Antonio Torrini, Peter Warden, Jay Cordaro, Giuseppe Di Guglielmo, Javier Duarte, Stephen Gibellini, Videet Parekh, Honson Tran, Nhan Tran, Niu Wenxu, and Xu Xuesong. 2021. MLPerf tiny benchmark. In Neural Information Processing Systems Track on Datasets and Benchmarks.","journal-title":"Neural Information Processing Systems Track on Datasets and Benchmarks"},{"key":"e_1_3_3_37_2","article-title":"MobileNets: Efficient convolutional neural networks for mobile vision applications","volume":"1704","author":"Howard Andrew G.","year":"2017","unstructured":"Andrew G. Howard, Menglong Zhu, Bo Chen, Dmitry Kalenichenko, Weijun Wang, Tobias Weyand, Marco Andreetto, and Hartwig Adam. 2017. MobileNets: Efficient convolutional neural networks for mobile vision applications. CoRR abs\/1704.04861 (2017).","journal-title":"CoRR"},{"issue":"1","key":"e_1_3_3_38_2","first-page":"1","article-title":"A depthwise separable convolutional neural network for keyword spotting on an embedded system","volume":"2020","author":"S\u00f8rensen Peter M\u00f8lgaard","year":"2020","unstructured":"Peter M\u00f8lgaard S\u00f8rensen, Bastian Epp, and Tobias May. 2020. A depthwise separable convolutional neural network for keyword spotting on an embedded system. EURASIP J. Audio, Speech Music Process. 2020, 1 (2020), 1\u201314.","journal-title":"EURASIP J. Audio, Speech Music Process."},{"key":"e_1_3_3_39_2","first-page":"501","article-title":"Rigid-motion scattering for texture classification","volume":"3559","author":"Sifre L.","year":"2014","unstructured":"L. Sifre and St\u00e9phane Mallat. 2014. Rigid-motion scattering for texture classification. Comput. Sci. 3559 (2014), 501\u2013515.","journal-title":"Comput. Sci."},{"key":"e_1_3_3_40_2","unstructured":"Keras. 2022. Retrieved from https:\/\/keras.io\/"},{"key":"e_1_3_3_41_2","unstructured":"Tensorflow. 2022. Performance Measurement with TF-Lite. Tensorflow. Retrieved from https:\/\/www.tensorflow.org\/lite\/performance\/measurement"},{"key":"e_1_3_3_42_2","first-page":"318","volume-title":"Conference on Programming Language Design and Implementation","author":"Lam Monica","year":"1988","unstructured":"Monica Lam. 1988. Software pipelining: An effective scheduling technique for VLIW machines. In Conference on Programming Language Design and Implementation. 318\u2013328."},{"key":"e_1_3_3_43_2","article-title":"Post-training 4-bit quantization of convolution networks for rapid-deployment","author":"Banner Ron","year":"2018","unstructured":"Ron Banner, Yury Nahshan, Elad Hoffer, and Daniel Soudry. 2018. Post-training 4-bit quantization of convolution networks for rapid-deployment. arXiv preprint arXiv:1810.05723 (2018).","journal-title":"arXiv preprint arXiv:1810.05723"},{"key":"e_1_3_3_44_2","unstructured":"Advanced AI Embedded Systems. 2023. Retrieved from https:\/\/www.nvidia.com\/en-us\/autonomous-machines\/embedded-systems\/"},{"key":"e_1_3_3_45_2","unstructured":"Hexagon DSP Processor. 2023. Retrieved from https:\/\/developer.qualcomm.com\/software\/hexagon-dsp-sdk\/dsp-processor"},{"key":"e_1_3_3_46_2","article-title":"BERT: Pre-training of deep bidirectional transformers for language understanding","author":"Devlin Jacob","year":"2018","unstructured":"Jacob Devlin, Ming-Wei Chang, Kenton Lee, and Kristina Toutanova. 2018. BERT: Pre-training of deep bidirectional transformers for language understanding. arXiv preprint arXiv:1810.04805 (2018).","journal-title":"arXiv preprint arXiv:1810.04805"},{"key":"e_1_3_3_47_2","article-title":"Attention is all you need","volume":"30","author":"Vaswani Ashish","year":"2017","unstructured":"Ashish Vaswani, Noam Shazeer, Niki Parmar, Jakob Uszkoreit, Llion Jones, Aidan N. Gomez, \u0141ukasz Kaiser, and Illia Polosukhin. 2017. Attention is all you need. Adv. Neural Inf. Process. Syst. 30 (2017).","journal-title":"Adv. Neural Inf. Process. Syst."}],"container-title":["ACM Transactions on Embedded Computing Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3607870","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3607870","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T16:37:06Z","timestamp":1750178226000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3607870"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,5,13]]},"references-count":46,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2024,5,31]]}},"alternative-id":["10.1145\/3607870"],"URL":"https:\/\/doi.org\/10.1145\/3607870","relation":{},"ISSN":["1539-9087","1558-3465"],"issn-type":[{"type":"print","value":"1539-9087"},{"type":"electronic","value":"1558-3465"}],"subject":[],"published":{"date-parts":[[2024,5,13]]},"assertion":[{"value":"2022-11-01","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-06-09","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2024-05-13","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}