{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,7]],"date-time":"2026-03-07T00:59:40Z","timestamp":1772845180189,"version":"3.50.1"},"publisher-location":"New York, NY, USA","reference-count":70,"publisher":"ACM","license":[{"start":{"date-parts":[[2023,9,17]],"date-time":"2023-09-17T00:00:00Z","timestamp":1694908800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.acm.org\/publications\/policies\/copyright_policy#Background"}],"funder":[{"name":"German Research Foundation (Deutsche Forschungsgemeinschaft)","award":["SPP 2377"],"award-info":[{"award-number":["SPP 2377"]}]},{"name":"German Research Foundation (Deutsche Forschungsgemeinschaft)","award":["405422836"],"award-info":[{"award-number":["405422836"]}]},{"name":"Ministry of Science and Technology of Taiwan","award":["MOST-111-2923-E-002-014-MY3"],"award-info":[{"award-number":["MOST-111-2923-E-002-014-MY3"]}]},{"name":"Ministry of Science and Technology of Taiwan","award":["MOST-111-2218-E-002-026"],"award-info":[{"award-number":["MOST-111-2218-E-002-026"]}]},{"name":"Ministry of Science and Technology of Taiwan","award":["MOST-109-2221-E-002-147-MY3"],"award-info":[{"award-number":["MOST-109-2221-E-002-147-MY3"]}]},{"name":"Ministry of Science and Technology of Taiwan","award":["MOST-109-2221-E-001-012-MY3"],"award-info":[{"award-number":["MOST-109-2221-E-001-012-MY3"]}]},{"name":"Ministry of Science and Technology of Taiwan","award":["NSTC-112-2218-E-002-025-MBK"],"award-info":[{"award-number":["NSTC-112-2218-E-002-025-MBK"]}]},{"name":"Macronix Inc., Taiwan","award":["111HT912003"],"award-info":[{"award-number":["111HT912003"]}]}],"content-domain":{"domain":["dl.acm.org"],"crossmark-restriction":true},"short-container-title":[],"published-print":{"date-parts":[[2023,9,17]]},"DOI":"10.1145\/3607889.3609088","type":"proceedings-article","created":{"date-parts":[[2024,1,24]],"date-time":"2024-01-24T14:16:49Z","timestamp":1706105809000},"page":"11-20","update-policy":"https:\/\/doi.org\/10.1145\/crossmark-policy","source":"Crossref","is-referenced-by-count":2,"title":["Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications"],"prefix":"10.1145","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9602-2922","authenticated-orcid":false,"given":"Jorg","family":"Henkel","sequence":"first","affiliation":[{"name":"Karlsruhe Institute of Technology, Karlsruhe, Karlsruhe, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5312-8679","authenticated-orcid":false,"given":"Lokesh","family":"Siddhu","sequence":"additional","affiliation":[{"name":"Karlsruhe Institute of Technology, Karlsruhe, Karlsruhe, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0253-4594","authenticated-orcid":false,"given":"Lars","family":"Bauer","sequence":"additional","affiliation":[{"name":"Karlsruhe Institute of Technology, Karlsruhe, Karlsruhe, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6285-5862","authenticated-orcid":false,"given":"Jurgen","family":"Teich","sequence":"additional","affiliation":[{"name":"Friedrich-Alexander-Universitat, Erlangen, Erlangen, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4324-2187","authenticated-orcid":false,"given":"Stefan","family":"Wildermann","sequence":"additional","affiliation":[{"name":"Friedrich-Alexander-Universitat, Erlangen, Erlangen, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8829-5610","authenticated-orcid":false,"given":"Mehdi","family":"Tahoori","sequence":"additional","affiliation":[{"name":"Karlsruhe Institute of Technology, Karlsruhe, Karlsruhe, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6084-9810","authenticated-orcid":false,"given":"Mahta","family":"Mayahinia","sequence":"additional","affiliation":[{"name":"Karlsruhe Institute of Technology, Karlsruhe, Karlsruhe, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5007-445X","authenticated-orcid":false,"given":"Jeronimo","family":"Castrillon","sequence":"additional","affiliation":[{"name":"TU Dresden, Dresden, Dresden, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5130-9855","authenticated-orcid":false,"given":"Asif Ali","family":"Khan","sequence":"additional","affiliation":[{"name":"TU Dresden, Dresden, Dresden, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1780-6217","authenticated-orcid":false,"given":"Hamid","family":"Farzaneh","sequence":"additional","affiliation":[{"name":"TU Dresden, Dresden, Dresden, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9295-3519","authenticated-orcid":false,"given":"Joao Paulo C. De","family":"Lima","sequence":"additional","affiliation":[{"name":"TU Dresden, Dresden, Dresden, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8114-9760","authenticated-orcid":false,"given":"Jian-Jia","family":"Chen","sequence":"additional","affiliation":[{"name":"TU Dortmund University, Dortmund, Dortmund, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9992-9415","authenticated-orcid":false,"given":"Christian","family":"Hakert","sequence":"additional","affiliation":[{"name":"TU Dortmund University, Dortmund, Dortmund, Germany"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7110-921X","authenticated-orcid":false,"given":"Kuan-Hsun","family":"Chen","sequence":"additional","affiliation":[{"name":"University of Twente, Enschede, Enschede, Netherlands"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0091-5027","authenticated-orcid":false,"given":"Chia-Lin","family":"Yang","sequence":"additional","affiliation":[{"name":"National Taiwan University, Taipei, Taipei, Taiwan"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8983-9835","authenticated-orcid":false,"given":"Hsiang-Yun","family":"Cheng","sequence":"additional","affiliation":[{"name":"Academia Sinica, Nanking, Taipei, Taiwan"}]}],"member":"320","published-online":{"date-parts":[[2024,1,24]]},"reference":[{"key":"e_1_3_2_1_1_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICRC.2018.8638612"},{"key":"e_1_3_2_1_2_1","doi-asserted-by":"crossref","unstructured":"A. Ankit et al. 2019. PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference. In Int. Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS). 715--731.","DOI":"10.1145\/3297858.3304049"},{"key":"e_1_3_2_1_3_1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2020.2975719"},{"key":"e_1_3_2_1_4_1","volume-title":"Automation & Test in Europe Conf. (DATE). 673--678","author":"Buschj\u00e4ger S.","year":"2021","unstructured":"S. Buschj\u00e4ger, et al. 2021. Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance. In Design, Automation & Test in Europe Conf. (DATE). 673--678."},{"key":"e_1_3_2_1_5_1","doi-asserted-by":"publisher","DOI":"10.1109\/ICDM.2018.00017"},{"key":"e_1_3_2_1_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2710627"},{"key":"e_1_3_2_1_7_1","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228439"},{"key":"e_1_3_2_1_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2789723"},{"key":"e_1_3_2_1_9_1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2537400"},{"key":"e_1_3_2_1_10_1","volume-title":"DTC: A Drift-Tolerant Coding to Improve the Performance and Energy Efficiency of Multi-Level-Cell Phase-Change Memory","author":"Chen Y.-S.","year":"2023","unstructured":"Y.-S. Chen, et al. 2023. DTC: A Drift-Tolerant Coding to Improve the Performance and Energy Efficiency of Multi-Level-Cell Phase-Change Memory. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (2023)."},{"key":"e_1_3_2_1_11_1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474229"},{"key":"e_1_3_2_1_12_1","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669157"},{"key":"e_1_3_2_1_13_1","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630086"},{"key":"e_1_3_2_1_14_1","volume-title":"TC-CIM: Empowering Tensor Comprehensions for Computing-In-Memory. In Int. Workshop on Polyhedral Compilation Techniques.","author":"Drebes A.","year":"2020","unstructured":"A. Drebes, et al. 2020. TC-CIM: Empowering Tensor Comprehensions for Computing-In-Memory. In Int. Workshop on Polyhedral Compilation Techniques."},{"key":"e_1_3_2_1_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/2592798.2592814"},{"key":"e_1_3_2_1_16_1","volume-title":"Automation & Test in Europe Conf. (DATE). 914--919","author":"Ferreira A. P.","year":"2010","unstructured":"A. P. Ferreira, et al. 2010. Increasing PCM main memory lifetime. In Design, Automation & Test in Europe Conf. (DATE). 914--919."},{"key":"e_1_3_2_1_17_1","volume-title":"In-Memory Data Parallel Processor. In Int. Conf. on Arch. Support for Programming Languages and Operating Systems (ASPLOS). 1--14","author":"Fujiki D.","year":"2018","unstructured":"D. Fujiki, et al. 2018. In-Memory Data Parallel Processor. In Int. Conf. on Arch. Support for Programming Languages and Operating Systems (ASPLOS). 1--14."},{"key":"e_1_3_2_1_18_1","volume-title":"Software Wear Management for Persistent Memories. In Conf. on File and Storage Technologies (FAST). 45--63","author":"Gogte V.","year":"2019","unstructured":"V. Gogte, et al. 2019. Software Wear Management for Persistent Memories. In Conf. on File and Storage Technologies (FAST). 45--63."},{"key":"e_1_3_2_1_19_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3174101"},{"key":"e_1_3_2_1_20_1","doi-asserted-by":"publisher","DOI":"10.1145\/3483839"},{"key":"e_1_3_2_1_21_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586167"},{"key":"e_1_3_2_1_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2022.3197094"},{"key":"e_1_3_2_1_23_1","unstructured":"D. Hernandez. 2020. Measuring the Algorithmic Efficiency of Neural Networks. arXiv:2005.04305 [cs.LG]"},{"key":"e_1_3_2_1_24_1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342009"},{"key":"e_1_3_2_1_25_1","volume-title":"Challenges and future directions for energy, latency, and lifetime improvements in NVMs. Distributed and Parallel Databases","author":"Kargar S.","year":"2022","unstructured":"S. Kargar. 2022. Challenges and future directions for energy, latency, and lifetime improvements in NVMs. Distributed and Parallel Databases (2022), 1--27."},{"key":"e_1_3_2_1_26_1","unstructured":"A. A. Khan et al. 2023. CINM (Cinnamon): A Compilation Infrastructure for Heterogeneous Compute In-Memory and Compute Near-Memory Paradigms. arXiv preprint arXiv:2301.07486 (2023)."},{"key":"e_1_3_2_1_27_1","doi-asserted-by":"crossref","unstructured":"A. A. Khan et al. 2019. ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0. ACM Transactions on Architecture and Code Optimization (TACO) 16 4 Article 56 (2019) 23 pages.","DOI":"10.1145\/3372489"},{"key":"e_1_3_2_1_28_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2022.02.043"},{"key":"e_1_3_2_1_29_1","volume-title":"MLIR: Scaling Compiler Infrastructure for Domain Specific Computation. In Intl. Symp. on Code Generation and Optimization (CGO). 2--14","author":"Lattner C.","year":"2021","unstructured":"C. Lattner, et al. 2021. MLIR: Scaling Compiler Infrastructure for Domain Specific Computation. In Intl. Symp. on Code Generation and Optimization (CGO). 2--14."},{"key":"e_1_3_2_1_30_1","article-title":"A System-Level Simulator for RRAM-Based Neuromorphic Computing Chips","volume":"15","author":"Lee M. K. F.","year":"2019","unstructured":"M. K. F. Lee, et al. 2019. A System-Level Simulator for RRAM-Based Neuromorphic Computing Chips. ACM Trans. on Architecture and Code Optimization (TACO) 15, 4, Article 64 (2019), 24 pages.","journal-title":"ACM Trans. on Architecture and Code Optimization (TACO)"},{"key":"e_1_3_2_1_31_1","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415663"},{"key":"e_1_3_2_1_32_1","doi-asserted-by":"crossref","unstructured":"Q. Li et al. 2013. Compiler directed write-mode selection for high performance low power volatile PCM. In Languages Compilers and Tools for Embedded Systems (LCTES). 101--110.","DOI":"10.1145\/2499369.2465564"},{"key":"e_1_3_2_1_33_1","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287715"},{"key":"e_1_3_2_1_34_1","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240800"},{"key":"e_1_3_2_1_35_1","doi-asserted-by":"publisher","DOI":"10.1145\/3507639"},{"key":"e_1_3_2_1_36_1","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2747910"},{"key":"e_1_3_2_1_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2015.88"},{"key":"e_1_3_2_1_38_1","volume-title":"SHRIMP: Efficient Instruction Delivery with Domain Wall Memory. In Int. Symp. on Low Power Electronics and Design (ISLPED). 1--6.","author":"Multanen J.","year":"2019","unstructured":"J. Multanen, et al. 2019. SHRIMP: Efficient Instruction Delivery with Domain Wall Memory. In Int. Symp. on Low Power Electronics and Design (ISLPED). 1--6."},{"key":"e_1_3_2_1_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/UV50937.2020.9426214"},{"key":"e_1_3_2_1_40_1","doi-asserted-by":"publisher","DOI":"10.1145\/3063130"},{"key":"e_1_3_2_1_41_1","doi-asserted-by":"crossref","unstructured":"G. Pedretti et al. 2021. Tree-based machine learning performed in-memory with memristive analog CAM. Nature communications 12 1 (October 2021) 5806.","DOI":"10.1038\/s41467-021-25873-0"},{"key":"e_1_3_2_1_42_1","volume-title":"Enhancing Lifetime and Security of PCM-based Main Memory with Start-gap Wear Leveling. In Int. Symp. on Microarch. 14--23","author":"Qureshi M. K.","year":"2009","unstructured":"M. K. Qureshi, et al. 2009. Enhancing Lifetime and Security of PCM-based Main Memory with Start-gap Wear Leveling. In Int. Symp. on Microarch. 14--23."},{"key":"e_1_3_2_1_43_1","volume-title":"Scalable High Performance Main Memory System Using Phase-Change Memory Technology. In Int. Symp. on Computer Arch. 24--33","author":"Qureshi M. K.","year":"2009","unstructured":"M. K. Qureshi, et al. 2009. Scalable High Performance Main Memory System Using Phase-Change Memory Technology. In Int. Symp. on Computer Arch. 24--33."},{"key":"e_1_3_2_1_44_1","doi-asserted-by":"crossref","unstructured":"A. Sebastian et al. 2020. Memory devices and applications for in-memory computing. Nature nanotechnology 15 7 (2020) 529--544.","DOI":"10.1038\/s41565-020-0655-z"},{"key":"e_1_3_2_1_45_1","volume-title":"ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars. In Int. Symp. on Computer Arch. 14--26","author":"Shafiee A.","year":"2016","unstructured":"A. Shafiee, et al. 2016. ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars. In Int. Symp. on Computer Arch. 14--26."},{"key":"e_1_3_2_1_46_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3101464"},{"key":"e_1_3_2_1_47_1","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2018.00106"},{"key":"e_1_3_2_1_48_1","volume-title":"Seque: Lean and Energy-aware Data Management for IoT Gateways. In Int. Conf. on Edge Computing and Communications.","author":"Sixdenier P.-L. A. E.","year":"2023","unstructured":"P.-L. A. E. Sixdenier, et al. 2023. Seque: Lean and Energy-aware Data Management for IoT Gateways. In Int. Conf. on Edge Computing and Communications."},{"key":"e_1_3_2_1_49_1","unstructured":"D. Stutz et al. 2021. Bit Error Robustness for Energy-Efficient DNN Accelerators. In Machine Learning and Systems (MLSys). 569--598."},{"key":"e_1_3_2_1_50_1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488799"},{"key":"e_1_3_2_1_51_1","volume-title":"RePIM: Joint Exploitation of Activation and Weight Repetitions for In-ReRAM DNN Acceleration. In Design Automation Conf. (DAC). 589--594","author":"Tsai C.-Y.","year":"2021","unstructured":"C.-Y. Tsai, et al. 2021. RePIM: Joint Exploitation of Activation and Weight Repetitions for In-ReRAM DNN Acceleration. In Design Automation Conf. (DAC). 589--594."},{"key":"e_1_3_2_1_52_1","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC52403.2022.9712536"},{"key":"e_1_3_2_1_53_1","unstructured":"Upmem. 2022. UPMEM Processing In-Memory (PIM): Ultra-efficient acceleration for data-intensive applications. In 2022 UPMEM PIM Tech paper v2.7. 1--22."},{"key":"e_1_3_2_1_54_1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116464"},{"key":"e_1_3_2_1_55_1","doi-asserted-by":"publisher","DOI":"10.1145\/3396236"},{"key":"e_1_3_2_1_56_1","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3358191","article-title":"Achieving lossless accuracy with lossy programming for efficient neural-network training on NVM-based systems","volume":"18","author":"Wang W.-C.","year":"2019","unstructured":"W.-C. Wang, et al. 2019. Achieving lossless accuracy with lossy programming for efficient neural-network training on NVM-based systems. ACM Trans. on Embedded Computing Systems (TECS) 18, 5s (2019), 1--22.","journal-title":"ACM Trans. on Embedded Computing Systems (TECS)"},{"key":"e_1_3_2_1_57_1","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835933"},{"key":"e_1_3_2_1_58_1","article-title":"WADE: Writeback-Aware Dynamic Cache Management for NVM-Based Main Memory System","volume":"10","author":"Wang Z.","year":"2013","unstructured":"Z. Wang, et al. 2013. WADE: Writeback-Aware Dynamic Cache Management for NVM-Based Main Memory System. ACM Trans. on Architecture and Code Optimization (TACO) 10, 4, Article 51 (dec 2013), 21 pages.","journal-title":"ACM Trans. on Architecture and Code Optimization (TACO)"},{"key":"e_1_3_2_1_59_1","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0549"},{"key":"e_1_3_2_1_60_1","volume-title":"Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing. In Computer Society Symp. on VLSI (ISVLSI). 176--181","author":"Xie L.","year":"2017","unstructured":"L. Xie, et al. 2017. Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing. In Computer Society Symp. on VLSI (ISVLSI). 176--181."},{"key":"e_1_3_2_1_61_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.2890257"},{"key":"e_1_3_2_1_62_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3185548"},{"key":"e_1_3_2_1_63_1","doi-asserted-by":"crossref","unstructured":"Y. Xu et al. 2017. Energy-Efficient Cache Management for NVM-Based IoT Systems. In Int. Symp. on Parallel and Distributed Processing with Applications and Int. Conf. on Ubiquitous Computing and Communications (ISPA\/IUCC). 491--493.","DOI":"10.1109\/ISPA\/IUCC.2017.00081"},{"key":"e_1_3_2_1_64_1","doi-asserted-by":"publisher","DOI":"10.1145\/3307650.3322271"},{"key":"e_1_3_2_1_65_1","doi-asserted-by":"publisher","DOI":"10.1145\/3531437.3539709"},{"key":"e_1_3_2_1_66_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3104736"},{"key":"e_1_3_2_1_67_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2019.2900036"},{"key":"e_1_3_2_1_68_1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218638"},{"key":"e_1_3_2_1_69_1","doi-asserted-by":"publisher","DOI":"10.1145\/3330345.3330387"},{"key":"e_1_3_2_1_70_1","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"}],"event":{"name":"CASES '23 Companion: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems","location":"Hamburg Germany","acronym":"CASES '23 Companion","sponsor":["SIGBED ACM Special Interest Group on Embedded Systems","SIGDA ACM Special Interest Group on Design Automation","SIGMICRO ACM Special Interest Group on Microarchitectural Research and Processing","CEDA","IEEE CAS"]},"container-title":["Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems"],"original-title":[],"link":[{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3607889.3609088","content-type":"unspecified","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/dl.acm.org\/doi\/pdf\/10.1145\/3607889.3609088","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,17]],"date-time":"2025-06-17T16:37:06Z","timestamp":1750178226000},"score":1,"resource":{"primary":{"URL":"https:\/\/dl.acm.org\/doi\/10.1145\/3607889.3609088"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,9,17]]},"references-count":70,"alternative-id":["10.1145\/3607889.3609088","10.1145\/3607889"],"URL":"https:\/\/doi.org\/10.1145\/3607889.3609088","relation":{},"subject":[],"published":{"date-parts":[[2023,9,17]]},"assertion":[{"value":"2024-01-24","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}